Fullscreen HTML5Med Res (??MB)HTML4

Teach-In 2026 by Mike Tooley World of Wireless – An Introduction to Radio and Wireless Technology, part 12.9 RF sources and oscillators L ast month, our focus shifted to frequency conversion methods used in both receivers and transmitters, with particular emphasis on how multipliers and mixers provide us with a means of changing the frequency of a signal. This month, we take a deep dive into RF sources, explaining how to get the best out of a variety of phaselocked loop (PLL) signal and marker/ generator modules, plus direct digital synthesis (DDS) chips. Our Hands-On constructional project is an accurate calibration source and programmable frequency marker. Free-running RF oscillators In the December 2025 issue, the part 2 article (“Introducing RF components and circuits”) briefly mentioned some basic RF oscillators that use quartz crystals as the frequency-determining element. These circuits included the popular Pierce, Colpitts, Miller and Franklin oscillator configurations. Since there’s no attempt to regulate the output frequency, these arrangements can all be described as ‘free running’. Free-running oscillators are found in many applications, but their use is constrained by the quality and accuracy of the frequencydetermining elements, including the effects of temperature, supply voltage and ageing. Before we move on to investigate oscillator stability and methods of frequency control, let’s look at one more type of free-running oscillator that offers several advantages over the Colpitts oscillator that we’ve previously used. signals over a relatively narrow tuning range. For applications needing a much wider tuning range and good frequency stability, you might prefer the Franklin oscillator configuration (see Fig.9.1). It requires two separate stages, making it a little more elaborate than the Colpitts arrangement. The advantage is that the tuned circuit components (L1 and C1) can be very loosely coupled to the two active devices. The circuit employs two N-channel junction gate field-effect transistors (JFETs), TR1 and TR2, with a third insulated-gate FET (Mosfet TR3) configured as a source follower to improve isolation and supply enough current to drive a relatively low-impedance load at the output. The Franklin oscillator employs a conventional parallel resonant circuit composed of L1 and C1. To improve frequency stability, the resonant circuit is minimally coupled to the active components through low-value capacitors C2 and C3. With appropriate changes to component values, the arrangement shown in Fig.9.1 is suitable for operation from below 100kHz to well over 50MHz. Fig.9.2 shows a practical realisation of Fig.9.1. Where C1 is a conventional variable capacitor that can R4 150Ω Fig.9.1: the wide-range Franklin oscillator arrangement. C2 22pF d g L1 TR1 BF245C s C1 C3 22pF R2 100kΩ L2 1mH d g TR2 BF245C s R1 1kΩ R3 470kΩ TR3 2N7000 d g s VR1 2kΩ C5 47uF + C4 100nF +12V + C6 47uF D1 8.2V SK1 Output GND 2N7000 buffer Fig.9.2: a practical realisation of Fig.9.2 (L1 and C1 are external). 9V shunt Zener regulator 2 × BF245C Franklin oscillator DC supply L-C tuned circuit (off-board) The Franklin oscillator Earlier in the series, we used a simple Colpitts oscillator to generate RF 56 Output level adjustment RF output Practical Electronics | July | 2026 Fig.9.3: a Tina-TI simulation of the Franklin oscillator with L and C values chosen for operation at 5MHz. be adjusted from 10pF to 290pF, the values required for L1 (not shown in Fig.9.2) can be determined from Table 9.1. This makes the circuit ideal for use as the basis of a general-purpose RF signal generator with several switched ranges. Fig.9.3 shows the Tina-TI simulation of the Franklin oscillator in Fig.9.1. For simplicity, we’ve replaced the preset output amplitude control (RV1) with a fixed resistor. The values of C1 and L1 (100pF and 10µH respectively) were chosen so that the tuned circuit is resonant at approximately 5MHz. Tina’s virtual oscilloscope indicates that the circuit produces an output of approximately 1.5V peak-to-peak with a period of around 200ns. Tina-TI can be used to investigate the working frequency range of the Franklin oscillator in Fig.9.3. Start by experimenting with the values of L1 and C1 (see Table 9.1) and also try reducing the values of the coupling capacitors, C2 and C3, to provide greater isolation for the resonant circuit. It is informative to observe the effect of reducing the load impedance, RL, on the output waveform. When Out C3 1n P1-3 Tune VR1 10k R1 100k P1-2 TR2 2N7000 L + C8 100u Com. d P2-3 s C5 270p + P2-2 In g L1 R2 3.3u 220k D1 1SV149 C e C4 270p C7 100u c b C2 10n C1 100n P1-1 TR1 PN2222 R4 220k IC1 78L09 R3 2.2k RV1 500 SK1 Output C6 100n P2-1 Fig.9.4: an electronically tuned Colpitts oscillator. 2N7000 buffer PN2222 Colpitts oscillator 78L09 voltage regulator Fig.9.5: a practical realisation of Fig.9.4. DC supply Tuning voltage RF output 1SV149 variable capacitance diode Practical Electronics | July | 2026 Output level adjustment + the output voltage has fallen to half its open-circuit value, the oscillator’s output impedance will be equal to the value of RL. To obtain a specific output frequency from the circuit in Fig.9.3, you can determine the values of L1 and C1 using the formula on page 4 of the December 2025 issue: f0 = 1 ÷ 2π√LC. Click on L1 and C1 in the Tina simulation to change their values and observe the effect on the output period and waveform. Electronic tuning Up to now, our variable RF oscillators have all relied on mechanical tuning of the variable capacitor used in the frequency-determining LC resonant circuit. Variable capacitors can be large and costly; they’re also unsuitable for situations where automatic frequency control (AFC) is needed. A different approach is to use electronic tuning based on a variable capacitance diode (also known as a ‘varicap’ or ‘varactor’). Figs.9.4 & 9.5 show a Colpitts oscillator with electronic tuning via a variable capacitance diode. The tuned circuit is L1 (a 3.3µH inductor) in parallel with the series combination of C2 (a 10nF capacitor) and D1 (a 1SV149 variable capacitance diode). Table 9.1: inductances for Franklin oscillator with 10-290pF capacitance Inductance Approximate tuning range 150µH 0.9-2.5MHz 33µH 1.8-5.2MHz 6.8µH 3.2-12.4MHz 3.3µH 5.2-16.5MHz 1µH 9.3-27.6MHz 57 Frequency (kHz) Frequency (kHz) Improved RF signal generating techniques 7528 7500 7527 7000 7526 6500 7525 6000 7524 5500 7523 5000 7522 4500 0 2 4 6 8 10 Tuning voltage (V) Fig.9.6: output frequency plotted against tuning voltage for the electronically tuned Colpitts oscillator shown in Fig.9.4. D1 is operated in a reverse-biased state, with variable DC voltage from the tuning control, VR1. This takes advantage of the varicap’s relatively large variation in capacitance with reverse-bias voltage. To promote frequency stability, the bias voltage is derived from a three-terminal 78L09 voltage regulator. The 1SV149 variable-capacitance diode has a capacitance of about 450pF with an applied reverse bias of 1V DC, progressively falling to around 20pF when this reaches 9V. With the values in Fig.9.4, this variation in capacitance results in an overall 3MHz tuning range, from about 4.5MHz (4500kHz) to around 7.5MHz (7500kHz), as illustrated in Fig.9.6. Linearity and frequency error Fig.9.6 demonstrates the impact of non-linearity at both ends of the electronic tuning range of our modified Colpitts oscillator. However, if the tuning voltage can be limited to a narrower band, such as 4-7V, its linearity is significantly improved. Linearity is the ratio between observed frequency error and overall tuning range, expressed as a percentage. Limiting the tuning range as suggested results in a frequency excursion of around 1.5MHz, with a significantly improved linearity of around ±3.3%. Drift Drift is another undesirable characteristic of all free-running oscillators. Drift is the variation of output frequency with time due to temperature changes, and is usually specified in Hz or kHz per unit time. Drift is often characterised as either short-term or long-term. Short-term 58 0 2 4 6 8 10 12 Time (min.) Fig.9.7: oscillator drift for the electronically tuned Colpitts oscillator shown in Fig.9.4. drift is invariably larger than longterm drift, resulting from the rapid increase in temperature during the brief period after power is initially applied to the oscillator circuit. Short-term drift is therefore usually quoted for the first few minutes of operation. Thereafter, the output frequency tends to change at a much lower rate, and will usually stabilise at a value that remains reasonably constant. Fig.9.7 shows the variation of output frequency for the Colpitts oscillator shown in Fig.9.4 when set initially to a frequency of 7523.5kHz. Note how the frequency increases by around 3.5kHz in the first five minutes, after which the rate of change of frequency progressively reduces, stabilising at around 7527kHz when the circuit reaches its working temperature. Thereafter, the long-term drift is less than about 100Hz over a four-minute period (about 25Hz per minute). This is adequate for many non-critical applications, but the lack of frequency stabilisation makes it unsuitable for narrow-band operation and digital demodulation. Fig.9.8: a temperaturestabilised, oven-controlled crystal oscillator. Because of their inherent non-­ linearity and a tendency to drift, free-running oscillators are avoided in critical RF applications. Instead, modern RF signal sources use phaselocked loops, frequency dividers and digital control methods, often controlled using an I2C or SPI serial bus. Various strategies are used for generating signals, some of which are based on a voltage-controlled crystal oscillator (VCXO) combined with a phase-locked loop and frequency divider. Others employ direct digital synthesis (DDS), with the signal generated digitally. We will be looking at both methods based on currently available low-cost modules. An essential component in many frequency-generating systems is a variable crystal oscillator (VCXO). This comprises a crystal oscillator with limited tuning provided by a variable capacitance diode, enabling its output frequency to be adjusted electronically as described earlier. To allow useful tuning around the nominal crystal frequency, a VCXO must trade some intrinsic stability for increased frequency pull range. This can degrade its frequency-versustemperature characteristic, its ageing, its short-term stability and associated phase noise. When a VCXO is used in a PLL, its frequency excursion must always be at least as great as the combined instability of the VCXO itself and the reference to which it is being locked. A VCXO that incorporates additional circuitry to counter the effects of temperature change is referred to as a TC/VXO (temperature-compensated voltage-controlled oscillator). To further reduce the effects of temperature change, a small temperature-controlled oven can be added, creating an OC/VCXO (oven-controlled voltage-controlled crystal oscillator). Fig.9.8 shows an example of a low-cost oven-controlled crystal oscillator that can be used as a highly accurate frequency reference. Frequency stability The stability of a frequency reference is usually stated in terms of parts-per-million (PPM) or parts-per-billion (PPB). For example, a 10MHz crystal oscillator with a Practical Electronics | July | 2026 Stage B (synthesis) Stage A (synthesis) PLL A XA XTAL OSC XB PLL B Fig.9.10: the internals of the Si5351A IC (there is also an 8-output version). quoted stability of 10PPM will have a maximum frequency error of 100Hz. The module shown in Fig.9.8 provides sine and square wave outputs at 10MHz with a quoted stability better than 20PPB. It consumes 600mA during its initial five-minute warm-up period but less than 250mA thereafter. For accurate calibration, the output frequency can be adjusted by a control voltage obtained from a multi-turn preset potentiometer (R5). This derives its supply from a DC source that’s closely regulated to ensure stability. Next, we will move on to examine two contrasting approaches for accurate and stable frequency generation. The first is based on PLL techniques and frequency division; the second involves DDS techniques. The Si5351 clock generator The Si5351 is an I2C-programmable frequency generator that’s ideally suited for replacing one or more crystal-­controlled oscillators. To aid the experimenter, the device is readily available in a variety of low-cost modules that can be easily incorporated into your own designs, as shown in Fig.9.9. It’s important to note that frequent references to the Si5351 as a DDS (direct digital synthesis) chip are incorrect because the device is based on PLL techniques and fractional dividers, rather than direct waveform synthesis used in DDS. The Si5351 can generate precision frequencies up to 160MHz on each of its outputs. Three versions of the Si5351 are available: • the Si5351A generates up to eight programmable clock frequencies from a single crystal-controlled master clock • the Si5351B adds an internal VCXO and provides the flexibility to replace free-running clocks as well as synchronous clocks • the Si5351C offers similar features but can also synchronise to an external reference clock (CLKIN) Practical Electronics | July | 2026 Crosspoint switches Input Stage Stage C (output) VDDO Multi Synth 0 R0 CLK0 Multi Synth 1 R1 CLK1 Multi Synth 2 R2 CLK2 Fig.9.10 shows a simplified schematic of the Si5351A. The device consists of an input stage, two synthesis stages (A and B) and an output stage (C). The input stage accepts an external crystal (XTAL) that sets the fundamental clock frequency. The first synthesis stage (Stage A) multiplies the oscillator frequency using two phase-locked loops (PLL A and PLL B) to produce high-frequency intermediate clock signals. These two clocks (derived from Stage A) are then fed to a programmable cross-point switch within Stage B. This flexible switching arrangement provides signal routing to the three ‘MultiSynth’ stages that act as highresolution fractional dividers. The outputs from Stage B are fed to three further integer dividers, R0 to R2, at the input of Stage C. This additional stage of integer division allows the chip to generate output frequencies as low as 8kHz. The divided frequency outputs are then fed to three buffer stages to produce the final output frequencies, CLK0 to CLK2. Fig.9.11 (overleaf) shows a simplified schematic of the Si5351B. The device uses a similar arrangement to that of its smaller counterpart, but adds two further inputs: a clock input (CLKIN) and a control voltage input (VC). The former allows locking to an external clock input, while the latter provides frequency control from an external voltage control as well as the option of locking to an external clock input. Stages B and C of the Si5351B are extended to provide eight outputs, CLK0 to CLK7, enabling the chip to generate free-running or synchronous non-integer related clock frequencies at each of its outputs. Note that it’s possible for one device to synthesise clocks for multiple clock outputs. The Si5351 uses a fixedfrequency standard AT-cut quartz crystal (introduced in part 2, December 2025) as a reference for its internal oscillator. The output of the oscillator can be used to provide a free-running reference for one or both of the phase-locked loops. The oscillator requires a fundamental crystal frequency of either 25MHz or 27MHz; internal load capacitors are provided to avoid the need for external components. During software configuration, the capacitors can be set to provide a 6pF, 8pF or 10pF crystal load. The Si5351B’s external clock input is used as a clock reference for PLL A and PLL B; the external clock input (CLKIN) can accept any frequency between 10MHz and 100MHz. The Si5351B’s internal VCXO provides excellent linearity coupled with reliable startup and a wide tuning range (linear from 10% to 90% of VDD). A unique feature of the chip is its ability to generate multiple output frequencies determined by the same control voltage. The chip can thus replace multiple PLLs or VCXOs that would normally be locked to a common reference. By applying a control voltage (Vcontrol), the device can function without an external pullable quartz crystal. As with the Si5351B, the Si5351A uses two synthesis stages (A and B) to generate its final RF output from Fig.9.9: a low-cost clock generator module based on the Si5351A chip. 59 Stage B (synthesis) Fig.9.11: the internal arrangement of the Si5351B IC. This version of the chip always has eight outputs. Input Stage Divider XA XTAL OSC PLL B (VCXO) XB VControl Crosspoint switches PLL A (SSC) Crosspoint switch CLKIN Stage A (synthesis) VCXO CLK0 to CLK7. Stage A uses PLLs to multiply the lower frequency input references to a high-frequency intermediate clock. The second stage uses high-resolution fractional dividers provided by MultiSynth 0 to MultiSynth 7. Frequencies of up to 160MHz can be generated on multiple outputs. The Stage A (input) cross-point switch enables each PLL to lock onto either the CLKIN or XTAL input. This allows the PLLs to use the same or different sources for independent or synchronous clock generation. Stage B’s cross-point switch lets any fractional divider receive input from either PLL A or PLL B, so outputs can fXO Crystal oscillator fXO = 25 or 27MHz R0 CLK0 Multi Synth 1 R1 CLK1 VDDOB Multi Synth 2 R2 CLK2 Multi Synth 3 R3 CLK3 VDDOC Multi Synth 4 R4 CLK4 Multi Synth 5 R5 CLK5 VDDOD Multi Synth 6 R6 CLK0 Multi Synth 7 R7 CLK7 be synchronous or non-synchronous at unrelated, non-integer frequencies as required. The VCXO in the Si5351B already generates a high-frequency intermediate clock, so it can be fed directly into Stage B. The high-resolution fractional dividers allow synthesis of the VCXO centre frequency from 400kHz to 160MHz. Frequency generation with the Si5351 It’s worth providing a few simple examples of frequency generation with this chip. Fig.9.12 illustrates the various stages of conversion, division and synthesis within the device. fVCO = fXO x Div.A DC Phase detector VCO Stage A Div.A = a + b/c a = 15 to 90 b = 0 to 1048575 c = 1 to 1048575 The output of Stage A (fVCO) is a multiple of the crystal oscillator frequency (fXO). The multiple is determined by the Stage A fractional division ratio, Div.A. In turn, Div.A is determined by variables a, b and c. The yellow note in Fig.9.12 shows the range of values that can be used for these. The output of Stage B (f ) is a ratio of the VCO frequency (fVCO). The ratio is determined by the Stage B fractional division ratio, Div.B. In turn, Div.B is determined by variables d, e and f. As before, the yellow note in Fig.9.12 shows the range of values that can be used for these quantities. The output of Stage C (fout) is a ratio f = fVCO / Div.B fout = Fractional Divider (Div.B) Integer divider R = 1,2,..128 Stage B Stage C fVCO = 600 to 900MHz fVCO/Div.A VDDOA Multi Synth 0 Fractional divider (Div.A) 60 Stage C (output) (fxo x Div.A) (Div.B x R) Div.R = 1,2,..128 Div.B = d + e/f d = 4 to 900 e = 0 to 1048575 f = 1 to 1048575 Fig.9.12: frequency generation using the Si5351’s fractional and integer dividers. Practical Electronics | July | 2026 (Div.A) 25MHz of the output frequency from Stage B (f ). The ratio is determined by the Stage C division ratio, R, which can take an integer value from 1 to 128. We can now combine these relationships to obtain the following. The output frequency, fVCO, from Stage A is given by: 25MHz Here, a, b and c determine the division ratio provided by f the Stage A f vco = vco b f= fractional divider. f vco =f xoDiv.B ⋅Div.A=f xo⋅(a+ ) e The output frequency, (d +f, from ) cStage f B is given by: f f f = vco = vco b ) f xo⋅(a+ Div.B e f xo⋅Div.A (d + ) bc ffout = = f e c) vco =fDiv.B⋅R xo⋅Div.A=f xo⋅(a+ (d + )⋅RdiviHere, d, e and f determine the sion ratio provided by the f Stage b B ⋅(a+ ) f xo fractionalf divider. f vco f vco c xo⋅Div.A == stage of synf = (and final) The third f out = Div.B e e integer Div.B⋅R thesis applies an additional (d(d + + ) )⋅R ratio of division, R, in Stage f f C. The Phase detector DC Phase detector VCO ÷35.7632 (Div.A) Phase detector 25MHz ÷15 (Div.B) 440kHz ÷2032 (Div.B) 55MHz ÷1 (Div.R) 55kHz ÷8 (Div.R) (a) 55MHz (b) 55kHz DC 25MHz 894.08MHz ÷33 (Div.A) 25MHz 55MHz 825MHz VCO 25MHz b f vco =f xo⋅Div.A=f xo⋅(a+ ) c (a) 55MHz DC 25MHz 440kHz 894.08MHz ÷2032 (Div.B) VCO 55kHz ÷8 (Div.R) Fig.9.13: generating (a) 55MHz and (b) 55kHz clock signals using an Si5351. ÷35.7632 (Div.A) (b) 55kHz final output frequency can then be determined from: b f xo⋅(a+ ) f ⋅Div.A c f out = xo = e Div.B⋅R (d + )⋅R f Fig.9.13 shows how the Si5351 can generate outputs at (a) 55MHz and (b) 55kHz. In the second case, the a fractional division ratio is used for Div.A and the additional integer divider applied by Div.R. To simplify the design process when using the Si5351 series of chips, you will find the Skyworks ClockBuilder Pro. utility extremely useful. This software will guide you through each of the stages of a clock design, as shown in Figs.9.14 & 9.15. Fig.9.14: selecting chip and package type in Skyworks ClockBuilder Pro. Here we’ve selected the 10-pin MSOP packaged version of the Si5351A. Programming the Si5351 Programming the Si5351 is simple and can be done using any low-cost microcontroller that supports the I2C bus. An example Arduino code fragment is shown in Listing 9.1 (overleaf). This can be used to generate a constant 10MHz square wave output from the Si5351’s CLK0 output at a level of approximately 10dBm (10mW). An Si5351 module, like that shown in Fig.9.8, can be driven from the Arduino’s I2C data and clock signals (pins A4 and A5 on an Arduino Nano). An additional ground connection is also required. The code is greatly simplified by the use of two library files, “si5351.h” and “Wire.h” (the latter is used for I2C communication). If you need a Practical Electronics | July | 2026 Fig.9.15: entering the crystal frequency and internal load in Skyworks ClockBuilder Pro. 61 #include "si5351.h" #include "Wire.h" Listing 9.1: an example code fragment for the Si5351 to produce a 10MHz, 10dBm output. Si5351 si5351; void setup() { bool i2c_found; // Start serial and initialize the Si5351 Serial.begin(57600); i2c_found = si5351.init(SI5351_CRYSTAL_LOAD_8PF, 0, 0); if(!i2c_found) Serial.println("Device not found!"); // Set CLK0 to 10 MHz and 10dBm appx. si5351.set_freq(1000000000ULL, SI5351_CLK0); si5351.drive_strength(SI5351_CLK0, SI5351_DRIVE_8MA); Serial.println("CLK0 set to 10MHz at 10dBm"); // Query status update si5351.update_status(); delay(500); Fig.9.16: a low-cost RF generator module based on the AD9833 DDS chip. } void loop() { // Other code goes here } 12-bits FREQ0 register Phase accumulator (28-bits) MUX FREQ1 register Control logic/ serial interface FSYNC SCLK S PHASE0 register MUX SIN ROM lookup table DAC (10-bits) VOUT On-board reference Full-scale control COMP PHASE1 register Fig.9.17: the simplified internal arrangement of the AD9833 DDS chip. SDATA I2C Bus Ext. USB Arduino Uno (for power and programming) 3 GND 4 +5V GND 10 11 A4 SDA A5 SCL 16x2 GND GND LCD display +5V 13 VCC R1 4k7 SPI Bus R2 4k7 VCC GND FSYNC DAT CLK B1 Up B2 Down more extensive example, this month’s Hands-On project provides you with a complete Arduino Si5351 application in the form of a useful frequency marker and calibration aid. Direct digital synthesis (DDS) and the AD9833 The AD9833 is an example of a low-cost, fully integrated DDS chip. It requires an external reference clock and a handful of other components to provide digitally synthesised sinewave outputs at up to 12.5MHz. The frequency and phase are both software-programmable, allowing easy tuning coupled with the ability to apply digital modulation when re- 62 AD9833 module Output Fig.9.18: the circuit for the push-button digital VFO arrangement. quired. Like the Si5351, the AD9833 is available in a low-cost module, such as the one shown in Fig.9.16. The AD9833 has a standard threewire SPI serial interface, allowing it to also be controlled by a low-cost microcontroller, although the pin that would normally be called CS (chip select) is labelled FSYNC. The pin marked CS on the module is not needed in our application. Supplied in a 10-lead MSOP package, the chip operates from a DC supply of 2.3-5.5V. To minimise power requirements, the device incorporates a SLEEP function that disables parts of the chip that are not being used. The simplified internal arrangement of the AD9833 is shown in Fig.9.17. It consists of two frequency select registers (FREQ0 and FREQ1), a phase accumulator, two-phase offset registers (PHASE0 and PHASE1) and a phase offset adder. These stages are followed by a SIN ROM. This storage device uses the digital phase information as an address to a lookup table containing amplitude data. The output of the SIN ROM is fed to a 10-bit digital-to-analog converter (DAC). This accepts successive amplitude data from the SIN ROM and converts it to corresponding analog voltages. The output from the DAC is a quantised analog waveform with an amplitude of about 0.6V peak-to-peak. The AD9833’s frequency registers are 28 bits wide and, with a 25MHz clock rate, a resolution of 0.1Hz can be achieved. For low-frequency applications with an external clock rate of 1MHz, the AD9833 can provide a resolution as low as 0.004Hz. Although the phase accumulator uses 28 bits, its output is truncated to 12 bits because it’s neither practical nor necessary to use all the bits. Using the full 28-bits would require a lookup table with a staggering 228 = 268,435,456 entries! AD9833 applications The AD9833 can be configured for use in a wide variety of applications, not just basic RF signal or clock generation like the Si5351. In basic frequency shift keying (FSK), the two frequency registers are loaded with different values. One represents the ‘space’ frequency, while the other represents the ‘mark’ frequency. Using the AD9833’s control register, the user can then modulate the carrier frequency between the stored ‘mark’ and ‘space’ values. The two-phase registers enable Practical Electronics | July | 2026 Fig.9.19: the author’s prototype pushbutton digital VFO. #include <MD_AD9833.h> #include <LCD-I2C.h> #include <Wire.h> #include <SPI.h> unsigned long freq = 7100000; Listing 9.2: a pushbutton digital VFO using the AD9833. // Initial frequency in kHz // Step and limits const long upperlim = 7200000; // Upper limit in kHz const long lowerlim = 7000000; // Lower limit in kHz const long step = 9000; // Step in kHz // Pins used for SPI data const uint8_t PIN_DATA = 11; const uint8_t PIN_CLK = 13; const uint8_t PIN_FSYNC = 10; // Buttons const int UP = 3; const int DOWN = 4; // MD_AD9833 AD(PIN_FSYNC); // Hardware SPI LCD_I2C lcd(0x27, 16, 2); // Default I2C LCD the chip to perform phase shift keying (PSK). In this case, the carrier frequency is phase shifted, the phase being altered by an amount related to the bit stream input to the modulator. More complex modulation schemes, such as GMSK and QPSK, can also be implemented using the AD9833. Fig.9.18 shows how an AD9833 module can be used to form the basis of a simple push-button digital VFO controlled by a few lines of code running on an Arduino Uno. The arrangement uses a 16×2 alphanumeric LCD to indicate the output frequency and two miniature push-buttons for ‘up’ and ‘down’ frequency control. The author’s prototype digital VFO is illustrated in Fig.9.19, and the Arduino code is given in Listing 9.2. The library file developed by Marco Colli of MajicDesigns greatly simplifies interfacing with the AD9833. The Arduino code in Listing 9.2 allows the push-button digital VFO to be adjusted in 9kHz steps over the range 7.0-7.2MHz. Values for the initial frequency, upper and lower limits can be easily changed and adapted for use in your own projects. This application uses the I2C bus to control the LCD display and the SPI interface for communication with the AD9833. Fig.9.20 shows a more advanced application in which the AD9833 forms the basis of a digitally controlled RF sweep generator with touchscreen frequency control. Hands-On: A programmable frequency marker/calibrator This month’s Hands-On project is another useful item of RF test equipment: a programmable frequency void setup(void) { AD.begin(); Wire.begin(); lcd.begin(&Wire); lcd.display(); lcd.backlight(); } void loop() { // Read button status if (digitalRead(UP) == LOW) freq = freq + step; if (digitalRead(DOWN) == LOW) freq = freq - step; // Check if limits are reached if (freq >= upperlim) freq = upperlim; if (freq <= lowerlim) freq = lowerlim; // Update the LCD lcd.setCursor(0, 0); lcd.print("AD9833 VFO"); lcd.setCursor(0, 1); lcd.print(freq); lcd.print(" Hz"); AD.setFrequency(MD_AD9833::CHAN_0, freq); delay(250); // Button delay } Practical Electronics | July | 2026 Fig.9.20: a touchscreen-controlled RF sweep generator based on the AD9833. 63 Ext. USB Fig.9.21: the circuit of the programmable frequency marker/calibrator. Arduino Nano (for power and programming) D3 D4 D5 GND VIN GND A5 6m 2m 10m S1 Band select marker and calibrator, based on a low-cost Si5351 module, controlled by an Arduino Nano. The unit provides separate calibration outputs at 1MHz and 10MHz, together with three switchselectable marker outputs that can be programmed to frequencies of your choice. The three marker frequencies selected for the prototype were 28.050MHz in the 10m band, 50.050MHz in the 6m band and 144.500MHz in the 2m band. The marker/calibrator circuit is shown in Fig.9.21. The Si5351 module is connected to the I2C bus via pins A4 (SDA) and A5 (SCL). The module derives its power from the Nano’s supply, VIN; the three band marker frequencies are selected by a rotary switch, S1, connected via digital inputs D3, D4 and D5. The internal layout of the frequency marker/calibrator is shown in Fig.9.22. All components are mounted on the underside of the USB PORT 16 D13 D12 17 3.3V D11 I2C Bus Outputs 18 REF D10 SDA A0 D9 SK1 10MHz 19 CLK2 20 A1 D8 SCL Si5351 SK2 1MHz 21 CLK1 A2 D7 GND module 22 A3 D6 SK3 Marker CLK0 VIN A4 D5 23 A5 D4 24 lid of a small ABS enclosure. To A6 D3 25 minimise wiring, the Si5351 module A7 D2 26 should be located relatively close to the Nano. VIN GND 27 To avoid the need to fit coaxial RST RST 28 connectors (which can be difficult GND D1/RXD 29 unless you have the right tools), VIN D0/TXD 30 we’ve used ready-made panelmounting sockets. These are available at a reasonable cost from several Top view online suppliers and come fitted Fig.9.23: the Arduino Nano with 15cm pigtail cables and SMA pin connections. connectors (see Fig.9.22). We used standard SMA connectors for the two calibrator outputs and a Wiring is straightforward using single female BNC connector for the terminal pin headers fitted to both switched marker output. An alterna- the Si5351 module and the Arduino tive combination of connectors can Nano (see Fig.9.23 for the connecbe used to suit your requirements. tions). The front panel layout of The Nano’s USB supply and pro- the frequency marker/calibrator is gramming connection is made using shown in Fig.9.24. a short 20mm USB extension lead. The Arduino code for the freThis mates with a bulkhead USB quency marker/calibrator is shown connector mounted on the front pan- in Listing 9.3. It sets the Si5351 el, but again, different arrangements crystal load to 6pF and the two calican be made to suit your needs. brator outputs (1MHz and 10MHz) A4 Fig.9.22: the internal layout of the programmable frequency marker/ calibrator. 64 Practical Electronics | July | 2026 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Parts List – programmable frequency marker/calibrator 1 small ABS enclosure, 158 × 90 × 60mm or larger 1 Arduino Nano with pin headers 1 Si5351A module 1 4-pole, 3-way rotary switch (only one pole is used) (S1) Connectors/cables 2 panel-mounting female SMA sockets with male SMA 15cm pigtail connectors (SK1, SK2) 1 panel-mounting female BNC socket with male SMA 15cm pigtail connector (SK3) Hardware 2 M3 × 5mm metal or nylon hexagonal standoffs/spacers 4 M2 × 5mm metal or nylon hexagonal standoffs/spacers 2 M3 × 10mm panhead machine screws 2 M3 × 10mm countersunk head machine screws 8 M2 × 10mm panhead machine screws 1 panel-mounting USB-C female socket with a male 20cm USB-C pigtail connector to 5dBm (corresponding to about 0.4V into 50Ω). The output of the switched marker has been set to 10dBm (10mW into 50Ω) for each band, but the code can be easily modified for different output levels and frequencies. Coming up! In Part 10, we move on to explore short- and long-range digital wireless communication. Our HandsOn constructional project will be a simple RF field strength indicator. PE See you next time! #include "si5351.h" #include "Wire.h" Listing 9.3: Arduino code for the DDS marker/calibrator. Si5351 si5351; const int SEL_144MHz = 3; const int SEL_50MHz = 4; const int SEL_28MHz = 5; // D3 selects 2m marker // D4 selects 6m marker // D5 selects 10m marker #define fmark1 2805000000ULL // 10m frequency #define fmark2 5005000000ULL // 6m frequency #define fmark3 14450000000ULL // 2m frequency void setup() { // Enable internal pull-ups on each switch input pinMode(SEL_144MHz, INPUT_PULLUP); pinMode(SEL_50MHz, INPUT_PULLUP); pinMode(SEL_28MHz, INPUT_PULLUP); // Adjust crystal reference frequency si5351.init(SI5351_CRYSTAL_LOAD_6PF, 0, 0); // Set CLK1 to 1MHz, 5dBm si5351.set_freq(100000000, SI5351_CLK1); si5351.drive_strength(SI5351_CLK0, SI5351_DRIVE_2MA); // Set CLK2 to 10MHz, 5dBm si5351.set_freq(1000000000, SI5351_CLK2); si5351.drive_strength(SI5351_CLK1, SI5351_DRIVE_2MA); delay(500); } void loop() { // Read switch and select required marker on CLK0 if (digitalRead(SEL_28MHz) == LOW) si5351.set_freq(fmark1, SI5351_CLK0); if (digitalRead(SEL_50MHz) == LOW) si5351.set_freq(fmark2, SI5351_CLK0); if (digitalRead(SEL_144MHz) == LOW) si5351.set_freq(fmark3, SI5351_CLK0); // Set output to approx. 10dBm si5351.drive_strength(SI5351_CLK0, SI5351_DRIVE_8MA); delay(500); } Fig.9.24: the front panel of the programmable frequency marker/ calibrator. Practical Electronics | July | 2026 65