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Circuit Surgery Regular clinic by Ian Bell Measuring circuit frequency response using a PC sound card, part 7: op amp output impedance & compensation I n recent articles, we have been looking at frequency response measurement. This was motivated by the need to measure the response of a practical implementation of an example digital filter (from our series on DSP) using the sound card (audio interface) of a PC or laptop together with software for this purpose. As part of this topic, we have been discussing the signal conditioning needed to interface the circuit under test to the sound card’s line inputs and outputs. Most recently, we focused on op amp based amplifier feedback, frequency response and stability. Last month, we covered the effect of capacitive loading on op amp amplifiers and its potential to cause instability (unwanted oscillation). This is relevant to the signal conditioning circuit, but our discussion is applicable to a wide range of other applications. This month, we will continue on this Op amp stability recap Op amp based amplifiers rely on negative feedback. The op amp on its own (without feedback) has an open-loop gain, AO. The amplifier circuit with feedback has a closed-loop gain, AC. Its loop gain is - AO; this is the gain around the closed feedback loop, where β is the fraction of the output that is subtracted from the input signal. The frequency response of op amps (as shown in Fig.1) is important when discussing circuit stability. As signal frequency increases, the phase shift due to the delay around the loop becomes more negative, so the effective total phase shift reduces from 180° towards (and then past) zero. If the total phase shift is zero or an integer multiple of ±360°, the feedback Pole 1 Ao Gain (dB) theme, looking at some aspects we did not cover last month, including how we might mitigate the effect of capacitive loads on stability. Ac Closed loop response Open-loop response Unity gain bandwidth 0 Pole 2 f0 –90 –180 180° Total loop phase shift Loop delay phase shift 0 Closed loop bandwidth Log frequency Capacitive loading Last month, we performed a simplified analysis of a unity-gain buffer with a capacitive load (Fig.2). We will reuse this model later, so it is worth recapping. The circuit includes the op amp’s output impedance (ZO) because its interaction with the load capacitance is an important factor in circuit stability. To keep the analysis simple, we assume the op amp output impedance is resistive (ZO = RO) and its input impedance is infinite. We also ignored the resistive part of the load (RL in Fig.2). We also assumed an idealised op amp with just one low-frequency pole in its open-loop frequency response, AO(s), Pole 1 in Fig.1, and no frequency dependence of the direct feedback connection (β = 1 at all frequencies). The result was that the capacitive load added a pole to the loopgain at a frequency of fp = 1 ÷ 2πROCL. In this scenario, the circuit must be stable without the capacitive load because the single pole in AO(s) only provides -90° of phase shift. With the additional – 90° Vout Phase margin 0° Fig.1: the typical frequency response of an op amp. 48 Log frequency will be positive, potentially resulting in instability. Phase margin (see Fig.1) and gain margin are measures of how close a circuit is to being unstable. The open-loop gain of most op amps is deliberately reduced at high frequencies so that unity-gain amplifiers are stable. This typically creates a low-frequency (typically 1-10Hz) pole in the open-loop response (Pole 1 in Fig.1 is typical of an op amp dominant pole). Above this frequency, the open-loop gain falls from AO at 20dB per decade until another pole or zero is reached. Vin + ZO Vop CL RL Fig.2: an op amp based buffer with a capacitive load. Practical Electronics | April | 2026 Fig.3: an LTspice schematic for simulating the loop gain of unity and higher-gain amplifiers based on op amps. pole provided by RO and CL, the phase shift can reach 180° and potentially cause instability. Real op amps have more than one pole (as shown in Fig.1), so the additional pole due to the capacitive load can easily cause sufficient phase shift for instability under certain conditions. Simulations using the OPAx134 op amp from the sound card interface showed marginal stability with a 1nF load and full instability with 2nF. Amplifier gain There are a couple of things that we did not include in our discussion last month that are worth looking at now. We only considered unity-gain circuits, and we assumed the output impedance of the op amp was resistive. We will continue to use this latter simplification in further examples, but it is worth looking at what a more realistic view of output impedance looks like. First, though, we will consider the relationship between closed-loop gain and stability. Fig.3 shows an LTspice schematic for simulating loop-gain for two op amp circuits, one with 100% feedback (using U1) and the other (using U2) having a feedback factor of β = 0.1, set by the potential divider ratio of R3 and R4, that is R4 ÷ (R3 + R4) = 1kΩ ÷ (1kΩ + 9kΩ) = 0.1. This simulation is of loop gain, which determines stability, not the closed-loop gain of a specific amplifier circuit. Therefore, the circuits in Fig.3 do not have an input signal because we are just looking at the feedback loop. U1 is configured as a unity-gain amplifier with its output connected directly to the inverting input (R2 has zero resistance). This is the circuit setup we used last month. For U2, the feedback configuration could relate to a non-inverting amplifier with a gain of 10, or an inverting amplifier with a gain of 9. The gain of the non-inverting amplifier is found from 1 ÷ β = 1 ÷ 0.1 = 10, or we can use the well-known resistor formula: 1 + R3 ÷ R4 = 1 + 9kΩ ÷ 1kΩ = 10. Practical Electronics | April | 2026 The gain of the inverting amplifier is found from 1 – (1 ÷ β) = 1 – (1 ÷ 0.1) = -9, or we can use the other well-known resistor formula: -R3 ÷ R4 = -9kΩ ÷ 1kΩ = -9. For more detail on the relationship between circuit gain and β, please refer to the February 2026 Circuit Surgery column. The simulation setup in Fig.3 is similar to the simulation of idealised unity-gain amplifiers last month. It uses the UniversalOpAmp4 model with AO = 1.778×106 (125dB) and GBP = 8MHz, but with the output resistance RO set to a more idealised value of 10Ω to reduce interaction with the resistor network. Fig.4 shows the results from the simulation in Fig.3. The gain curves show that the loop gain for the higher gain (×10 or ×-9) amplifier (yellow trace) is 20dB below the loop gain of the unity-gain amplifier. Note the reciprocal relationship between closed-loop gain and loop gain – lower loop gain corresponds with higher closedloop gain. At DC, and frequencies well below the op amp’s dominant pole, the loop gain of the unity-gain amplifier is βAO, with β = 1, the loop gain is equal to AO, which was set at 125dB in the op amp model, as noted above. For the higher-gain amplifier, we have β = 0.1, so the loop gain is 1/10th of the loop gain of the unity-gain circuit. In decibels, 1/10th is a difference of log10(1/10) = -20, so we expect a DC loop gain of 125dB – 20dB = 105dB, which is what we see in Fig.4. The graph in Fig.4 has been annotated with the phase margin and shows that the phase margin of the higher gain circuit (65°) is much better than that of the unity-gain buffer (23°). Fig.4 shows that the phase response is the same for both circuits. This is because the two feedback networks are purely resistive, so neither adds any delay (and hence phase shift) to the loop. However, as just discussed, the higher closed-loop gain circuit has a feedback potential divider that reduces the loop gain. This means the loop gain of the higher-gain amplifier falls to unity (0dB) at a lower frequency (727kHz) than the unity-gain circuit (3.39MHz). The 0dB gain values are shown in the phase margin annotations. Phase margin is the difference between 0° and the total loop phase shift (including 180° due to inversion) at unity loop gain (see Fig.1). Or we can express it as the difference in the phase shift due to Fig.4: the LTspice simulation results from the circuit in Fig.3. 49 loop delay from -180° (also see Fig.1). The equal phase shift for the two circuits, and the lower loop-gain of the higher-gain amplifier, means that the phase margin of the higher-gain amplifier is better. The phase margin measurements are illustrated in the zoom-in on the loop response plot shown in Fig.5. As noted in our introduction to op amp frequency response in February 2026, the fact that lower closed-loop gain op amp amplifiers are more likely to be unstable may seem counterintuitive to some. Perhaps this is because people think of a high-gain circuit as being ‘unstable’ because it is very sensitive to changes in its inputs ignals, so may react in unwelcome ways if the input is too large. It could also be because people often experience feedback from loudspeakers via microphones and musical instruments (known as acoustic feedback or the Larsen effect). In such a case, you are inside the loop, so turning down the amplifier (reducing gain) to stop the screeching sound is effectively reducing loop-gain, thus making the system more stable in line with the discussion above. Reducing the gain of the amplifier here does not correspond to a lower-gain op amp circuit, but it is possible to see that it might be perceived as such. It is also worth noting that the gain and phase shift responses of an acoustic scenario will typically be much more complex than an op amp based amplifier, due to multiple sound reflections and other room acoustic properties, which will change as people and microphones move. Uncompensated op amps The low-frequency pole (Pole 1 in Fig.1) found in most op amp open loop frequency responses is designed to ensure stability in unity-gain circuits built with the op amp. Modification of the frequency response to ensure stability is called compensation. These devices are referred to as compensated or ‘unity-gain stable’ op amps. Some op amps are not designed to be stable in low closed-loop gain configurations and must be used in higher-gain configurations to be stable. These are referred to as decompensated op amps. Other op amps are uncompensated – they do not have any compensation built in, so to be stable in any circuit, they must be compensated by the user adding external components; for example, a capacitor connected between two pins provided for that purpose. Decompensated op amps may also have pins to allow the user to increase the level of compensation. Fig.6 is a comparison of the gain responses of unity-gain stable, decompensated and uncompensated op amps, assuming they all have the same DC open-loop gain (AO). The decompensated op amp has a 50 Fig.5: a zoom-in of Fig.4 showing the phase margin measurements. low-frequency pole at a slightly higher frequency than the unity-gain-stable device, but has the same basic shape to the frequency response. The uncompensated op amp has it first pole at a higher frequency and a more complex-looking response because its high-frequency poles are more dominant in the shape of the graph. Fig.6 is a little simplified as related devices with different compensation may not have exactly the same open-loop gain, and the high-frequency poles of the decompensated and uncompensated op amps are not shown. Decompensated op amps (and uncompensated ones with suitable compensation added) allow closed-loop circuits to have higher bandwidth as long as they are stable at the required closed-loop gain (AC), with all other things being equal. This can be seen in Fig.6, where the closed-loop bandwidth of the decompensated device (dotted cyan trace) is larger than for the unity-gain stable device (dotted magenta trace). Example devices The NE5532 is a widely used low-noise dual op amp designed for audio use that is unity-gain stable (it would be suitable in place of the OPAx134 in the sound card interface). The NE5534 is a similar single (not dual) device with the same op amp circuitry as the NE5532, except that it is decompensated so that it is only stable for a closed-loop gain of three or more. This allows the NE5534 to achieve higher bandwidth than the NE5532. The NE5534 also has a higher slew rate (maximum rate of change of the output), which allows it to handle faster transients and larger signals without distortion. The frequency response of the NE5534 can be optimised to specific applications using an external compensation capacitor between the COMP and COMP/BAL pins. However, the datasheet only provides example compensation capacitor values on some characteristic tables and curves (some datasheets provide formulae for compensation capacitor values). With a 22pF external compensation capacitor, the NE5534 is unity-gain stable and has the same unity-gain bandwidth as the NE5532. This makes sense because of the similarity of the devices. Gain / dB AO Decompensated open-loop response Unity-gain stable open-loop response (Fig.1) AC Uncompensated open-loop response Closed-loop Responses Log frequency Closed-loop bandwidths Fig.6: unity-gain stable, decompensated and uncompensated op amp responses Practical Electronics | April | 2026 Fig.7: an LTspice schematic for simulating and measuring op amp output impedances. Higher bandwidths are available from decompensated op amps in higher-gain circuits if they have not been further compensated to obtain unity-gain stability. In general, the extra complexity and need for external compensation capacitors mean they are less widely used than unity-gain stable devices. Similarly, the OPAx227 low-noise op amps from Texas Instruments are unity-­gain stable, while the OPAx228 are optimised for closed-loop gains of 5 or more. These devices are available in single, dual and quad packages and, unlike the NE5534, do not have compensation pins. as for Fig.3 except its output resistance is set to 200Ω. The open-loop circuits use the approach to simulation we discussed in February 2026. We use separate DC and AC resistance values in the feedback network to ensure the op amp is biased correctly by applying feedback in the simulator’s operating point calculation, but it is open loop for the AC analysis. The results are shown in Fig.8, with the OPAx134 at the top and the idealised model below. The open-loop output impedance OPAx134 (green trace) varies significantly with frequency, whereas the idealised open-loop output impedance (yellow trace) is flat throughout the frequency range at the value set in the model parameter. 200Ω matches the low-frequency value from the OPAx134. Op amp output impedance We have assumed a fixed-resistance output impedance to simplify the analysis of op amp frequency response. However, the actual impedance is more complex and varies with frequency. We can obtain plots of op amp output impedance against frequency using LTspice. One way to achieve this is to inject a current (i) into the op amp’s output in an AC analysis and plot v ÷ i, where v is the voltage at the op amp’s output. The op amp has zero input signal in this simulation. An LTspice schematic for simulating op amp output impedance is shown in Fig.7. Both open-loop (U1,U3) and closed-loop (U2,U4) impedances are investigated. We look at both a real op amp (the OPAx134 – U1,U2) and an idealised case using the UniversalOpAmp4 model (U3,U4). The UniversalOpAmp4 is configured Practical Electronics | April | 2026 Fig.8: the results from running the simulation using Fig.7. 51 The shapes of the open-loop output impedance curves for different op amps vary, but the kind of variation shown for the OPAx134 in Fig.8 is not unusual. Flat parts of the curve (low and mid-range frequencies) show resistive behaviour. The parts of the curve that slope down as the frequency increases exhibit capacitive behaviour (capacitor impedance drops with increasing frequency), whereas upward slopes are inductive. The closed-loop output impedance in both cases (red trace for the OPAx134, magenta for the idealised op amp) is close to zero until higher frequencies are reached. In these circuits, the output impedance is reduced by (1 + βAO) with feedback applied. For example, with AO = 125dB = 106.25 and β = 0.1, we get an expected reduction by a factor of (1 + βAO) ≈ 0.1 × 106.25 = 105.25 (we can ignore the “1 +”). This gives an impedance of 200Ω ÷ 10 5.25 which is around 1mΩ. Zooming in on the plots confirms an impedance around this value. β is set by the feedback resistors for U2 and U4, as discussed for the circuit in Fig.3. For both the OPAx134 and idealised cases, the impedance starts to noticeably increase in the plots at around 10-100kHz. In both cases, the curves then tend towards following the openloop output impedance as the frequency increases. The open-loop gain response of the OPAx134 is shown in Fig.9 (we discussed this in the February 2026 issue). This shows that by 100kHz, AO has dropped to about 45dB, that is, 125dB – 45dB = 80dB lower than at DC. This significantly decreases (1 + βAO), so the factor by which the output impedance is reduced decreases accordingly. 80dB is a factor of 104, so we expect the output impedance to be about 104 larger than at DC; 1mΩ × 104 = 10Ω, which is in line with the impedance value on the graphs in Fig.8. The fact that the beneficial effect of feedback reducing effective output impedance diminishes at high frequencies can impact circuit performance. One relatively well-known example is in Sallen-Key low-pass filters, where the gain can rise at high frequencies, after falling above the cutoff frequency, due to increasing output impedance being unable to compensate for signal feedthrough in the capacitor between the input network and the op amp’s output. [Editor’s note: I prefer multi-feedback topology filters as they do the same job with just one extra resistor and don’t suffer from this problem to the same extent, although they are not immune.] Whether the high-frequency impedance changes are important or not will 52 Fig.9: the open-loop response of the simulated OPAx134 op amp. depend on the specific details of each circuit and the signals being processed. Compensation We have discussed the fact that op amps are typically fully or partially compensated to provide stable operation in unity-gain or other low-gain configurations (eg, 3-5 times). This assumes that the capacitive loading or parasitics in the feedback loop are not sufficiently large to cause problems, which is not always the case in real circuits. Assuming the problem cannot be fixed by layout changes to reduce parasitics (eg, increasing the separation between signal and ground tracks), the stability of an op amp circuit that is unstable or has unsatisfactory phase margin can be improved by circuit modifications. As in the design of the op amp devices, this process is called compensation. It works by adding zeros or poles to the loop gain. The component values must be chosen correctly, because such modifications may not work or even make stability worse if not set up correctly. Also, changes in the load may shift the effect of any compensation circuit and hence affect stability, so working with a wider range of possible loads can be more challenging. Isolation resistor compensation circuit’s behaviour and help us select component values. Fig.10 shows a version of the circuit in Fig.2 with the isolation resistor added to provide compensation (RC). Like our analysis of the Fig.2 circuit last month, we will ignore the load resistance (RL) to keep things simple. Like last month, we will use the s-­d omain component values for the analysis. In Fig.10, we have a potential divider with RO (=ZO) forming the top part, and CL and RC in series forming the lower part (series impedance RC + 1÷sCL in the s-domain). This potential divider will contribute to the overall loop gain. The loop gain without the load and compensation resistor, which is -βAO(s), is multiplied by the potential divider factor of: R C +1/ s C L R O + R C +1/ s C L R C +1/ s C we can reAs in previous 1+sexamples, R C LL polynomials arrange the equation Cto get R sC O + R C +1/ L in s in the1+s numerator and denominator: ( RO + R C)CL R C +1/ s C L 1+s R C C L 1 R C +1/ s C L f p1+s =O +( R R + RR C ) CC L 2 π ( OR O + C) L 1+s R C Like the uncompensated case, a pole C 1 L is addedf to the loop 1 gain, but with the = p1+s R OR+ + RC ) C L f z2=π( at: pole frequency 2( πOR CRCCL) C L 11 f p =f = z2 π ( R O + R C ) C L 2π R C A simple approach to stabilising an op amp circuit with a capacitive load is to insert a resistor between the op amp output and the load. This is often called C L an isolation resistor because it separates, or isolates, the load from the op amp’s 1 output. The technique is also referred f z= 2 π RC C L to as an ‘out of loop’ compensation ap– RC ZO proach because the isolation resistor is Vout not inside the feedback loop. + CL As this is a relatively straightforward Vin approach, we will perform a simplified analysis of this circuit to obtain equa- Fig.10: isolation resistor (RC) tions that can provide insights into the compensation for improving stability. Vop RL Practical Electronics | April | 2026 Fig.11: an LTspice schematic for investigating isolation resistor based op amp compensation. That is different from the uncompensated case last month, which gave fp = 1 ÷ 2πROCL. The fact that this pole is at a lower frequency due to the resistance term increasing (from RO to RO + RC) is not ideal, as on its own, it would make things worse. However, the key impact of the isolation resistor is to add a zero to the loop gain. We have mainly been dealing with poles in our discussion of op amp circuits. Recall that the effect of a zero is opposite to that of a pole – it reduces the rate of decrease in gain (by 20dB/ decade) and makes the phase shift more positive (eventually by 90°). A zero can compensate for the effect of a pole caused R C +1/ sCL by the presence of a capacitive load or parasitics,Ras long as itsis R C +1/ Cat O+ L a suitable frequency. Zeros occur1+s at frequencies where the RC C L s-domain gain equation is zero, that is, ( R O + RofC the ) C Lequation is when the1+s numerator zero; in this case, 1 + sRCCL = 0. As in previous examples, we 1 substitute s = jω f p =find the magnitude, to get a = j2πf and 2 π ( RHertz: O + RC ) C L zero frequency in 1 f z= 2 π RC C L Compensation example The LTspice circuit in Fig.11 can be used to explore the use of an isolation resistor for compensation. Like the circuit in Fig.3, this uses the Universal­OpAmp4 idealised op amp models configured Practical Electronics | April | 2026 for loop-gain simulation. The three op amp circuits are unloaded (U1), loaded (U2) and loaded with an isolation resistor (U3). There is also an R C circuit that includes the resistance and capacitance values relevant to loading and compensation. In this circuit, R10 represents the op amp’s output impedance (RC = 35Ω), R11 represents the isolation resistor used for compensation (RC = 35Ω) and C3 represents the load capacitance (CL = 200nF). This circuit enables us to see the pole and zero due to the load and compensation separately from the op amp’s feedback loop. Investigating compensation components may need some trial and error, so in the Fig.11 circuit, the values are set via the LTspice parameter directive (.param), allowing all instances to be changed with a single edit. In LTspice, parameter values can be used in component values instead of directly using numerical values by writing the parameter name in curly braces (eg, {RO}) as the value. The output resistance value of the op amps is entered as {RO} in the parameter table accessed by right-clicking the component. With the values set, we can use the formulae discussed above to calculate the frequencies involved. We expect the pole in the loaded but uncompensated circuit to be at fp = 1 ÷ 2πROCL = 1 ÷ (2π × 100Ω × 200nF) = 7.96kHz (where 200nF = 200×10-9F). For the compensated circuit, we expect the pole to move to a lower frequency, fp = 1 ÷ 2π(RO + RC)CL = 1 ÷ (2π × [100Ω + 35Ω] × 200nF) = 5.89kHz. We can expect the zero to be at fz = 1 ÷ 2πRCCL = 1 ÷ (2π × 35Ω × 200nF) = 22.7kHz. 5-year collections 2019-2023 £49.95 2018-2022 £49.95 2017-2021 £49.95 2016-2020 £44.95 Purchase and download at: www.electronpublishing.com 53 Simulation results The simulation results are shown in Fig.12. The bottom pane shows the response of the RC model, while the upper pane shows the loop-gain responses of the three op amp circuits. The RC model plot shows the effect of the pole causing a decrease in gain and an increasingly negative phase shift, which is reversed by the zero as frequency increases. The pole and zero frequencies (5.89kHz and 22.7kHz, as we calculated) are marked by the vertical cyan lines. This plot is similar to the example showing a close pole and zero from our introduction to the topic in the January 2026 issue. The zero reverses the phase shift due to the pole before the full -90° is reached. It also limits the decrease in gain from the pole. On the upper plot in Fig.12, the green trace shows the unloaded circuit response. This features a standard low-frequency op amp pole, in this case at about 5Hz (here phase has shifted -45° from the 180° due to negative feedback inversion at DC). The phase shift levels out at 90° above about 100Hz. Phase margin annotation shows that it is very good for this circuit at 87°. The other circuit’s responses follow the same curve at low frequencies. There is also a high-frequency pole from the op amp beyond the upper range of the graph, which shows some effect on the phase shift of all the loop-gain plots above about 10MHz. The red trace in Fig.12 shows the uncompensated, loaded op amp response. We can see the pole at 7.96kHz, which is marked with the vertical red line. This second pole, due to the load capacitance, occurs at a relatively low frequency, causes the phase shift to approach 0° well before the loop-gain reaches unity (0dB), resulting in the poor phase margin of 1.7° shown in the annotation. This situation is similar to the circuits with poor stability from capacitive loading discussed last month. The yellow trace in Fig.12 shows the compensated, loaded op amp response. This includes a pole and zero due to the combination of the load and isolation resistor. This pole and zero match those from the RC circuit model shown in the lower pane. The cyan vertical lines show their frequencies. By comparing the yellow and cyan traces, we can see the effect of the compensated load on the loop-gain response. The phase margin annotation shows that the compensation has been effective at improving stability, with the value of 89° being similar to the unloaded circuit. Adding responses As mentioned above, the overall loop 54 Fig.12: the simulation results from the circuit in Fig.11. gain is equal to the basic loop gain of -βAO(s) (β = 1 in this case) multiplied by the potential divider factor due to the load capacitance, isolation resistor and op amp output impedance (modelled by the RC circuit). Multiplying gain magnitudes of series stages in circuits translates to addition when we represent the gain in decibels due to the properties of logarithms: log(A × B) = log(A) + log(B). In the lower pane of Fig.12, we see the gain of the RC circuit change from 0dB to -12dB over the range of approximately 1kHz to 100kHz. Looking at the loop-gain magnitude for the compensated circuit (yellow trace) in comparison with the unloaded circuit (green trace), which has a loop gain of -βAO(s), we see the gain of the compensated circuit drops by 12dB relative to the unloaded one over the same frequency range, then stays at that difference for higher frequencies. For example, at 100MHz, the two gains are -23dB and -35dB. Phase shift is related to delay, so contributions from circuits in series add. Again, we can compare the unloaded (dotted green) and compensated (dotted yellow) curves and see that if we add the RC model phase (dotted cyan) to the unloaded phase, we get the compensated phase curve. The RC model has zero phase shift at both low and high frequencies due to the opposing action of the pole and zero. The RC model phase curve dips to -36° between the pole and zero frequencies, and the compensated circuit’s phase curves dips by 36° from 90° down to 54° at the same frequencies. At low frequencies, the curves for the loaded but uncompensated circuit (red traces) are initially similar to the compensated curve as both have poles at similar frequencies, However the compensation adds a zero that causes the compensated response to stop deviating further (gain), or bend back towards (phase) the unloaded case at higher frequencies. Here, we see the presence of compensation mitigating or reversing the effects of the instability-inducing pole caused by the capacitive loading. Isolation resistor value If we know what the frequency of the zero introduced by the isolation resistor should be, we can use the formula above to calculate the resistor value. There is no single specific value that the frequency of the zero should be at for a given response to improve its stability, but there are some rules-of-thumb that can provide guidance. Looking at the overall pattern of the response with the compensation in place, we can note the general fact that at a decade above a pole or zero frequency, the majority of its influence on phase has occurred, concluding that the zero introduced by the isolation resistor should be a decade or so below the unity-gain (0dB) frequency of the circuit that needs compensating to have the desired effect on phase margin. With the help of the formula for the frequency of the zero, this rule-of-thumb can be used to help select an appropriate value. In Fig.12, we see that the condition is met. The unity gain (0dB) frequency of the loaded, uncompensated op amp loop-gain (red trace) is around 250kHz, which is a little over a decade above the zero frequency of 22.7kHz. Alternatively, we note that about half of the phase shift influence occurs in the decade below the zero frequency, so if we set the frequency of the zero equal to the Practical Electronics | April | 2026 Fig.13: an LTspice schematic for investigating isolation resistor compensation with OPAx134 op amps. unity-gain (0dB) frequency of the circuit that needs compensating, that may be sufficient to improve the stability of the circuit. This will give a resistor ten times smaller than the previous rule; suitable values are likely to be between these two cases. The pole due to the load capacitance would be fully cancelled if the zero was at the same frequency. This leads to another rule-of-thumb: that the frequency of the zero should be less than ten times the frequency of the uncompensated pole due to the load capacitor, so that the pole and zero are not too far apart. Looking at the formulae for the pole and zero (above), we see they differ in the resistance terms; using RC for the zero and (RC + RO) for the pole. If RC was much larger than RO, RO would have little influence on the pole frequency, and the two would be very close. This implies the use of a large isolation resistance might be useful, but we have to consider the effect of load resistance. So far we have ignored the possibility of a load resistance in parallel with the load capacitance (as shown in Fig.10). This was to keep the analysis simple and, in the simulations, to keep them matched to the analysis. However, a parallel resistance and capacitance combination is common (eg, a resistive load at the end of a long-shielded cable), so it must not be completely ignored. We can perform an analysis similar to the one above with RL included (as in Fig.10). The algebra involves more terms, so manipulating the equations is more cumbersome, but the results are similar; the pole shifts to a lower frequency and a zero is added to the loop gain. Practical Electronics | April | 2026 The pole and zero expressions can be written in terms of the parallel combination of RL with RC for the zero, and with (RC + ZO) for the pole. They then have a similar form to the formulae above. This makes sense as ‘looking’ from the output into the circuit, the load resistance is in parallel with the combination of RC and ZO. Also, if RL is infinite (not present or ignored), the parallel resistance part of the expressions reverts to the simpler versions given earlier. Including RL has some impact on the choice of isolation resistor in terms of pole and zero frequencies, but a more important concern is that RC and RL form a potential divider at the op amp’s output and hence change the overall closed-loop gain of the circuit. That is a major disadvantage of this approach to compensation for circuits requiring precision gain values. In the case of the sound card circuit, the overall gain is adjusted as part of the setup process to get the right signal levels, and the measurement is performed relative to calibration, so this would not be a problem. Still, in other applications, an alternative approach to compensation may be needed. OPAx134 example Fig.13 shows an LTspice schematic for loop-gain simulation of OPAx134 unitygain buffers that are unloaded (U1), loaded (U2) and loaded with isolation resistor compensation (U3). The results are shown in Fig.14. The unloaded and compensated circuits are stable; with similar phase margins, the loaded circuit is unstable. The uncompensated circuit has a unity gain frequency of 1.085MHz (see the annotation in Fig.14). Using the first Fig.14: the results from simulating the circuit in Fig.13. 55 Fig.15: an LTspice schematic for closed-loop simulation of the circuits in Fig.13. unity-gain-frequency-based rule above, we can get a zero at this frequency using RC = 1 ÷ 2πfpCL = 1 ÷ (2π × 1.085MHz × 20pF) = 7.3Ω (20pF = 20×10-12F). Using a decade lower frequency for the pole, in the variant of the rule, would give 73Ω. The pole frequency due to the uncompensated load capacitor can be calculated if we know the op amp’s output resistance. From Fig.8, we can assume it is about 54Ω, as the curve is quite flat around this value over the relevant range. This gives fp = 1 ÷ 2πROCL = 1 ÷ (2π × 54Ω × 20pF) = 146kHz. Using the pole-based Fig.16: results from the AC analysis simulation in Fig.15. Fig.17: results from the transient analysis simulation in Fig.15. 56 rule above, we get a maximum zero frequency of 1.46MHz. Using the same calculation as in the previous paragraph, the minimum isolation resistor value is 5.5Ω, which is not far from the 7.3Ω obtained via the other rule. The results in Fig.14 were obtained using a 10Ω isolation resistor, a round value a little larger than the minimum values from above. The shapes of the curves in Fig.14 follow a similar pattern to Fig.12, but with some more complexity due to the op amp’s high frequency behaviour. Fig.15 shows an LTspice schematic for simulating the closed-loop behaviour of the OPAx134 buffer unloaded (U1), loaded (U2), compensated (U3) and with a resistive load added (U4). Fig.16 shows the AC analysis results, and Fig.17 the transient analysis with a pulse input. In Fig.16, the gain response of the loaded circuit (red trace) shows a large peak typical of an unstable circuit. The two compensated (and stable) circuits have much smaller peaks. The circuit with the resistive load (cyan trace) has a gain of -0.83dB (0.909) rather than the unity gain of the buffer without the resistive load (yellow trace) due to the potential divider effect discussed above. In Fig.17, the unloaded (green trace), compensated (yellow trace) and compensated with resistive added load (cyan trace) circuits all have similar overshoot and minimal oscillation (stable behaviour). The unloaded and compensated circuits have similar phase margins, so the overshoot is similar, as discussed last month. The reduced gain of the circuit with the resistive load is also seen here. Next month, we will look at alternative approaches to stabilising an unstable or marginally stable op amp circuits. PE Practical Electronics | April | 2026