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Circuit Surgery Regular clinic by Ian Bell Measuring the frequency response of a circuit using a PC sound card, part 6: op amp capacitive loading I n recent articles, we have been looking at the measurement of frequency response. This was motivated by the need to measure the response of a digital filter (from our series on DSP) without using advanced lab test equipment. We covered the general principles of frequency response measurement and use of the sound card (audio interface) of a PC or laptop together with free software called Room EQ Wizard (REW). Recently, we have been looking at the signal conditioning that is needed to interface a circuit to the sound card’s line inputs and outputs. Op amp circuits are the key building blocks of the circuitry. Last month, we covered concepts relating to op amp amplifier feedback, frequency response and stability. This month, we will consider conditions that may cause op amps to become unstable, in particular, capacitive loading of the output and how to simulate Feedback and stability recap Op amps have very high open-loop gain; too high to use directly. Therefore, negative feedback is applied, in which a fraction (β) of the output is subtracted from the input signal. The use of negative feedback in op amp amplifiers provides significant advantages in circuit performance and ease of design (op amps have always been intended to be used with negative feedback). There are three different gain values that can be used when discussing an Pole 1 Ao Gain (dB) these circuits and measure phase margin. This is relevant to the signal conditioning circuit because of potentially high capacitive loads presented by circuits under test, and any long audio cables which may be used. However, our investigations are also more widely applicable to op amp circuit design for other applications. Ac Closed loop response Open-loop response Unity gain bandwidth 0 Pole 2 f0 –90 –180 180° Total loop phase shift Loop delay phase shift 0 Closed loop bandwidth Log frequency Log frequency 90° Phase margin 0° Fig.1: determining the phase margin of an op amp from its frequency response and phase plot. 32 amplifier with feedback. The op amp on its own (without feedback) has an open-loop gain (AO). Amplifier circuits with feedback have a closed-loop gain (AC) value. The value -βAO is the loop gain, which is the gain around the closed feedback loop. The signal inversion that makes the feedback negative is equivalent to a phase shift of 180°, which is by convention taken as positive (±180° phase shifts are the same for a steady sinewave). As the frequency increases, the phase shift from the delay around the loop becomes more negative, so the effective phase shift reduces from 180° towards (and then past) 0°. If the total effective phase shift from inversion and delay is 0° or an integer multiple of ±360°, the feedback will be positive rather than negative. If the gain at the frequency where this occurs is unity or more, the circuit can enter sustained oscillations and the amplifier is deemed to be unstable. In an ideal amplifier, the oscillation amplitude could continuously increase, but in real circuits the amplitude is limited by non-linearities (eg, the limited supply rails). Amplifiers that are close to being unstable will not oscillate continuously, but may produce undesirable outputs, such as large overshoot and severe ringing (decaying oscillations) when input transients occur. The term ‘unstable’ is often used in such cases anyway. Changes in conditions such as temperature, supply voltage or component ageing may shift a marginally stable circuit into continuous oscillation. To avoid this, we can measure how close a circuit is to being unstable using phase margin or gain margin. Phase margin is the difference between the phase shift of the loop gain due to delay and -180° (see Fig.1). Typically, 45° is regarded as acceptable, but this is a rule of thumb and not universally used. Applying more feedback (a larger β value) results in a greater Practical Electronics | March | 2026 likelihood of instability, so low-gain op amp amplifiers are more likely to oscillate. The open-loop gain of most op amps is deliberately reduced at high frequencies so unity-gain amplifiers are stable. This is commonly achieved using dominant pole compensation, which creates a low frequency (typically 1-10Hz) pole in the open-loop response (Pole 1 in Fig.1 is typical of an op amp dominant pole). Above this frequency, the open-loop gain falls off (from AO) at 20dB per decade until another pole or zero occurs. The closed-loop gain (AC) remains flat until frequencies at which it approaches the open-loop gain (see Fig.1), which is at a high frequency because AO is very large for most op amps. If we multiply the closed-loop gain by the closed-loop bandwidth, we get the gain-bandwidth product (GBP or GBW). A feature of dominant pole compensated frequency responses is that the GBP is constant. Capacitance in the feedback loop Last month, we briefly discussed the fact that capacitance in the feedback loop of an op amp will modify the frequency response of the feedback loop (the loop gain). Any change to the loop gain’s response will change the stability of the op amp; it may get better or worse, depending on the specific change in the loop response. We also showed an example of the impact of capacitance at the op amp’s input, which introduced an additional pole in the loop response. The key locations for possible capacitance in an op amp amplifier’s feedback loop are from the op amp’s input to ground, across the feedback capacitor, and at the op amp’s output. Capacitance at the input and output are most likely to cause instability, whereas capacitors are quite commonly added across the feedback resistor to improve stability. Parasitic capacitance All the loop-gain influencing capacitances can be present as parasitic or stray capacitance – the unwanted capacitance inherent in the components and interconnection (eg, wires and PCB tracks), and the op amp’s internal capacitances. Fig.2 shows an example amplifier circuit with the parasitic capacitance from the Cp2 RI – Vin RF + op amp’s input capacitance. So, in most cases, it will be relatively small. On the other hand, capacitors may be specifically connected to the output, and the capacitance from the next stage inputs plus the potentially much longer interconnects may be significantly higher than that seen at the input. Unity-gain op amps are often used to buffer DC voltages in circuits such as mid-supply references or voltage reference IC outputs. Often, relatively large capacitors are used on the outputs of these circuits to stabilise the reference voltage during transients. In our sound card interface signal conditioning circuit, we used a split supply, so did not use a mid-supply reference. However, this approach could be used in a version of the interface, if required. Reference buffers and mid-supply references can suffer instability problems due to the large output capacitances used. It may not be obvious, as these circuits are used for DC purposes; however, the op amp buffer is still an AC amplifier and could be triggered into temporary or sustained oscillations. In audio or other AC contexts, the capacitance on the output (load) is typically from the input capacitance of the next stage and from cables used to connect systems together. For example, RCA (phono) audio cables typically have capacitances of 40-150pF/m. Some lower and significantly higher values may be found in certain cables. Fig.3 shows an op amp non-inverting amplifier with a capacitive and resistive load (CL and RL, respectively). We have labelled the op amp’s internal output impedance (Zo) as an impedance for generality, but it may often be considered simply to be a resistance (RO). The op amp’s output impedance will interact with the load capacitance and is therefore important when considering the impact of capacitive loading on the op amp. Circuit analysis We will analyse a simple version of the circuit in Fig.3, where RL is not present (this implies a very high load resistance) and we are using a unity gain buffer, so RF – Vout Vin Cin Cp1 wiring, components (Cp1 to Cp3) and the op amp’s input capacitance(Cin). Parasitic capacitance values will depend on the layout of the constructed circuit, but will typically be in the low picofarad range. For example, in 2014, Dave Jones from EEVblog measured the capacitance between rows on a solderless breadboard because there was no definitive value published that he could find. The result was 2-3pF range (see https:// youtu.be/6GIscUsnlM0). Generally, keeping parasitics as small as possible will reduce problems. There is not much you can do about it when using solderless breadboard, which limits its use in high-frequency circuits. For PCB layouts, make sure tracks on the inverting input are short, for example by placing both gain setting resistors as close as possible to the inverting input pin. The capacitance at the input pin can also be reduced by removing any ground plane in the area under the connections to the pin, although this could increase interference pickup. The interaction between all the stray capacitances in different parts of the feedback loop and the op amp’s frequency response is complex and may be difficult to predict, as the exact value of the parasitics may not be known. However, if you want to get into the details, there are software tools available that will calculate PCB trace capacitances. Different construction techniques and different layouts for the same circuit will have different parasitics. This means that if two copies of the same circuit are constructed differently, one may be OK, while the other is unstable. I remember someone building an op amp circuit that was fine on solderless breadboard, but which oscillated when built as a neat-looking (but maybe not so well designed) PCB. I do not remember the details, but it serves to illustrate that stability can be a tricky problem. Op amp input capacitance also contributes to the capacitance in the loop (see Fig.2). This is often not specified on device datasheets and is difficult to measure, so again, this leads to uncertainty about the exact situation you have in a particular circuit. Typically, op amp input capacitances are in the range of 2-20pF, depending on the type of op amp. Analog Devices provides some example values in an article on measuring op amp input capacitance (https://pemag. au/link/acal). Vout Cp3 Fig.2: parasitic capacitances in an op amp feedback loop. Practical Electronics | March | 2026 + Capacitive loading In an op-amp-based amplifier, the capacitance at the op amp’s inverting input is likely to be just the stray capacitance of the local connections between the gain resistors and the op amp pins, plus the ZO Vop CL RL RG Fig.3: an op-amp-based amplifier circuit showing output impedance and load. 33 – Idealised AO GBP Vin + RO Vout CL Fig.4: a simple model of the effect of capacitive load on a unity-gain buffer. RF=0 and RG is not present. It is a good idea to use the case of a unity-gain buffer because, as mentioned above, this circuit is most likely to be unstable. We will assume that the op amp’s output impedance is a resistance (RO). Consider an idealised op amp that has specific open-loop gain (AO) and GBP, with dominant pole compensation, but no other poles, zero output impedance and infinite input impedance. It could drive a capacitive load with no impact on its behaviour due to its zero output impedance. Therefore, as noted above, we need to include the op amp’s output resistance to model the effect of load capacitance. This leads to a simple model with an RC circuit formed by RO and CL in the feedback loop (see Fig.4). To analyse the circuit, we will use the s-domain component values for the RC circuit, as discussed in recent articles. In Fig.4, we have a potential divider formed by RO and CL, which will contribute to the overall loop gain. Without the RC circuit, the loop gain is -βAO, where for the idealised unity gain amplifier β=1 and is not frequency-dependent. AO has a single low-frequency pole (like pole 1 in Fig.1) due to the op amp compensation, so we write AO(s) to remind us that it is frequency-dependent. With the capacitive loading included, the loop gain becomes: −1/ s C L β A0 ( s) R O +1/ s C L This is obtained by multiplying the existing loop gain by 1 the potential divider ( s ) that β A 0(recall equation−for the RC circuit 1+s R O C L capacitive reactance in the s-domain is 1/sC). As we did in the January article, we Fig.6: the simulation −1/ s C Lresults for the circuit in Fig.5. β A (s) 0 rearrangeR the RC part to get polynomials O +1/ s C L in s in the numerator and denominator: − 1 β A0 ( s) 1+s R O C L We see that the output resistance and load capacitance combined contribute a pole at 1+sROCL=0 (where the s-domain gain is infinite), which is the same as for an RC circuit on its own. As in previous examples, we substitute s = jω = j2πf and find the magnitude to get a pole frequency of f = 1 ÷ (2πRC). This is very likely to be at a much higher frequency than the dominant pole from the op amp’s compensation, so it will correspond to pole 2 in Fig.1. Adding the capacitive load does not change the pole in AO(s), but if the two poles happened to be very close in frequency (unlikely in typical op amp circuits), they would not show as two obviously distinct features in the response as in Fig.1. In this idealised scenario, the circuit must be stable without the capacitive load because the single pole AO(s) only provides -90° of phase shift. With the additional pole provided by RO and CL, the phase shift can reach 180° and potentially cause instability. We can simulate some examples to illustrate this. If we have a complex situation (eg, the load resistance RL is present), we proceed with the analysis in the same way as above, but the algebra will have more terms. Capacitive load simulations The Fig.5 schematic contains two versions of the op amp loop gain simulation circuit discussed last month. The circuits are configured for unity gain by setting the feedback resistors to zero and the grounded resistor to a very high value (10GΩ) so it is more-or-less open circuit. There are two copies of the circuit, one with and one without a capacitive load, to facilitate comparison. The op amps in the circuits in Fig.5 are idealised generic devices using LTspice’s UniversalOpAmp4 model. This model was chosen because it has an output resistance that can be set via the device’s parameters (right-click the symbol), which we need for this simulation. Other lower­-numbered (simpler) UniveralOpAmp models do not provide this. UniveralOpAmp4 has two poles in its open-loop gain. Like last month, I used AO= 1.778 × 106 (125dB) and GBP = 8MHz to provide a reasonable match to the OPA2134 used in the sound card interface. Fig.5: an LTspice schematic for simulating the loop gain of ideal op amp with capacitive loads. 34 Practical Electronics | March | 2026 For this simulation, we ideally want a single-pole op amp to match the preceding discussion, so the second pole of the op amps in this example was pushed to a high frequency by setting a high phase margin (130°). We are just looking at the general form of the response, so can choose arbitrary values for the op amp output resistance and load capacitance. To obtain a clear graph, we need a pole frequency well above the op amp’s low frequency pole, but also away from the high frequency second pole. The UniveralOpAmp4’s default output resistance (Ro) is 1kΩ, but I increased it to 2kΩ for this example, which together with the 5nF load capacitor should produce a pole in the loop gain at 1 ÷ (2πRC) = 1 ÷ (2π × 2000 × 5 × 10-9) = 15.9kHz. The UniveralOpAmp4 model has input capacitance, both common mode (Ccm) and differential (Cdiff), which I changed to zero so that only the load capacitor and the op amp poles were influencing the frequency response, in line with the analysis above. The results from the simulation in Fig.5 are shown in Fig.6. As explained last month, we plot vfb ÷ vai to show the loop gain of the amplifier. In Fig.6, we see that the circuit without the capacitive load (green traces) has a single low-frequency pole from the op amp’s internal compensation. The op amp’s high-frequency pole is beyond the range of the graph, so we just see a simple single-pole response. The circuit with the load capacitor (orange traces) has an additional pole at 15.9kHz, in line with the analysis above. Fig.6 shows the pole frequency measured by placing a cursor at the point where it causes -45° of phase shift relative to much lower frequencies. To find the pole frequency this way, we need any adjacent poles to be well separated. The phase shift due to the low-frequency poles has levelled out at 90° before any significant shift due to the second pole, so the condition is met here. When using the cursors in AC analysis, they are attached to the gain curve by default. To measure on the phase curve, click the radio button to the right of the phase measurement to select it in the cursor readout display, as shown in Fig.6. The phase margin of the loop gain in the circuit with the capacitive load is about 2.4° - this is the amount of phase above 0° on the graph at the point where the gain falls to unity (0dB). The -177.6° from the delay in the loop is close to cancelling the 180° from the negative feedback signal inversion. 2.4° is a very poor phase margin, indicating potential instability. Fig.7: simulating the loop gain of an op amp with various capacitive loads. (ignoring the UniveralOpAmp4 high frequency pole, which is not visible on Fig.6), so the maximum phase shift due to delay is -180°. The results produce straightforward frequency responses that match closely with the simple example analysed above. This is useful for understanding the fundamentals, but real circuits will exhibit more complex behaviour. We will look at some examples using the OPAx134 op amp from the sound card interface. Fig.7 shows three circuits similar to those in Fig.5 but with the real op amp model. The three circuits have different capacitive loads of zero (for U1), 1nF (for U2) and 2nF (for U3) so we can compare their responses. Creating multiple copies of a circuit (as in Figs.5 & 7) is straightforward using the duplicate tool from the LTspice toolbar. The components are automatically given new names, but user-named nets (wires) are not renamed, so you must remember to do this manually where needed. Otherwise, the simulation will give erroneous results or may fail with an error. For example, in this circuit, the supplies (nets VCC and VEE) do not need to change as they are the same for each circuit, but the signal nets fbx, aix and opx must be named differently in each copy. Nets that have not been given names manually will be automatically given new unique names, but should not be used for plotting. It is a good idea to name signals that you want plot results for; otherwise, it will not be clear from the name on the plot what the signal is. Fig.8 shows the results of simulating the circuits in Fig.7. We can see that the circuits with the capacitive loads (orange and red traces) have an additional pole in the low megahertz range. The gain decreases more rapidly above this frequency, and the phase shift at frequencies above about 1MHz is significantly higher for the loaded circuits. Simulation with the OPAx134 This example (and the analysis above) is idealised and only involves two poles Practical Electronics | March | 2026 Fig.8: the simulation results for the circuit in Fig.7. 35 Simulation files Most Circuit Surgery columns feature the use of the free circuit simulation software LTSpice. It is used to support descriptions and analysis in Circuit Surgery. The examples and files for this issue are available for download: https://pemag.au/link/ac9b Fig.9 shows a zoom-in on Fig.8 at the unity gain (0dB) point of the three curves, with the phase shift graph moved so that 0° phase shift aligns with 0dB and scaled so that an appropriate range fits on the plot. This makes reading the phase margin straightforward. The relative position of the gain (left axis) and phase (right axis) graphs is arbitrary and can be chosen to help present the data effectively. From Fig.9, we can see that the phase margin for the unloaded circuit is about 54°. For the 2nF load, the phase margin is very slightly negative (implying instability). Fig.9: a zoom-in on simulation results for the circuit in Fig.8. Annotation and LTspice FRA Last month, we briefly discussed LTspice’s transient Frequency Response Analysis (FRA) (.fra command), which uses a stepped frequency sinewave to plot the loop gain of a circuit. We will look at using this with the capacitive load in a moment. First, it is worth noting that using FRA automatically annotates the frequency response graph with the phase margin, which is useful as it saves trying to measure it manually from the graph. However, this annotation is not exclusive to the FRA. You can add the gain and phase margin annotations to an AC analysis result (as shown in Fig.10) using “Notes & Annotations” from the right-click menu of the graph background. Select the “Annotate Phase Margin” (or gain margin) from the menu. By default, this shows the data for just the first trace, but if you attach a cursor to one of the other traces, the data relevant to that trace will be added to the plot. To attach a cursor, click the trace name at the top of the plot. The annotation does not state which trace it relates to, but you can change the text colour to match the trace (as in Fig.10) or edit the text (right-click the text to do this). You may also need to move the annotation to a more convenient location using the Move tool from the Toolbar. Fig.11 shows an LTspice schematic for running an FRA for a unity-gain buffer with capacitive load. The results (with a 1nF load) are shown in Fig.12. This shows the circuit is marginally stable, 36 Fig.10: phase and gain margin annotations added to an AC analysis. Fig.11: the LTspice schematic for FRA of a unity-gain buffer. with a phase margin of 5.7°, which is not exactly the same as the value from the AC analysis (0.51° in Fig.10). Running the FRA without a capacitive load indicated a phase margin of 53.5° (graph not shown), very close to the 53.6° from the AC analysis. The FRA uses transient analysis with the full model of the op amp, whereas the AC analysis uses a linearised model. The FRA should be more accurate, but if oscillations occur in the FRA transient analysis, the results will not be valid. Oscillations will Practical Electronics | March | 2026 5-year collections 2019-2023 £49.95 2018-2022 £49.95 2017-2021 Fig.12: the FRA results from the circuit in Fig.11 with a 1nF load. £49.95 2016-2020 £44.95 Purchase and download at: www.electronpublishing.com Fig.13: the FRA results from the circuit in Fig.11 with a 2nF load. The results in Figs.9 & 10 indicate that the circuit is unstable with a 2nF load. If we run the FRA with a 2nF load capacitor, we get the results shown in Fig.13. This is clearly erroneous, because the loop gain at low frequencies, which should be the same in all cases (as seen in Fig.10), is very different (60dB in Fig.13 vs. 125dB in Fig.10). There are also significant irregularities in the curves in Fig.13. For circuits that oscillate in the FRA, you have to use AC analysis to get the response curves. Of course, the AC analysis results for an unstable circuit are fictitious in a way – the circuit does not actually work as an amplifier with the loop gain or circuit gain indicated. However, it is useful as an analysis tool to indicate how much the curves need to shift to obtain stability. Closed-loop response Fig.14: an LTspice schematic for simulating buffers with different loads. not occur in the AC analysis, which is not using the time domain; it is just calculating the gain and phase shift at specific frequencies. With a 1nF capacitive load, the unitygain buffer is very close to being unstable, Practical Electronics | March | 2026 but should not oscillate continuously, particularly in a simulation where there is no noise or other disturbance to trigger it, and in which we do not apply any abruptly changing inputs (the FRA uses smoothly changing sinewaves). Above, we have described special techniques to obtain the loop gain of the circuits, from which we can directly find phase margin. Or course, we can also run standard transient and AC analysis of the closed-loop circuits to observe the circuit’s behaviour, including oscillations due to instability. In a similar approach to the AC analysis discussed above, Fig.14 shows a schematic for the transient analysis of three versions of an OPAx134-based unity-gain buffer with different capacitive loads of zero (for U1), 1nF (for U2) and 2nF (for U3). The simulation is configured to provide a 100mV step input to the op amp (a pulse waveform). 37 The results are shown in Fig.15. The circuit with no capacitive load produces a more-or-less clean reproduction of the input step, with just a small overshoot (top plot pane, green trace). With the 1nF load, a circuit we know is very marginally stable, there is significant overshoot and a decaying oscillation – this is a case of very severe ringing (middle pane, orange trace). For the 2nF load, the unstable case, there is sustained oscillation, which initially ramps up in amplitude after the step input (bottom pane, red trace). Fig.16 shows a zoom-in of the waveforms around the step transition time. We can see that the unloaded circuit just overshoots and settles quickly; there is effectively only about one cycle of oscillation. The cursors have been placed on the ringing from the 1nF loaded circuit and show an oscillation at around 4.5MHz, which is close to the 4.485MHz 0dB (unity gain) frequency shown in Fig.10. From the theory discussed last month, we would expect the oscillation to occur at the loop gain 0dB frequency. We can also apply a sinewave isngal using the same schematic as in Fig.14, with the V1 source configured appropriately. Using SINE(0 0.1 1k) produces a 100mV peak 1kHz sinewave. The results are shown in Fig.17, which uses the same order and colours for the signal as Figs.15 & 16. The unloaded circuit and the circuit with the 1nF load both output a clean sinewave. There is no indication of problems with the 1nF load here, unlike the severe ringing with the step input. The smooth nature of a sinewave means it is less likely to trigger decaying oscillations than a step input, but this does not mean it will never happen in a physical circuit, particularly as other factors (noise, interference, supply glitches etc) could act as a trigger. The circuit with the 2nF load is unstable and therefore oscillates with the sinewave input. Fig.18 shows the results of a closedloop AC analysis for the OPAx134 unity gain buffer. This was obtained using the schematic in Fig.14 but with C1 = 250pF (U2, op2, cyan trace) and C1 = 1nF (U3, op3, orange trace). U1 has no capacitive load, as in the previous examples (op1, green trace). These capacitor values avoid the unstable circuit with the 2nF load (although the AC analysis will run OK with a 2nF load, a physical circuit would not produce useful results). The results shown in Fig.18 indicate that the amplifier tends to have a peak in the closed-loop gain around the 0dB point in the loop gain. Gain peaking is measured in dB relative to the flat (low-frequency part) of the closed-loop gain curve, as shown for op2 in Fig18. Increased capacitive load (and 38 Fig.15: the results from simulating Fig.14. Fig.16: a zoom-in on the step response in Fig.15. Fig.17: the response of the circuits in Fig.14 with a sinewave input. Practical Electronics | March | 2026 hence a poorer phase margin for this circuit) results in larger peaking in the gain. Indirect phase margin measurement Fig.18: the AC Analysis results for the circuits in Fig.14 with C1=250pF and C2=1nF. Fig.19: measuring overshoot. Fig.20: an LTspice schematic for measuring overshoot. Practical Electronics | March | 2026 The closed-loop results above show that overshoot and gain peaking vary with capacitive loading. It follows that there is a relationship between the amount of overshoot and peaking and the phase margin. This is potentially useful because it is difficult to measure loop gain directly on physical circuits (to obtain phase margin). It is also not totally straightforward in simulation; you have to insert the FRA device or voltage source in the loop, as we have done in these articles. Measuring overshoot or gain peaking could allow you to indirectly measure phase margin if you knew the relationship between them. Texas Instruments provides curves of these relationships in a presentation on measuring op amp stability – see the PDF at https://pemag.au/link/acam They indicate that these curves are obtained from the mathematical relationship between the quantities, but do not give any details. It may be based on relating a generic system equation (eg, a second-­order system), for which the Q (or damping factor) to overshoot or peaking relationship is known, to the shape of op amp response. The phase margin can be related to pole frequencies, which in turn can be mapped to the generic response equation. I was interested to see how well the Texas Instruments curves correspond to the simulation results with the OPAx134. I obtained values for overshoot and phase margin over a wide range from no load to close to fully unstable. This was done using the approaches described above, but I used a 12mV rather than 100mV step in line with Texas Instruments’ recommendation to use output steps in the 10-20mV range to prevent other aspects of op amp behaviour influencing the results. For this approach, you have to apply the step waveform directly to an op amp input to get a valid result (intervening circuitry may distort the step), but this was already the case here anyway. As shown in Fig.19, overshoot is the difference between the peak voltage caused by the step input and the final stable output voltage after the ringing has settled to zero (or some minimal amount). The step value is the voltage change, which takes account of any offset (Fig.19 shows a 12mV step with 0.4mV offset). Overshoot can be expressed as a percentage of the step value. Measuring the overshoot manually is a little time consuming, but it can be automated using an LTspice .meas directive. Fig.20 shows an LTspice schematic for implementing this. This is similar to Fig.14, but instead of drawing multiple copies of the buffer amplifier, we use a single circuit 39 in the overshoot simulation were simulated using a version of Fig.7 to obtain the corresponding phase margins. The comparison with the Texas Instruments curve is shown in Fig.21. The match is reasonably close but not perfect. This may be because the Texas Instruments curve assumes a generic system response (as mentioned above) but the op amp has a more complex behaviour. However, the Texas Instruments curve provides a reasonable estimate for the phase margin. I used AC analysis for the phase margin as it was quicker than FRA, but FRA may have produced results closer to the Texas Instruments curve at low phase margins. Conclusion Fig.21: the approximate relationship between step response percentage overshoot and phase margin. with a parameterised load capacitor. Only part of the capacitor value list is shown to save space. The capacitor value for C1 is written as {CL}, where the curly brackets (braces) denote a parameter value, which can be set using the .param directive or stepped through multiple values using the .step directive. The .meas directive can be used to evaluate various useful values from simulation results. In this case, we obtain the maximum value of the op amp output voltage (using MAX V(op1)), which is the value of the peak voltage of the overshoot. Values obtained using .meas are printed in the simulation log text file, which can be viewed using View → Spice Output Log from the main menu after the simulation runs. The table of values can be copied and pasted into a spreadsheet to facilitate further calculations and plotting of data. In this case, the percentage overshoot was calculated using 100 × (max(Vop1) – Vstep – Voffset) ÷ Vstep. The same load capacitor values used You have to be a bit careful about the capacitances connected to an op amp, especially a high-bandwidth type. Sometimes an op amp will appear to be relatively stable, but a transient ‘shock’ could kick it into oscillation if the configuration doesn’t have enough phase margin. Worse still, you could have a prototype that works fine, but another unit built from a different batch of ICs could be unstable. Even if it doesn’t enter sustained oscillation, it could still ‘misbehave’ under the right (or wrong) conditions unless PE you do your homework. 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Plus: nika, MikroElektro Microchip pe L-Tek PoSco software The free CD-ROM provides a practical introduction to PIC microcontrollers Plus MikroElektronika, Microchip and L-Tek PoScope software In 2 TeachLtd nicsorne dsPIC are Publishing PIC and rated Ele©ctro MPLAB, logy Incorpo ogy 2013 Wimb and logo, Techno Technol ip ip name of Microchip Microch .09 arks 016-02 The Microch s. © 2013 ed tradem countrie 1. MCCD1 register d. Issue and other in the USAAll rights reserve Inc. PLUS 3 09:59:25 29/07/201 d 1 Teach In 2 - JUL13.ind Teach In 5 Cover.indd 1 06/05/2010 16:22:29 10 13:21:42 ELECTRONICS TEACH-IN 5 EE M FR -RO CD FROM THE PUBLISHERS OF 15 design and build circuit projects for newcomers or those following courses in school and colleges. CIRCUIT SURGERY Pu rne bo im ELECTRONICS TEACH-IN 5 – CD-ROM JUMP START 29/07/2013 10:00:29 PIC’n’ Mix – starting out with the popular range of PIC microcontrollers and Practically Speaking – tips and techniques for project construction. 29/04/20 dd 1 CD Cover.in ELECTRONICS TEACH-IN 4 – CD-ROM A BROAD-BASED INTRODUCTION TO ELECTRONICS Mike & Richard Tooley The Teach-In 4 CD-ROM covers three of the most important electronics units that are currently studied in many schools and colleges. These include, Edexcel BTEC level 2 awards and the electronics units of the Diploma in Engineering, Level 2. The CD-ROM also contains the full Modern Electronics Manual, worth £29.95. The Manual contains over 800 pages of electronics theory, projects, data, assembly instructions and web links. A package of exceptional value that will appeal to anyone interested in learning about electronics – hobbyists, students or professionals. 40 ELECTRONICS TEACH-IN 4 Three Teach-ins for the great price of EE M FR -RO CD £8.99 FROM THE PUBLISHERS OF A BROAD-BASED INTRODuCTION TO ELECTRONICS FREE CD-RO M WORT H £29.9 5 i An eleven part tutorial i uses inexpensive circuit simulation software FREE M CD-RO THE MODERN ELECTRONICS MANuAL The essential reference work for everyone studying electronics i Over 800 PDF pages i In-depth theory autorun, should This software in Windows if not, open double-click and f Explorer index.pd requires This CD-ROM Reader™ from Adobe® dable Free Downloa be.com www.ado L ANUA BA SE M .co.uk £18.95 PLUS you also get the contents of the free CD-ROM from each issue... ... so that’s another TWO Teach-Ins and The Full Modern Electronics Manual! i Extensive data tables and web links What a Bargain!! magLtd. 2011 ng www.epe ne Publishi © Wimbor Teach In 4 Cover.indd 1 The CD-ROM also contains: n Complete Teach-In 2 book, a practical introduction to PIC microprocessors n MikroElektronika, Microchip and L-Tek PoScope software. 14/11/2011 20:33:21 Practical Electronics | March | 2026