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Circuit Surgery Regular clinic by Ian Bell Measuring the frequency response of a circuit using a PC sound card, part 5: op amp frequency response & stability I n recent articles, we have been looking at measuring frequency responses. This was motivated by the need to measure the response of a practical implementation of an example digital filter (from our series on DSP) without advanced test equipment. We covered the general principles of frequency response measurement and the use of a “sound card” (audio interface) in a PC or laptop together with a free app called REW (Room EQ Wizard). Recently, we have been discussing the signal conditioning that might be needed to interface the circuit under test to the sound card’s line inputs and outputs. These circuits contain operational amplifier ICs (op amps), so this month we will take a detailed look at op amp frequency response and its impact on amplifier performance, particularly the possible problem of instability. The interface circuit can be connected to a wide range of loads, and there is potential for some loads to cause problems. This month, we will consider op amps in general, so our discussion will have wider application than just to the sound card interface. Feedback structure Fig.1 shows the structure of a generic feedback system. This is not a circuit diagram – it represents the relationship between signals, rather than showing specific components and wiring. It can apply to both inverting and non-­inverting op amps, but there are differences in some details. We can use this diagram to help Circuit input signal Vinp Input Network N NVinp N=1 for signals as shown. Applies to non-inverting amplifier. Mixing Network + Amplifier input signal Vai ± Feedback signal some devices have much higher gains, and others lower, related to requirements in specific applications. It is not practical to use this high gain directly as a linear amplifier, but it provides the potential for very good performance, and straightforward circuit design, when negative feedback is applied. The output of the amplifier block is vO = AOvai for the non-inverting amplifier and vO = -AOvai for the inverting amplifier. The feedback signal (vfb) is obtained from the output of the amplifier (vO ) by passing it through the feedback network (a resistor-based potential divider in the op amp circuit), which multiplies it by a factor of β, so vfb = βvO = ±βAOvai . β is known as the feedback factor, and typically β ≤ 1. The feedback is either added to (inverting amplifier) or subtracted from (non-inverting amplifier) the input signal by the mixing block. The overall effect, taking into account the sign of AO, is subtraction – hence negative feedback. There are three different gain values that can be used when discussing an amplifier with feedback. These relate to the three paths in the block diagram shown in Fig.4: 1) The amplifier block on its own has an open-loop gain of AO = ±vO ÷ vai 2) The whole circuit (amplifier with feedback) has a closed-loop gain of AC = ±vO ÷ vinp 3) -βA O is the ‘loop gain’, the gain around the closed feedback loop + Referring to Fig.1 (with N=1 for the non-inverting amplifier), we can calculate the closed-loop gain in terms of Amplifier output signal Circuit output signal Vo Vo ±Ao Op Amp Feedback Network Vfb Vo β Fig.1: the structure of an amplifier with negative feedback (shown here as non-inverting). 42 define and analyse key concepts relating to op amp feedback. The signals in Fig.1 could be either voltages or currents, but we have labelled them as voltages. The input signal (vinp) may pass through an input network, which multiplies the input by a factor N. For the non-inverting op amp (Fig.2), the input goes straight to the op amp, so N=1. Fig.1 is labelled on the assumption that N=1, as this is the simplest situation, but it is not always the case. For the inverting op amp (Fig.3), the resistors form a potential divider for the input signal, so the input network is not unity gain. After the input network, the signal passes to the mixing network, the output of which is the feedback signal (vfb ) subtracted from the input (vinp ) to give the input to the amplifier block (vai ). This function is performed by the op amp, so it is not a separate component in the implementation. For the non-inverting amplifier, the op amp’s differential amplifier operation achieves the subtraction. For the inverting amplifier, the ‘summing junction’ shown in Fig.3 adds signals at the inverting input (it’s effectively subtraction because the feedback is from the output that is obtained via the inverting input). The amplifier block represents the open-loop gain of the op amp (AO), that is, the gain of the op amp without any feedback. The op amp amplifies the difference between its two inputs by AO. A O is typically in the order of 10 5 to 106 times (100dB to 120dB), although Vinp Vo – Gain calculations RF RG RF Vinp RI – + Fig.2: a non-inverting op amp based amplifier circuit. Vo Fig.3: an inverting op amp based amplifier circuit. Practical Electronics | February | 2026 Circuit closed-loop gain A C = Vo / Vinp Vinp N Vinp Vai + Vo Vo ±Ao − Vfb Break in loop to define loop gain Amplifier open-loop gain AC = Vo / Vai Loop gain –βAo = V' fb / Vfb V' fb β Vo Fig.4: the relationship between open-loop gain, closed-loop gain and loop gain, for N=1 as in Fig.1. I expect people have often first used the well-known op amp formulae such as AC = -RF ÷ RG without wondering why there is nothing related to the op amp itself in the calculations. Of course, we can’t be too complacent – the op amp does play its part; in particular, variation of the open-loop gain with frequency means that βAO ≫ 1 does not always apply. Inverting amplifiers In the preceding discussion, we used N=1 in Figs.1 & 4, which applies to the non-inverting amplifier. For the inverting amplifier, the input block does not have unity gain. The circuit input passes through the potential divider formed by the two resistors. It may not be obvious that we have a potential divider in this circuit because we don’t have a simple case where one of the resistors is grounded (as RG is in the non-inverting amplifier). However, when analysing linear circuits with multiple vo AO voltage sources, we can treat each source AC= = separately and then add up their contribuv inp ( 1+ β A O ) tions to the voltage on the node of interest. In a typical1op amp circuit, AO is very To calculate the contribution of one large and A Cβ=is a moderate fraction, so βAO source, we set all the others to zero (this β larger than 1 and we can is the superposition theorem in linear is usually much v AO approximate (1 βAO)oto= βAO. Then the circuit theory). So, in the inverting amA+C = R Gto give: v AO terms cancel plifier (Fig.3), the contribution of vOUT to 1+ β A ( inp O) β= the total voltage at the summing junction RG + R F is found by setting vinp = 0. 1 C= ) A Now −A( 1−β ( 1−β ) 1 we have a potential divider in O β AC= ≈− =1− which RG is the lower resistor. From this, β β βA ( 1+the O ) of the op amp This means that we get effectively the same formula for β Rgain G β= circuit is set by the feedback resistor values as the non-inverting amplifier, but with R Gindependent + RF (which determine β), of the RI in place of RG (because we used difop amp’s open-loop gain – as long as βAO is ferent resistor names). ( 1−βas) A ) input 1 voltage also makes a contrimuch larger than one − (notated βAOO ≫ 1).( 1−βThe A = ≈− =1− C This is important because use of βbution to the β total voltage at the summing ( 1+ β Athe O) negative feedback means that manufacjunction. This time, we set v OUT = 0, turing variations in individual op amp which gives us a potential divider with gains have minimal impact on the cirthe resistors swapped with respect to cuit, and we can swap between different the potential divider seen by the output op amp types without changing the gain(RF is now the lower/grounded resistor). setting calculations. Thus, the contribution to the summing Negative feedback to a very high-gain junction voltage is (1 – β)vinp. amplifier has other advantages, including If wevswap theAresistors in a potential a reduction in distortion effects due to divider, A C = othe =sum ofO the output fractions v A O ) add up to one. ( 1+ βmust inp cases non-linearities, obtaining constant gain for the two over a large bandwidth, and improveIt follows that for the inverting ampli1 ments in input and output impedances. fier, v AO A C =N = 1 – β in Figs.1 & 4. Calculating A C = o (Figs.2 = β For both amplifiers & 3), the the closed-loop gain for this amplifier ( 1+ β AbyO )the using the block diagram gives us both feedback fraction isv inp determined R G approximate (for βA ≫ 1) potential divider formed by the two rethe O β=full and 1 sistors. For the non-inverting amplifier expressions for closed-loop gain as: R + R G F AC= in Fig.2, we have: β the open-loop gain and feedback factor. Subtracting the feedback signal (βvO) from the circuit input gives the amplifier input as vai = vinp – βvO. The amplifier (and circuit) output is the amplifier input multiplied by the amplifier open-loop gain, vO =Aovai . Substituting in vai from the previous equation, collecting output terms and rearranging to find the closed-loop gain, we get: AC= RG β= RG + R F −( 1−β ) A O ( 1−β ) 1 ≈− =1− β β ( 1+ β A O ) ≈ means “approximately equal to”. This leads to AC = 1(÷ β = 1)+ (RF ÷ RG), Plugging the potential divider formula − 1−β A ( 1−βfor ) β into1the approximate version and the gain formula A =for this circuit.O ≈− =1− C ( 1+ β A O ) Practical Electronics | February | 2026 β β rearranging gives the inverting amplifier gain formula, AC = -RF ÷ RI. Loop gain We can define loop gain by breaking the loop, as shown in Fig.4. This allows us to obtain two different signals, vfb and v’fb, which are really at the same point in the loop, giving a gain for the complete opened loop path as v’fb ÷ vfb. We trace the entire path of the loop in the system diagram from and back to the break, so it does not matter where the break is. For the system diagram in Fig.4, the loop contains three elements. For the non-inverting amplifier, these are gain (AO), feedback (β) and the subtraction in the mixer block (a gain of -1). The loop gain for this system is these multiplied together, giving -βAO. For the inverting amplifier, we have -AO, β and addition in the mixer block (unity gain). Again, the loop gain is -βAO. Here, the minus sign shows we are subtracting the feedback from the input (negative feedback). We have not yet considered any delay in the feedback signal. Phase shift The output of a circuit does not respond infinitely quickly to changes at its input, so any signal fed back from the output to the input will be delayed in time with respect to the original input. Phase shift represents the delay of a sinewave signal through a circuit at a given frequency. If the delay is constant, the phase shift will increase linearly with frequency, but often things are not this simple, particularly over wide frequency ranges. Consider the total phase shift around the feedback loop (in Figs.1 & 4), assuming a constant delay for simplicity. As the loop gain is negative, this is equivalent to a phase shift of 180° at sufficiently low frequencies. “Equivalent to” because negative gain (signal inversion) is not an actual phase shift as it is not due to delay. At “sufficiently low” frequencies means where the cycle time of the waveform is very long compared with the delay, so the phase shift due to any delay is close to zero at these frequencies. Pure delay causes signals to lag the input, which is a negative phase shift. The 180° equivalent phase shift of signal inversion could be taken as either positive or negative, because shifting a steadystate sinewave by +180° and -180° gives the same result. By convention, intentional signal inversion (eg, by an inverting amplifier) is regarded as a positive phase shift because this makes it more distinct from delayinduced phase lag. LTspice and other tools plot inversion as +180° on graphs, such as Bode plot frequency responses. 43 5-year collections 2019-2023 £49.95 2018-2022 £49.95 2017-2021 Fig.5: an LTspice simulation for illustrating phase shift for inversion and delay. Fig.5 shows an LTspice schematic to illustrate the ideas discussed above and help interpret the results for op amp circuits discussed shortly. This is an abstract circuit in which a signal is delayed by a fixed time using the delay function of a behavioural source. The function delay(v(n),t) delays the voltage on node n by time t. In the schematic, there are two delays of 0.1ms, both fed from the signal Source. Signal Delayed is just delayed, while signal Inv_Delayed is inverted by multiplying the delay function by -1. Fig.6 shows the phase for the signals in the circuit in Fig.5 up to 10kHz. The Source signal (green trace) has zero phase shift for all frequencies because it is directly from the voltage source (V1) used for AC analysis – it is the reference from which phase shift of other signals in measured. This plot uses a linear frequency axis, rather than the more usual logarithmic one, as this allows us to see the linear increase in phase shift with frequency produced by the ideal constant delay. The phase shift of the Delayed signal (red trace) is zero at very low frequencies and becomes increasingly negative as frequency increases. The phase shift is straightforward to calculate due to the constant delay used here. For example, at 2.5kHz, the cycle time is 1 ÷ 2500 = 0.4ms, so the 0.1ms delay imposed by source B1 is one quarter of the cycle time, or -90° (360° ÷ 4). The phase shift is negative for delay from the definition of phase shift. The Inv_Delayed signal (cyan trace) follows the same pattern of phase shift, linearly getting more negative as frequency increases – this is because it is subject to the same delay as the Delayed signal. However, the Inv_Delayed signal starts with a phase shift of +180° at very low frequencies due to the signal inversion. Simulating open-loop gain It is straightforward to simulate closedloop gain in LTspice – it is just the normal simulation of the circuit. However, both measuring and simulating open-loop frequency response is more challenging because the DC operating point of the op amp may not be calculated correctly if the op amp is connected in a £49.95 2016-2020 £44.95 Purchase and download at: www.electronpublishing.com simple open-loop configuration, such as shown in Fig.7. Wired open-loop, the op amp output may (and almost certainly will) saturate at one of the supplies, so the bias conditions are not correct for amplifier operation. In terms of simulation, the DC operating point analysis runs prior to an AC analysis may result in parameters used in the AC simulation not being correctly configured to show the true open-loop behaviour. This may not be obvious in the AC analysis results, because it is likely to run OK and produce a graph. However, the results of such an AC analysis could differ significantly from the datasheet graphs. Fig.8 shows a schematic for simulating open-loop gain with the OPA2134 op amp (U1) used in the sound card interface circuit. A closed-loop circuit is also included (U2). The trick here is in the use of separate DC and AC analysis values for the resistors. You can add ac=value to a resistor’s value as shown. The first (normal resistor) Fig.6: the simulation results for the circuit in Fig.5. Fig.7: a simple open-loop op amp circuit is likely to give poor simulation results. 44 Practical Electronics | February | 2026 Fig.8: an LTspice schematic for op amp open-loop and closed-loop simulation. Fig.9: the results from simulating Fig.8, giving the open-loop Fig.10: the results from simulating Fig.8, comparing open-loop response of the OPAx134. and closed-loop gain. value will be used in the DC operating the OPAx134 together with the closedrate-of-change of gain and phase-shift point calculation, and the specified AC loop gain of a ×10 (20dB) non-inverting change. At frequencies above a pole frevalue is used in the AC analysis that amplifier using the same op amp (U2 in quency, gain decreases at a rate of 20dB plots the frequency response. Fig.9). The open-loop gain varies sigper decade more compared to below it, In Fig.8, the U1 circuit is configured as nificantly with frequency but remains and phase shift becomes 90° more negaa non-inverting amplifier with two 1kΩ much larger than the closed-loop gain tive – assuming there are no other poles resistors, to be used in the DC operating until the frequency reaches hundreds or zeros at similar frequencies. point calculation. The specific values do of kilohertz. Above a zero, the gain decreases at not matter too much; we just use typical For low frequencies, the approximation a rate of 20dB per decade less and the circuit values. βAO ≫ 1 discussed above is valid, and phase shift becomes 90° more positive. The key thing is that the AC resistor the gain is equal to 1 ÷ β = (R4 + R5) ÷ R5 In the gain plot in Fig.9, a couple of values that set the formula circuit gain = 10 (20dB) from the potential divider breakpoints are visible. There is a pole at value (1 + (R1 ÷ R2) = 1 × 108 as shown) formula. At sufficiently high frequenabout 5Hz; the gain is flat below the pole, are much larger than the op amp’s DC cies, the approximation is not valid, and at very low frequencies, and eventually open-loop gain (about 125dB (1.8 × 106) the closed-loop gain decreases with the falls by 20dB per decade, above the first for this op amp). Therefore, the resistor open-loop gain, following the AO ÷ (1 + pole, until frequencies of several megaratio does not set the circuit gain – the βAO) formula discussed above. hertz. There is an increase in phase shift op amp cannot provide this gain, and from 0 to -90° due to this pole. what we see is the maximum op amp Poles and zeros There is another breakpoint at around gain, which is the open-loop response. We discussed poles and zeros in depth 20MHz. There are two poles here at the To achieve this, the resistor ratio should last month. These terms come from the same or similar frequencies because the be ten or a hundred times the open-loop analysis of a circuit’s frequency response gain eventually drops at 60dB per decade gain, but excessively large and small rein the Laplace domain. (40dB more than in the mid-range) and sistor values or excessive ratios may not Although this is based on advanced the phase shift increases by -180° (2 × work due to numerical limitations in the mathematics, we can use the concept of -90° for two poles) to -270° (3 × -90° for simulator calculations. poles and zeros in a practical sense to three poles total in Fig.9). The results from Fig.8 are shown in describe frequency responses and help Fig.9. This plot uses slightly extended decide how they might need to be maSimulating loop gain axes compared to the open-loop renipulated to achieve our circuit design To plot the loop gain of an op amp in sponse graph in the OPAx134 data sheet aims. a simulation, we need to somehow break but shows a good match to the shape of As explained last month, poles and into the loop to inject a signal. This can the curves. zeros produce breakpoints in a cirbe done with a voltage source having a Fig.10 shows the open-loop gain of cuit’s frequency response where the DC voltage of 0, as shown in Fig.11. The Practical Electronics | February | 2026 45 Fig.11: an LTspice schematic for op amp loop gain simulation. two sides of the voltage source will be at the same DC voltage, so are effectively shorted together at DC. Inserting the voltage source provides separate nodes in the simulation model that relate to vfb and vai in Figs.1 & 4, and are labelled correspondingly in Fig.11. We can therefore plot vfb ÷ vai in an AC analysis to show the loop gain of the amplifier. With the presence of feedback resistors (this is a version of a normal amplifier circuit, not open-loop as discussed above), the op amp will be biased normally. The circuit in Fig.11 is not specifically either an inverting or non-inverting amplifier. It could be either, because the feedback loop is the same in both cases. In this simulation, we are just looking at the loop gain, so the normal input signal (which would either be to the inverting input or to resistors R2 and R4) is zero. The two op amps in Fig.11 are the UniversalOpAmp1 and UniversalOpAmp3 idealised behavioural models provided by LTspice. The feedback resistors R1 and R3 are set to zero, and the grounded resistors to a very large value (1GΩ). This feeds back the whole output signal (β = 1), so the loop gain (βAO) of this circuit will be equal to the open-loop gain, at least with a relatively ideal circuit. Using resistors like this easily allows us to change the circuit gain without having to redraw it. Fig.12 shows the results of the AC analysis from Fig.11 and highlights the difference between the UniversalOpAmp1 (U1, green trace) and UniversalOpAmp3 (U2, red trace) models, specifically that UniversalOpAmp1 has one pole and UniversalOpAmp3 has two poles. The single-pole model provides a simple idealised op amp, whereas the two-pole version is closer to real devices (note the similar high-frequency poles in Fig.9), but may not cover their full complexity. The specific gain and pole frequencies are set by right-clicking the op amp and adjusting the model parameters. We will look at the details of this later. The op amps were configured to give similar response to the OPAx134, within the limits of the models. The plot in Fig.12 shows that phase shift is +180° at low frequencies, which fits with the preceding discussion on inversion and phase shift. Fig.13 shows the results of a transient simulation using a 1μV, 2kHz signal from the V1 voltage source in the loop. This feeds a signal directly into the op amp. From Fig.12, we expect the loop gain to be about +72dB (4000 times). Fig.12: the results from simulating Fig.11, showing the loop gain of LTspice’s UniversalOpAmps. 46 We expect the phase shift to be -90° because Fig.12 shows +90° at 2kHz, which comprises the +180° equivalent shift from the inversion and -90° phase shift from the op amp’s first pole. Fig.13 shows the feedback signal (vfb1, red trace) multiplied by -1 to remove the inversion so that we can more easily see the phase shift due to delay round the loop. The input signal (vai1, green trace) is multiplied by 4000 to scale it to the same level as the feedback to facilitate comparison and confirm the loop gain value. The cursors show a time difference of 125μs, which is a quarter of the cycle time of 1 ÷ 2000 = 500μs, representing a 90° phase shift. The feedback signal is lagging (delayed), so the phase shift is -90°. Fig.14 shows two more versions of the circuits from Fig.11, both using Universal­ OpAmp3 (U3 and U4). In both cases, β=0.1; this is set by the potential divider formed by the resistors, for example R6 ÷ (R5 + R6) = 1kΩ ÷ (1kΩ + 9kΩ) = 0.1. The circuits would have a gain of 10 if used as an inverting amplifier, or -9 in the inverting configuration. Fig.15 shows the results from the circuit using U3 (cyan trace) compared with the response of U2 from Fig.11 (red trace). The only difference is the β value (1 for the U2 circuit and 0.1 for the U3 circuit). Fig.13: the results from simulating Fig.11,showing phase shift in the feedback loop. Practical Electronics | February | 2026 Fig.14: more loop simulation examples, part of same schematic as Fig.11. The loop gain for the U3 circuit is 10 times smaller than for U2 circuit, so its gain curve is exactly 20dB [20log10(0.1) = -20] below the curve for the U2 circuit. Both circuits have the same phase response. Fig.16 shows the results from the U4 circuit in Fig.14 (yellow trace). This has an extra capacitor compared to the circuit for U3 (also plotted, cyan trace). The capacitor is frequency-dependent, so it changes the shape of the frequency response, rather than just shifting on the dB axis as different resistor values do. It also changes the phase response significantly, adding -90° compared with the op amp alone. Adding this capacitor introduces an additional pole in the feedback loop. The value of the capacitor was chosen to place this pole in the middle of the graph, so it was clear to see. Instability Consider the total phase shift around the feedback loop (in Figs.1 & 4). We have +180° equivalent phase shift at DC due to the signal inversion, which is required to achieve negative feedback. As we increase the signal frequency, the total phase shift will tend to become more negative in a similar way to what we have seen in loop simulation examples above. However, for real op amps, the shape of the curves may be more complex. Once the phase shift due to the loop delay reaches -180°, the total effective phase shift around the loop is 0°. At this point, the -180° delay phase-shift cancels the +180° effective phase-shift from the inversion. We effectively multiply the loop gain by -1, giving +βAO. What was negative feedback has become positive feedback. Positive and negative feedback produce profoundly different behaviours in circuits, so it is possible that the presence of positive feedback at high frequencies will have a significant impact. Positive feedback at DC causes bistable operation, as observed in circuits such as Schmitt triggers and latches, where the output tends to saturate at one of two values, often at or close to the supply rails. Such circuits are unstable with intermediate DC voltages, but stable at voltages close to the supply rails. An op amp linear amplifier will typically not have strong (or any) positive feedback at DC and low frequencies, so it will probably not exhibit unstable behaviour related to DC (eg, the output stuck at a supply voltage). Instead, positive feedback of AC signals will add to the signal level of any existing signal at that frequency. Fig.15: the results from simulating Figs.11 & 14, giving loop responses (βAO) for β = 1 (U2, red) and β = 0.1 (U3, cyan). Practical Electronics | February | 2026 If the gain around the loop is sufficient, this could potentially cause the signal amplitude at that frequency to continuously increase until it is limited by circuit nonlinearities (the op amp’s maximum output level is reached). The result is oscillation at a frequency where the positive feedback is strong. The positive feedback reinforces the signal and so sustains the oscillation even if the input at the relevant frequency is removed. Typically, there will be some initiating signal at the relevant frequency that is amplified and built up by the feedback to sustain the oscillation. This can be due to noise in the circuit or disturbances; for example, from the power supply. Looking at the denominator of the closed-loop gain equations above (1 + βAO) gives further insight into this. If the denominator is zero, the gain will be infinite in an idealised circuit. The gain is infinite for βAO = -1; remembering that the loop gain (βAO) has both phase and magnitude, the conditions for this are that the magnitude of βAO is unity (|βAO| = 1) and the total effective phase shift (including the +180° inversion) is zero or an integer multiple of 360°. That is positive feedback with enough gain for it to be possible to sustain oscillation. Fig.16: results from Fig 14: loop responses (βAO) without (U3, cyan) and with (U4, yellow) a capacitor across the grounded resistor. 47 Gain (dB) Loop gain (dB) 0 –90 –180 180° Total loop phase shift Loop delay phase shift 0 Dominant pole Ao Gain margin Log frequency Open-loop response Ac Closed loop response 0 High-frequency pole f0 Phase margin 0° Fig.17: how phase margin and gain margin relate to the open-loop response of an op amp. Compensation Lower closed-loop gain corresponds with higher β (β closer to or equal to one) and hence higher loop gain. The higher loop gain means a low-gain op amp circuit is more likely to be unstable because it is easier to meet the criteria for oscillation. This may seem counterintuitive if we think of something with high gain as being ‘unstable’ because it is very sensitive to its input signals etc. Adding poles and zeros to a circuit’s feedback loop will change the response (see the two responses in Fig.16) and hence the stability of the circuit. For example, adding a pole may make a circuit more unstable because it causes the phase shift to increase; however, it also may make the circuit more stable because the gain is reduced at high frequencies. The actual situation will depend on the 48 Unity gain bandwidth Log frequency Fig.18: the relationship between open-loop and closed-loop frequency responses. 90° These two conditions for oscillation are referred to as Barkhausen’s criteria, which is commonly used in discussions of amplifier stability, however, general conditions for stability, or conversely, sustained oscillation are more complex, and Barkhausen’s criteria are not sufficient to guarantee oscillation. In unstable amplifiers, a small (eg, noise) signal will initiate an oscillation with increasing amplitude due to high loop gain. If sustained oscillations occur, nonlinearities will reduce the gain to settle at Barkhausen’s criterion, |βAO| = 1. If these (or other) conditions for sustained oscillation are not met, a circuit may produce decaying oscillations (severe ringing) after a trigger event, such as an input transient. Such circuits may not be strictly ‘unstable’ in the sense of oscillating continuously, but they will often be described as such if the amount of ringing is unacceptable. Closed loop bandwidth relationship of all the poles and zeros in the frequency response. A key example of adding a pole is found in the open-loop response of op amps – for example, in Fig.9 we see a low-frequency pole in the op amp’s frequency response. This is deliberately part of the design of most op amps, with the pole being typically in the low hertz range. It is chosen so that the op amp’s high-frequency gain is sufficiently low for it to be stable with 100% feedback (unity gain configuration). Modifying an amplifier’s open-loop response to ensure stability with feedback applied is called compensation. Adding a low-frequency pole to achieve this is called dominant-pole compensation, because the pole dominates the overall shape of the response. Most, but not all, op amps use this approach. Phase margin and gain margin Due to variations in individual components, component ageing and temperature variation, it is not a good idea to design an amplifier that is stable but close to being unstable. If so, some individual builds of the circuit, and others over time, or as environmental conditions change, will start to oscillate and fail as amplifiers. We can measure how close a circuit is to being unstable using the concepts of gain margin and phase margin. Figs.12, 15 & 16 show loop frequency responses for op amps. As frequency increases, the gain decreases and the phase shift becomes more negative, reducing the total phase shift from +180° at low frequencies towards zero as the phase shift due to delay moves from nearly zero towards -180°. For the amplifier to be stable, as the loop gain magnitude approaches unity (0dB), the negative phase shift (lag) in the loop due to delay must be less than -180°, so the total including inversion is greater than zero. The difference between the delay phase shift at this point and -180° is the phase margin. Similarly, as the phase shift due to delay around the loop approaches -180°, the magnitude of the gain must be < 1 to prevent oscillation. The difference between the loop gains when its phase shift reaches this point and unity gain is the gain margin (usually expressed in dB). Fig.17 illustrates these definitions. It is common to regard 45° as the minimum acceptable phase margin. This is to allow sufficient headroom for component and environmental variations, but it is a rule of thumb and not universally used. Usually, the acceptable range is between 30° and 60°, but it depends on who you ask and the trade-offs they are considering. A lower phase margin will tend to mean the circuit produces more ringing, while higher values tend to produce slower responses to fast-changing inputs. Gain-bandwidth product Fig.18 shows the frequency response of a typical dominant pole compensated op amp for both open-loop and closed-loop conditions (this is a generalised version of Fig.10). The op amp has full open-loop gain (AO) at DC, but the gain starts dropping at the low-frequency dominant pole (f0), typically from 1-10 Hz. Above f0, the gain falls off at 20dB/ decade. As AO is very large, it does not drop to unity (0dB) until a high frequency (the unity gain frequency, often many megahertz or more). The closed-loop gain (AC) remains flat until it approaches the open-loop gain, as discussed above. If we multiply closed-loop gain by closedloop bandwidth, we get the gain-bandwidth product (GBP). A feature of dominant-pole compensated frequency responses is that the GBP is constant. The gain drops by 20dB per decade at frequencies above f0. A drop of 20dB is a factor of 10 decrease in gain, but this is for a factor of 10 increase in frequency. Thus, the product of gain and frequency is constant. The shape of the open-loop curve up to any high-frequency poles is set by Practical Electronics | February | 2026 Simulation files Most Circuit Surgery columns feature the use of the free circuit simulation software LTSpice. It is used to support descriptions and analysis in Circuit Surgery. The examples and files for this issue are available for download: https://pemag.au/link/ac9b Fig.19: an LTspice schematic for FRA analysis of an op amp based amplifier circuit. etc). This is done specifically to allow higher-gain closed-loop gain circuits to have higher bandwidth (the open-loop gain AO can be higher at higher frequencies with smaller β values because the loop gain βAO is still sufficiently small there to achieve a good gain margin). This is a potential pitfall for those who do not read datasheets carefully enough to notice the minimum closed-loop gain specification. LTspice FRA example Fig.20: the results of the FRA analysis in Fig.19. AO and GBP. These values can be set by the user for LTspice’s UniversalOpAmp devices. For example, for the circuits in Figs.11 & 14, I used AO= 1.778 × 106 (125dB) and GBP = 8MHz to provide a reasonable match to the OPA2134 used in the soundcard interface. UniversalOpAmps numbered 3 and above also have a high-frequency pole, which can be set via their phase margin parameter. Some commercial op amps are not designed to be stable in low closed-loop gain configurations (eg, for gains below 2 or 5 You can measure gain margin and phase margin from loop simulations such as in Figs.11 & 14, but LTspice also has an automated method to do this called a Transient Frequency Response analysis (.fra command), which uses a steppedfrequency sinewave. This has the advantage that is uses the full op amp model, not the linearised version employed in AC analysis. A special FRA element (a component with a name starting with <at>) is inserted into the loop instead of a voltage source, as shown in Fig.19. There are several settings required, which are made by right-clicking the FRA element. The setting for the FRA in Fig.19 were: 10 points per decade, coarse steps to 100Hz, amplitude 0.5V up to 50kHz, reducing to 0.1V by 500kHz, analysis start at 100μs, minimum time 100μs, settling time 200μs. The results are shown in Fig.20 and include generated text stating the unity gain frequency (808.679kHz) and phase PE margin (85.3867°). 1591 ABS flame-retardant enclosures Learn more: hammondmfg.com/1591 uksales<at>hammfg.com • 01256 812812 Practical Electronics | February | 2026 49