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Power Electronics series By Andrew Levido Power Electronics Part 1: DC-DC Converters Power electronics is a very broad term that describes circuits with the primary function of handling electrical energy. In this series of articles, we will explore this area, with practical examples. I will share some useful tools and techniques. P ower electronics is all around us – the rapid growth of renewable energy, electric vehicles and the nearubiquity of switching power supplies means that a huge percentage of our electrical energy is generated, transmitted or consumed by power electronics. Fundamentally, power electronics systems convert electrical energy from one form (a source) to another (a load). Consider a smartphone; there is power electronics in the charger, converting the mains to an isolated low voltage. There is more in the battery charging circuit within the phone, and yet more to provide the many low-voltage power rails necessary for its operation from the battery. That battery is most likely a single LiPo cell, a type of lithium-ion cell, which will vary from around 4.2V when fully charged to around 3.3V when discharged. So the internal power supply electronics needs to be designed to convert that varying voltage to several fixed, regulated voltages for consistent performance of the various subsystems in the phone (processor, display, RF etc). At the other end of the spectrum, there are the kilowatt and megawatt-­ scale power electronics systems controlling industrial processes including variable-speed motor drives, robotics and a whole range of other applications. Electric and hybrid vehicles also rely on power electronics for their battery charging and management systems, and of course, in the drivetrain. This series will take a simlar approach to Ian Bell’s Circuit Surgery column, with formulae and fairly detailed analysis. However, we aim to make this comprehensible to just about anyone interested in the subject, so we will try to avoid any mathematics beyond what is (or at least should be) taught in high school. We will also make sure to provide examples and down-to-earth explanations. We want to make this discussion accessible, despite the complexity of the topic! Breadth and depth What makes power electronics especially interesting (and maybe a little bit daunting) is the enormous breadth and depth of the field. You can get an idea of its breadth by looking at Fig.1. This shows the scope of a typical power electronics system. It consists of the following subsystems: • Power switching: this is the heart of any power electronics system. Power is switched by semiconductor switches such as Mosfets, IGBTs, diodes, thyristors and the like. • Input and output filters: filters form an integral part of most power electronics systems, as we shall see. They can also help ameliorate some of the negative consequences of Fig.1: power electronics is a broad field, encompassing a knowledge of the load and the control loop as well as switching, drivers and filters. 24 switching like electromagnetic interference (EMI) and poor power factor. • Switch drivers: this might not seem very interesting, but power electronics switches can have demanding drive requirements. The control terminals of the switches are often floating at high voltages, or switching rapidly between different voltages. The driver circuits therefore often have to include bootstrap power supplies, level shifting and high-voltage isolation. • Control loops: most power electronics circuits require some form of closed-loop control. This can be a simple voltage regulator in a DC-toDC converter, or may involve multiple electrical or electromechanical sensors spread across a complex industrial machine. • Loads: the power electronics designer has to have a good understanding of the load, its characteristics in operation and any feedback transducers that may be involved. As well as covering this breadth, power electronics requires an ability to look at the system through different lenses at different times; from a wide-angle perspective, right down to a detailed microscope-level viewpoint. For example, take capacitors. In this article, we will introduce a highlevel analysis technique that assumes the average current through a capacitor is always zero. Later, we will have to zoom right in and look at the nonideal behaviour of the same capacitor, including its equivalent series resistance (ESR) and the effects of voltage and frequency on its dielectric. In the following article next month, we will consider capacitors from a complex impedance perspective. It is really important to use the right analysis lens at the right time. If you go too detailed too soon, you can become hopelessly mired in unnecessary Practical Electronics | April | 2026 Part 1: DC-DC Converters complexity. Conversely, if you stay at too high a level for too long, you may over-simplify things and miss something important. I think this constant zooming in and out is one of the reasons why some people find power electronics difficult to grasp. I am going to try to be very explicit about which lens we are using and when, to help dispel some of the complexity. To that end, we are going to zoom right out and start our analysis of DC-DC converter topologies with an annoyingly simple example. Fig.2: the simplest possible DC-DC switching converter. This is not very practical, but does reduce the average voltage efficiently. It’s basically just pulse-width modulation (PWM). A simple start Let’s start by assuming I want to build a switching DC-to-DC converter to reduce a source voltage, Vsrc, by 50% to power some load (Vload = ½Vsrc). The simplest possible approach is shown in Fig.2. If we operate switch S1 with a 50% on/off duty cycle (ie, on and off for equal periods), I think you would agree that the average voltage in the load (green dotted line) will be half that of the source voltage. The efficiency of the circuit will be 100%, since there are no lossy elements (much better than a linear regulator, which would be 50% efficient), so that is a win. Of course, I am ignoring the obvious fact that the output voltage (green solid curve) will be far from a smooth DC voltage. Before we move on to address this shortcoming, I want to take a minute to establish some conventions around the variables I will be using throughout this series. • I will use lower-case variables to represent time-varying or AC quantities; for example, v2 or q. • I will use upper-case variables for fixed or DC quantities, like Rload or Vsrc. • I will use angle brackets to indicate an average value, like ‹v2›. Obviously, it only makes sense to average time-varying values. I am using q(t) to describe a time-­ dependent control function that dictates the state of the switch. In the example of Fig.2, the control function (red trace) is a digital signal with a value of either 0 or 1. The label adjacent to S1 indicates that it is closed when q(t) = 1, and, by implication, is open when q(t) = 0. The period of the control function is T, and it is on for a time DT, where D is the duty cycle, which can have any Practical Electronics | April | 2026 Fig.3: adding filters to the input and output of a simple switch produces a buck converter. The use of average value analysis allows us to work out the transfer function very easily. value between zero and one. The cycle period T is the inverse of the switching frequency, f sw. The next step is to add a filter to the circuit of Fig.2 to smooth the output. In Fig.3, we have added an LC lowpass filter (L1/C2) to the output, and a capacitor, C1, to the input. The input capacitor is unnecessary if the voltage source is perfect, but I have put it in because it is almost always required in real life, and it will come in handy later. We will assume for now that the inductor and capacitor values are very large compared to the switching frequency so that the filtering is almost perfect. In this case, any capacitor voltage ripple or inductor current ripple are negligible. The switch has now been expanded to two complimentary switches: S1, which is closed when q(t) = 1 as before, and S2, which is closed when q(t) = 0. The latter is necessary to provide a path for the inductor current (which can’t change instantaneously) when S1 is opened. Average value analysis We are going to use a tool known as average value analysis to understand the transfer function (the relationship between the output and the input quantities) of this circuit. This kind of analysis is very useful for understanding the operation of a circuit at the highest level. We don’t need to know any component values, or even the switching frequency, to complete this analysis. Average value analysis requires our circuit to be in a condition known as ‘periodic steady state’ (PSS), which just means that the circuit is in a steady (unchanging) state at the macroscopic level. PSS therefore ignores transients like those that occur at start-up or where the load suddenly changes. In this state, each switching period looks exactly the same, even though voltages and currents change during the cycle. If each period is identical, it follows that all voltage and current waveforms must start and end each period at the same value. Something interesting happens to capacitors and inductors in PSS. Since the voltage across a capacitor starts and finishes each period at the same level, the average voltage across it must be constant. This implies that the average current through the capacitor must be zero. A similar thing happens for inductors. In PSS, the average current through an inductor must be fixed. This means the average voltage across it must be zero. We can therefore write 25 Power Electronics series two equations that help us with average value analysis: ‹ic› = 0 and ‹vl› = 0. Be careful with this – it applies only to the average voltage and current during PSS. Now we can perform an average value analysis on the circuit of Fig.3. If the average voltage across the inductor is zero, it should be apparent that ‹vx› = ‹v2›. We can also calculate ‹vx› from the green chart in Fig.3 and see that ‹vx› = DVsrc. We can further see that, due to the perfect LC filter, ‹v2› is equal to Vload. Putting these together, we find the circuit transfer function is Vload = DVsrc. Since D must be between zero and one, Vload must be equal to or lower than the input voltage. This circuit is a classic buck converter (‘buck’ meaning step-down in this context). Setting D to 0.5 gives us an output voltage of half the input voltage, as we wanted. This time, the output voltage is DC, ie, smooth. If the average capacitor currents and inductor voltages are zero in PSS, there can be no average energy change, and therefore no power dissipation in the inductor or capacitors. This means that the converter input power and the output power must be equal (Isrc • Vsrc = Iload • Vload). Substituting the voltage transfer function derived above gives the current transfer function Iload = Isrc ÷ D. Let’s just pause for a second here and recap what we have done. Using nothing but the average value analysis rules (in PSS, ‹ic› = 0 and ‹vl› = 0), and a diagram of vx, we have derived the voltage and current transfer functions for the classic buck converter. No fancy maths is required. We have not had to worry about component values or the switching frequency – just the assumption that the LC filter time constant is much larger than the switching period T. Average value analysis is a powerful tool for understanding the basic function of switching converters. While we are on a roll, let’s look at what happens if we swap the source and load in our circuit. This is worthwhile to illustrate just how important the filters are in determining the operation of a power electronic converter. A ‘reverse’ buck converter Fig.4 shows our new converter. It is exactly the same as the buck converter, 26 but I swapped the source and load. I have also switched the designations of the capacitors, voltages and currents so the subscript 1 is still associated with the source and subscript 2 with the load. I have also swapped the control sense of the two switches. S1 is now on when q(t) = 0, while S2 is on when q(t) = 1. This aligns with the conventional way this type of converter is described, but does not change its operation. Again, using average value analysis, we can see that if the average inductor voltage is zero, ‹vx› must equal ‹v1›, which is in turn equal to Vsrc. We can see from the graph of vx (green curve) that its average ‹vx› = (1 – D)Vload, so the transfer function of the converter must be Vload = Vsrc ÷ (1 – D). We can use conservation of power as above to find that Iload = Isrc(1 – D). Since D ranges between zero and one, the load voltage varies between Vsrc when D = 0 and approaches infinity as D approaches 1, so the output must be equal to or higher than the input. Therefore, this is a classic boost converter. Additional topologies We usually draw the boost converter with the source on the left, but I have done things this way to bring out the fact that the filter and switch arrangement is the same for both converters. Fig.5 summarises what we have just covered and adds several more topologies. I have used Mosfets and diodes in place of the switches to show how these circuits are usually implemented. If you think about it, a diode can be considered a sort of passive switch, as it goes into and out of conduction depending on the voltage across it. While diodes are typically less efficient than Mosfets (due to their minimum forward voltage), they have the benefit of requiring no active control circuitry. The first new converter is the buckboost which, as its name suggests, should be able to produce a voltage above and below the input. This time, it should be obvious the average value of vx must be zero, because the average value analysis rules dictate that the average inductor voltage must be zero. However, we can see that when Q1 is on, vx must equal Vsrc, and when it is off and the diode is conducting, vx must equal Vload. Vload must thus be negative to make the average of ‹vx› zero, as required by the average value analysis rules. You can probably see from the plot of vx that for the average to be zero, the area DVsrc when Q is on must equal the area −(1 – D)Vload, which is shown in the second equation. Rearranging gives the voltage transfer function shown in blue. As we expected, the output voltage is in the range of zero (when D = 0) and negative infinity (D = 1). Of course, there will be a practical upper limit on the output voltage of these converters (usually on the order of a few times the input voltage), but for the purposes of this high-level analysis, it can be infinite. The next converter we will look at is the Ćuk converter (pronounced “chook”). This was first presented by the American academic Slobodan Ćuk in 1976 (he was born in Belgrade, Yugoslavia, which is now part of Serbia). It is a departure from the previous converters, which use the inductor as the primary energy storage element. The Ćuk converter uses a capacitor (C3 in Fig.5) as the main energy storage device, with the now-familiar LC filters on the input and output. Fortunately, we can use average value analysis to work out the transfer function in just the same way as we have before. The upper waveform is the voltage at vx and the lower waveform is the voltage vy. When the Mosfet is on, vx is zero and the left-hand end of C3 is Fig.4: the classic boost converter is just the buck converter from Fig.3 with the source and load switched. Practical Electronics | April | 2026 Part 1: DC-DC Converters grounded. This means that vy must be equal to −‹vc›. When the Mosfet is off, vy must be zero, so the right-hand end of C3 is grounded, meaning vx must be equal to +‹vc›. This leads to the first two equations that describe the average values of vx and vy, respectively. The input and output filters mean that ‹vx› is equal to Vsrc, and ‹vy› is equal to Vload, as shown in the next line of equations. Finally, we can combine these to produce a transfer function that is identical to that of the buckboost converter, complete with voltage inversion. Why would one use a Ćuk converter when it has the same transfer function as the simpler buck-boost converter? Firstly, the Mosfet is ground-­referenced, making the drive circuit simpler. Secondly, it is possible to wind the two Ćuk inductors on the one core in such a way that the output ripple is dramatically reduced. Finally, having LC filters on both input and output, the Ćuk converter can have lower EMI than other converter topologies. The final type of converter I want to cover is the ‘single ended primary inductor converter’, generally abbreviated to SEPIC. This one also uses a capacitor as the energy transfer element. We’ll analyse this in the same way as all the others. When the Mosfet is on, vx is zero and when it is off, vx is the average capacitor voltage ‹vc› plus the output voltage Vload, as shown in the waveform. The average value of vx is given by the first equation. In this converter, ‹vy› must be zero due to inductor L2; therefore, ‹vx› must equal ‹vc›. We also know that, due to the input filter, Vsrc = ‹vx›, so we can re-write the first equation in terms of Vsrc, as shown in the third equation. Finally, we can rearrange this to get the voltage transfer function, which turns out to be similar to the buckboost and Ćuk converters, except not inverted. The SEPIC converter can therefore produce a positive voltage between zero and (in theory) infinity. As you might imagine, there are many other variations on this theme, and their characteristics are not always obvious from just looking at the circuit. I hope that you have seen that average value analysis is a simple way to get to grips with switching converters. Getting practical Enough theory for now. I want to build the buck converter we have been discussing, to see what’s involved and how closely reality matches the theory. I am also going to simulate it using a free circuit simulator called QSpice. To complete this design, we will have to zoom down into some of the detail, especially when it comes to capacitors. Fig.5: five common DC-DC converter topologies. Average value analysis allows us to understand their steady-state behaviour – and that of any converter you come across. Practical Electronics | April | 2026 27 Power Electronics series We will start with some specifications. The input voltage is nominally 12V, but let’s allow for a range of 10V to 14V. We want an output voltage of 6.0V and a maximum output current of 600mA, so a 10W load. We can use the transfer function derived above to calculate the required duty cycle range: 0.43 ≤ D ≤ 0.6. I will use a TPS5410 DC-DC converter chip in this example. This is a pretty old chip, and not necessarily one I would recommend for new designs, but it has a couple of advantages for us. It has a fixed switching frequency of 500kHz and uses an external flyback diode. These make it a good match to the theoretical circuit, and allow us to measure the inductor current ripple fairly easily. The circuit is shown in Fig.6. I have shown the connection of the internal Mosfet so you can see how it matches up with S1 in Fig.3. We will more-orless follow the design procedure set out in the chip’s data sheet, but I will take a bit of time to explain the formulas it provides so you can see how they are arrived at. The capacitor Cboot is used by a bootstrap circuit within REG1 to create a drive voltage for the internal Mosfet that is a few volts higher than Vsrc. We will just use the manufacturer’s recommended value of 10nF here. The output voltage feedback comes via the voltage divider R1/R2. The Vsens voltage on pin 4 should be 1.22V when the output voltage is at the desired level (6V in our case). If we let R2 = 10kW we can calculate that we need a value of 39.2kW for R2. This is very close to the standard value of 39kW, so we will use that. I will use an MBRA130LT3 schottky diode for S2 (D1) since I have one on hand. This is a 1A, 30V fast diode, so should be fine for this application, since the peak current should be just a little over the load current of 600mA. That’s it for the easy parts. Input capacitor selection The design process in the data sheet suggests that we start by selecting C1 to give the desired worst-case voltage ripple at the input. Fig.7 shows the data sheet equation (at the bottom) and the circuit fragment that will help us understand it. The capacitor is shown together with its equivalent series resistance (ESR), since this will be significant in calculating the ripple. The capacitor ripple voltage ∆v c is given by the top equation – the first part is the basic equation for the change in capacitor voltage as the current i c is extracted, and the second part is the voltage across Resr from Ohm’s law. Fig.7 shows us that when S1 is closed, the capacitor discharge current ic will be the net of the load current Iload, less the charging current, Isrc. The worst-case current occurs when D = 0.5 and Isrc = ½Iload. The capacitor current for the worst-case ripple must therefore be ½Iload. The worst-case ripple voltage is therefore given by the second equation, which substitutes ½Iload for ic and 0.5T for ∆t. This is almost identical to the data sheet formula. I have highlighted each term in a different colour so you can see how they are related. The mysterious ¼ term in the data sheet formula is simply the ½I load factor and 0.5 worst-case duty cycle combined. f sw is the switching period T shifted from the numerator to the denominator. The only real difference between the two equations is the missing ½Iload factor in the ESR term. This will just make the ripple estimate a little bit higher, which is of little consequence. Now we have to choose a capacitor with the appropriate value and ESR. This is not simple exercise when dealing with high-frequency circuits such as this. I want to use a multi-layer ceramic capacitor (MLCC) for its low ESR, in parallel with an aluminium electrolytic for bulk storage. For the MLCC, I chose a 4.7µF 25V X7R model (Samsung CL21B475KAFNNNE), while for the electrolytic, I will use a 100µF 35V unit (Panasonic EEE-FP1V101AP), both of which I have in my parts bins. It’s complicated! Now it is time to get out the microscope, because in high-frequency power electronics circuits (and indeed in many circuits), you can’t necessarily take capacitors at face value. The chart at the top left of Fig.8 shows that, although our 4.7µF MLCC capacitor is rated for 25V, its nominal capacitance will fall by 70% (to 1.4µF) when biased with 12V. This is a ‘feature’ of many MLCC dielectrics like X7R and X5R that you should be aware of. The capacitance also goes down with temperature and ageing, but not significantly in this application. This is a good reason to choose MLCCs with a higher voltage rating than might seem necessary at first (or, in applications requiring lower capacitance, selecting a more stable dielectric like C0G/NP0). The lower graph shows that, at 500kHz, the capacitor’s ESR is about 4.5mW, which is very low, and one of the main reasons you see these capacitors in switch-mode circuits. Fortunately, the capacitance of the electrolytic is relatively fixed with applied voltage and, according to its data sheet, it has an ESR of around 80mW at 100kHz. There is no data for higher frequencies, so we will assume this ESR holds at 500kHz. Figs.6 & 7: we built this example of a buck converter (see left diagram) as a practical exercise to see if the actual results matched the theory. The worst case input voltage ripple occurs when the duty cycle is 50% (see right diagram). The lower-most equation is copied from the data sheet, while those above it show how it was derived. 28 Practical Electronics | April | 2026 Part 1: DC-DC Converters Fig.8: the plots on the left show that the capacitance and ESR of an MLCC can be very different from the nominal values under DC bias and at high frequency. The circuit and formulae above shows how we combine parallel impedances; for example, when paralleling capacitors with significant ESR. Editor’s note – be careful with such assumptions because wet electrolytic capacitors have physical limitations in response time. Our two capacitors will be in parallel, but the diagram on the right of Fig.8 shows us why we can’t assume the total capacitance will be the sum of the two capacitances, or that the total ESR will be the parallel combination of the two resistances. Instead, we have to calculate the complex impedance of each capacitor/ESR combination (left equation), then calculate their parallel impedance (right equation) and decompose that to obtain the equivalent capacitor and resistance value. I use a spreadsheet to do these (literally) complex calculations, and the results can be surprising and sometimes counter-intuitive. For example, my spreadsheet shows that the parallel combination we will be using will have an equivalent capacitance of 11.8µF and an ESR of 69mW at 500kHz. Plugging these values into the input ripple formula suggests we can expect a peak-peak ripple voltage of about 46mV (67mV if you use the data sheet Practical Electronics | April | 2026 calculation, with its extra current in the ESR term). Inductor selection The next item we need to select is the inductor. The lower blue formula in Fig.9 is from the data sheet, and the circuit fragment shows us the simplified circuit when S2 is closed. It should be apparent that the voltage across the inductor is equal to the output voltage, Vload. During this period, the inductor current will ramp down by some amount, ∆il, that represents the peakto-peak current ripple. The first formula in the figure describes the general relationship between the rate-of-change of current in inductor and the voltage across it, arranged to make the inductance the subject. The second equation therefore shows the minimum inductance required to limit the current ripple to some value ∆il. In this equation, vl has been replaced by Vload and ∆t by (1 – D)T. The data sheet formula is almost identical to this; the expression (Vin(max) – Vout) ÷ Vin(max) evaluates to 1 – D, and T moves to the denominator as f sw. The current ripple is expressed as a factor (Kind) of the load current. The random-­looking 0.8 is there as a safety factor, to allow for inductor tolerance in the case you use an inductor with a value of exactly Lmin. If we choose to have maximum ripple current of 100mA, we can calculate that we need an inductor with a value greater than 85µH. The nearest larger practical value is 100µH, so that is what we will use. If we back-­calculate the ripple using this value, we get an expected peak-to-peak ripple current of 68mA. The peak inductor (and diode) current will be the average load current plus half of the ripple current, or 634mA. I chose a VLS6045EX101M inductor from TDK. This has a peak current rating of 1.1A and a DC resistance of 470mW (we want to keep that resistance low for good efficiency, as all the current flows through it). Output capacitor selection The capacitance of the output capacitor is not all that critical as far as output ripple is concerned – the output cap’s ESR is usually the important parameter. In theory, you could keep adding output capacitance to make the ripple as low as you want, but this would cause problems with the performance of the voltage regulating control loop. We will cover (some) control theory in the next article, but for now it is enough to know that the internal compensation in this particular controller requires the closed-loop crossover frequency to be in the range 3kHz < fc < 30kHz. Fig.9: the data sheet equation for peak to peak current ripple at the bottom of the figure is derived from the basic relationship between current and voltage in an inductor. 29 Power Electronics series Fig.10: simulation of the circuit (left) yields results (above) that are very consistent with the calculated values. The closed-loop crossover frequency must also be lower than the frequency of the ‘pole’ formed by the output capacitor and its ESR. The closed-loop crossover frequency is the frequency at which the closed-loop gain falls to zero. The manufacturer helpfully provides an expression that relates fc to the output filter corner frequency, f lc. Given we know the inductance, we can determine that C2 must be between 165.6µF and 31.4µF (at the loop crossover frequency, not necessarily at 500kHz). We can therefore use the same 4.7µF/100µF pair as we did for the input, since with 6V DC bias and the 4.5kHz crossover frequency the, parallel capacitance is about 102.5µF and the ESR is 76mW. This will have an ESR pole at 22kHz, much higher than the crossover frequency, so we should have a stable control loop. Notice that we have used the loop frequency to calculate the capacitance and ESR for loop stability, and that we will use the switching frequency to calculate them for ripple below. This is a great example of why power electronics can seem confusing – the same capacitor has different apparent values depending on the type of analysis we are performing. 30 The output ripple is then more-orless trivial to calculate, as it is just the output cap’s ESR multiplied by the peak-to-peak ripple current. At 500kHz with 6V bias, the tables and the spreadsheet tell us that total capacitance will be 9µF and the ESR 56mW. With a current ripple of 68mA, we should see about 3.8mV of peak-to-peak voltage ripple at the output. That much ripple is not likely to be a problem for whatever it is driving. With additional filtering, it could be reduced well below 1mV. Simulation Simulation is a powerful tool we can use to analyse the behaviour of power electronics circuits. There are a few very capable free simulators available. I have been using QSpice recently, as its user interface (UI) seems to be better than some of its competitors. Like everything in power electronics, the trick to good simulation is to work out what is important and what can be simplified or ignored. Fig.10 shows where I landed. A subcircuit (not shown) produces a control signal for the switch with a period of 2µs and a duty cycle of 0.5. I have given the input voltage a source impedance of 1W, which is reasonable, as perfect voltage sources don’t exist in reality. The input and output capacitances are represented by capacitors with series ESR resistances using the values that we just calculated. I have added the inductor’s series resistance for completeness. S2 is represented by a generic schottky diode, and S1 by a switch with an on-resistance of 110mW, like the Mosfet in the TPS5410. The “.tran” directive tells QSpice to perform a transient analysis over one second, but to display only the last millisecond. This is necessary because, when the converter starts from zero, it takes a little while to reach a steady state. The simulation output at the top of Fig.10 shows the inductor current at the top, the input voltage ripple in the centre and the output voltage ripple at the bottom. QSpice offers some handy utilities, including one to measure the peak-to-peak values of the displayed waveforms. You can see that the current ripple is 62mA, the input ripple is 55mV and the output ripple is 4.3mV. This accords pretty well with the calculated values (68mA for current ripple, 46mV or 67mV for input ripple and 3.8mV for output ripple). This is not surprising, since the simulation is using the same inputs as the calculations. The proof of the pudding would be to build the circuit and see how it performs. Test results I did just that, and the measured results are shown in Fig.11. The first oscilloscope trace is the current through the diode (measured across a 0.5W series resistor). This is a lot easier than measuring the inductor current directly. The ripple is derived from the slope on the top of the waveform. The measured ripple current is around 64mA, in line with the calculated value of 68mA. The input ripple (centre) current looks a lot like that in the simulation, but you can see some ringing on the waveform. This is caused by stray inductance in the circuit (for example, in the leads to the power supply) resonating with the input capacitance. The scale is 20mV/division, so the peak-to-peak ripple is in the region of 45mV, again very close to the calculated value of 46mV. Practical Electronics | April | 2026 Part 1: DC-DC Converters Finally, the output ripple is roughly the same shape as the simulation with the exception of switching spikes. These are due to the fast transitions of vx making their way through the inductor’s stray parallel capacitance. Nevertheless, the amplitude of the underlying ripple is about 4mV peak-to-peak, bang on the calculated 3.8mV value. If you want to eliminate the switching spikes, you can add a secondary LC filter; sometimes a ferrite bead is all it takes. But keep in mind that it may (likely will) affect transient regulation. I should point out that making these measurements is not trivial. If you were to use a normal ‘scope probe with its 150mm-long ground clip, you would see a whole lot of noise superimposed on these signals. Instead, I used a piece of thin 50W coax (RG316) with a BNC connector on one end. The screen on the other end is stripped back about 10mm, with the core and screen connected directly across the capacitor or resistor whose voltage is being measured. For signals that never exceed a volt or so, like the voltage across the 0.5W resistor used to measure the diode current, you can connect the coax directly to a scope with the 50W terminator enabled. You can’t do this for higher voltage signals, such as when measuring the input or output ripple, since the 50W terminator is usually not rated for more than a few volts. You may be able to use the normal high-impedance input and AC coupling, but I use a home-made power rail probe to eliminate the DC offset, allowing me to safely use the 50W input with its better noise performance. That device is described in a separate project in this issue, starting on page 47. Conclusion This introduction has demonstrated that power electronics is a field that requires the designer to shift back and forth between high-level circuit analysis and the minutiae of component behaviour. This is what makes it endlessly fascinating to me. Next month, we will look in detail at what is involved in designing the control loop of DC-to-DC converters like this one. Not understanding such control loops is probably the #1 problem that people have implementing PE such DC/DC converters! Practical Electronics | April | 2026 Fig.11: I built the circuit and measured the diode current (top), input voltage ripple (centre) and output voltage ripple (bottom). The results are very close to the calculated and simulated values. 31