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Circuit Surgery Regular clinic by Ian Bell Measuring circuit frequency response using a PC sound card, part 8: more on op amp compensation I n recent articles, we have been looking at how to measure frequency response. This was motivated by the need to measure the response of a practical implementation of an example digital filter (from our series on DSP) using the sound card (audio interface) of a PC or laptop, together with software for this purpose. As part of this topic, we have been discussing the signal conditioning that might be needed to interface the circuit under test to the sound card’s line inputs and outputs. Most recently, we investigated op amp feedback, frequency response and stability. Last month, we took a detailed look at the effect of capacitive loading on op amp amplifiers and its potential to cause instability (unwanted oscillation). This month we will consider various techniques for compensating op amp based amplifiers, ie, techniques to mitigate the instability problems. A recap on compensation Several gain values are used when discussing op amps with feedback. Without feedback, an op amp has open-loop gain (A O). With feedback, the circuit has a closed-loop gain, AC. The value -βAO is the loop gain, which is the gain around the closed feedback loop, with a fraction (β) of the output fed back. We often mention poles and zeros in the context of circuit stability. These are mathematical terms, but we can use the concepts in a practical sense to describe frequency responses. Above a pole, the amplifier’s gain decreases at a rate of 20dB per decade more than below it, and the phase shift becomes 90° more negative (assuming there are no other poles or zeros at similar frequencies). Above a zero, the gain – RC ZO increases at a rate of 20dB per decade Vout more than below it, and the phase shift + Vin CL becomes 90° more positive. As stated last month, a higher closedloop gain means a smaller feedback Fig.1: isolation resistor (RC) fraction, so higher-gain circuits are compensation for improving stability. 38 The op amp’s output impedance (ZO in Fig.1) is often ignored because the effective output impedance of a closedloop op amp amplifier is typically very low due to the action of negative feedback. However, it plays a role in circuit stability – it appears in the loop-gain equations for circuits such as that in Fig.1. To simplify circuit analysis, we may assume that an op amp’s output impedance is purely resistive and constant, but in real devices, it varies with frequency and may behave capacitively or inductively over some frequency ranges. Last month, we discussed output impedance in detail and described how to obtain plots of op amp output impedance against frequency using LTspice. generally more stable, with other aspects (such as the specific op amp used, loading and stray capacitance) being equal. Therefore, unity-gain buffers are the most challenging of the basic op amp circuits to achieve stability with, so they will be the focus of our examples. All op amps would produce circuits that are unstable unless something was done to reduce their open-loop gain at high frequencies. Most op amps are ‘compensated’ to be stable with unity closed-loop gain, but this compromises their performance in higher-gain circuits, so some are ‘decompensated’ and can only be used in circuits above a certain gain level (eg, 3-5×). Some op amps are uncompensated, and the user must add component(s) to provide compensation (usually including at least one capacitor). Our detailed discussion of op amp feedback and circuit stability in recent months, particularly with respect to problems caused by capacitive loads, leads to the fact that we often need to improve op amp stability by modifying a circuit. This usually involves adding zeros or poles to the loop gain. Last month, we looked in detail at compensation for capacitive loadinginduced instability using an isolation resistor – a resistor in series with the op amp’s output, outside the feedback loop (see Fig.1). This approach adds a zero to the loop gain, which improves stability by reducing phase shift in comparison with the uncompensated case. It is straightforward to implement, but can cause gain inaccuracy as it’s outside the feedback loop. In-loop compensation Using an isolation resistor for compensation results in the gain of the whole circuit no longer matching the designed value (no longer unity for a buffer, or the values set by the feedback resistors for other amplifiers). This is because the isolation resistor forms a potential divider with any load resistance (RL in Fig.1), which reduces the amplitude of the output and hence the effective gain of the circuit. If precision gain is important, this is a major disadvantage. Another way to think about this is that the circuit’s output is not fully under the influence of the feedback, so it is not able to respond to load changes, which may lead to degraded circuit performance. RF CC – Vop Vout RL Vin ZO RC + Vop CL Fig.2: in-loop or ‘dual feedback’ compensation. Practical Electronics | May | 2026 RL Fig.3: an LTspice schematic for investigating the efficacy of in-loop compensation. A potential solution to this problem is to include the isolation resistor used for compensation (RC ) inside the feedback loop (see Fig.2), which is called in-loop compensation. As a feedback capacitor for compensation (CC ) is also required, there are two feedback paths, so the technique is also referred to as ‘dual-feedback compensation’. The circuit in Fig.2 is a unity-gain buffer, like the circuit in Fig.1, but we have included a feedback resistor (RF). The resistor does not change the basic closed-loop gain. Ignoring the feedback capacitor (ie, the situation at low frequencies), this circuit still has 100% feedback via the resistor as there is no grounded resistor, which would be needed to set higher closed-loop gains. The use of a feedback resistor can provide better compensation than just using the typical direct connection from the output to the inverting input, including when isolation resistor compensation is used, as in Fig.1. Considering the simpler case, the key effects of this approach, with RF = 0Ω and suitable values for the other components, are to add a relatively low-frequency pole, plus a zero above the pole, to the transfer function. These have the potential to improve stability. The circuit also produces a higher-­ frequency pole in the loop gain, which is generally of less importance. The greater complexity of the in-loop compensation means that the loop-gain equation is quite large and cumbersome, so we will not go into the full algebraic analysis and derivation of the equations here. Ignoring the op amp’s output impedance (ZO ) and load resistance (RL ), we can obtain a simplified, approximate expression for the pole frequency as: f p≈ 1 2 π ( R C )( C L +C C ) We can use the parallel combination of RC and RL in place of RC in the above if we need to take account of the load resistance. The pole can act similarly to the dominant pole used in the builtin compensation in most op amps; that 1 is, lowering f p ≈ the gain as frequency in2 πto( Runity creases to get gain ) at a C )( C loop L +C C lower frequency. The zero frequency is: f z= 1 2 π RC C C The zero has a similar role as in the 1+ resistor 1+0.8approach π C L B R–O it rebasic isolation C≥ ducesRphase shift0.4 at frequencies above πC B the pole. We could use RLC + RO instead (where RO represents 10 Ra Cpurely C L resistive version of Z or just RC if necessary. COC) = If we include RF, weRget F another zero in the response, which provides more 1/ the s C Lphase shift. compensation for √ R +1/ s C O L values Choosing component The choice of values for the compo1 nents for in-loop compensation (RC & R O / R L +sR C CC) is not1+ completely straightforward O L due the complex interactions in the circuit – the feedback1 has poles and a f p= zero, while the op amp has poles and an 2 π ( Rthat O || R L ) C Lwith freoutput impedance varies quency. Therefore, it may be necessary to experiment to find1optimal values. f p= Simulations used to illus2 π (like R L || R ( R O ||those S)C L trate this article) can be used to rapidly assess different value combinations 1 implementation. before tryingfazphysical = 2 π RS C The isolation resistor (RSC ) should be as small as possible; values in the 10s 3 used. Idealto 100s of ohms are often C Sbe = smaller than the load ly, RC should 2 π f pk R S resistance (R L ), maybe by a factor of 10 or more. 1 may cover caOp amp manufactures f p= 2 π R pacitive loading in device E C p datasheets or other technical documents where values are suggested1 for specific def pa=feedback resistor (R ) is vices. Where F 2π R C F 1 2 π RC C C Practical Electronics f = | May | 2026 z F used, it should be much larger than RC (maybe 100 times or more) to reduce interaction with the isolation resistor. The frequency of the zero (fz ) is typically set to be about a decade below the unity gain (0dB) frequency of the uncompensated loop gain. Given that the loop gain is likely to be dropping at 20dB per decade at this point, we can also say that the zero should be close to the frequency at which the loop gain is 20dB. With values of RC in the range mentioned above, this gives a starting point for CC using the fz equation above. The pole frequency is typically about a decade below the zero frequency. Comparing the fp and fz equations above, this implies that the load capacitance is about ten times CC, which provides another way to choose a possible value for CC. Component values with RF > 0Ω The preceding discussion provides useful advice for selecting values but these are not strict rules. However, an application note from Intersil (now Renesas; see https://pemag.au/link/acb8) 1 provides design formulae for circuits f ≈ where RppF is2included. π ( R CC )( C LLThe +C CCapplication note is for their ISL7xx44) family of wideband amplifiers but should be 1 Their formumore widely f zapplicable. = π R CC C CC lae for RC andz CC2are: R CC ≥ 1+ √ 1+0.8 π C LL B R OO 0.4 π C LL B C CC = 10 R CC C LL R FF Here, B is the gain-bandwidth prod1/ s C LL R is chosen uct of the amplifier and F R OO +1/ s CRLLC. The first of to be 100 or more times these formulae is based on the decade 1 mentioned above, below unity-gain rule while the second formula is based on 1+ R OO / associated R LL +sR OO C with L L setting the zero RF a decade below that. 1 Simulation examples 2 π ( R OO || R LL ) C LL f pp = The LTspice circuit shown in Fig.3 can be used to investigate the loop1 f pp = gain responses of an op amp unity-gain π ( R OO compensation. || R LL || R SS ) C LL This buffer with 2in-loop example uses the OPAx134 op amp, which should be familiar from previ1 f zz = ous examples. Likewise, the 2 π R SS C SS simulation setup is as used in previous loop-gain examples and was discussed in detail C SS =20263issue. in the February π unloaded f pk R In Fig.3, U1 is 2an circuit, pk SS while U2 is loaded with a 20nF capaci1 was previously tive load – this circuit = shown to bef ppunstable. 2 π R EEThe C pp U3 circuit has in-loop compensation but without a feedback resistor (the feedback 1 f pp = 1 2 π R FF C FF 39 Fig.5: results from using out-of-loop isolation resistor compensation for op amp buffers from last month. Fig.4: the results from simulating the circuits in Fig.3. is a direct connection to the inverting input, as for U1 and U2). From our simulation of the same circuit last month, we know the 0dB frequency of the loop gain is around 1.1MHz, so a zero in the low hundreds of kilohertz should be about right. For the RC and CC values shown in Fig.3, the f z formula above gives 1 ÷ (2π × 500Ω × 2×10-9F) = 160kHz, which fits the guideline discussed above. The value of CC is about a tenth of CL, as expected. The zero frequency is about 1 ÷ (2π × 500Ω × [20×10-9F + 2×10-9F]) = 15kHz using the fP formula above. The U4 circuit includes a feedback resistor. Using the Intersil formulae with CL = 20nF, RO = 54Ω as discussed last month, and B = 8MHz from the OPAx134 datasheet, we get RC ≈ 30Ω. Setting RF = 100 × 30Ω = 3kΩ, we get CC = 2nF (the same as the value used in the U3 circuit). It is worth noting that the isolation resistor is significantly lower in value in this circuit. Fig.4 shows the simulation results with plots of the loop-gain frequency response. The green trace is the unloaded response from the U1 circuit while the red trace is the unstable response from the loaded but uncompensated U2 circuit. The yellow trace in Fig.4 shows the response of the compensated buffer without the feedback resistor (U3 circuit). The cyan plot in Fig.4 shows the response of the U4 circuit with the feedback resistor. The response is much closer to the unloaded case than the U3 circuit without the resistor, and the phase margin is better, indicating that it is doing a better job of compensating for the load. circuits on the two graphs have a similar general shape, but have significant differences relative to the uncompensated response, which is due to the different compensation implementations. The circuit with in-loop compensation has a pole at a relatively low frequency. In Fig.4, we see the phase (dotted yellow trace) decreasing with respect to the red (uncompensated) trace, starting at just over 1kHz. This is the effect of the pole at 15kHz (the phase shift effect starts about a decade below the pole frequency). This early decrease in phase is not what we want for stability, but it is safe in this case because the phase shift remains sufficiently far above zero to not be a problem. As the frequency increases further, the zero at 160kHz reverses most of the shift due to the pole, keeping the phase shift well above zero. In the out-of-loop case (Fig.5), the yellow and red phase traces track, including at about 20kHz, where the pole due to the load capacitance (which is at 146kHz) begins to affect the response. The curves separate at around 100kHz as the phase shift of the compensated circuit increases due to the zero caused by the isolation resistor. The gain for the in-loop case (solid yellow in Fig.4) shows a reduction with respect to the uncompensated case in the range of 10kHz to 1MHz. A key point here is that the loop gain of the compensated circuit reaches unity (0dB) at a lower frequency than the uncompensated circuit. This is the advantage in stability provided by the low-frequency pole. In comparison, the out-of-loop response (Fig.5) shows the gain decreasing more slowly for the compensated case. This is not ideal, but the phase increase due to the zero provides a stability improvement. The differences and similarities between the in-loop and out-of-loop examples help to show that it is the specific interaction between the poles and zeros in a response that determines stability. Both examples show similar phase margins of around 50° but have different pole-to-zero relationships. Fig.7: a compensated buffer circuit with a load resistance. Compared to last month’s solution For comparison, Fig.5 shows the results from the out-of-loop isolation resistor compensation of the same buffer from last month. The (uncompensated circuit) red trace in Fig.5 is the same as in Fig.4. The yellow traces for the compensated 40 Fig.6: an LTspice schematic for closedloop simulation of the circuits in Fig.3. Practical Electronics | May | 2026 Fig.8: simulation results for the circuits in Fig.6 and Fig.7 with 100mV step input signals. Fig.10: AC analysis results for the circuits in Fig.6 and Fig.7. Fig.9: simulation results for the circuits in Fig.6 and Fig.7 with 10V step input signals. Fig.11: illustrating poor compensation component value choices. Closed loop simulations Fig.6 shows an LTspice schematic for closed-loop simulation (normal circuit operation) of the circuits in Fig.3. The op amp instance names (U1 etc) and output names (op1 etc) are the same. Fig.7 shows an additional circuit where a resistive load has been added to the output. The results for a transient simulation of these circuits with a 100mV step input are in Fig.8. As discussed in previous months, a step input will often trigger continuous oscillation in an unstable circuit and will result in large overshoots and ringing (decaying oscillation) in circuits with a poor phase margin. Therefore, they provide useful insights into stability. The trace colours in Fig.8 are the same as those for Fig.4. The output of the unstable capacitively loaded circuit with U2 (red in Fig.4) is not shown, as the oscillations would swamp the graph. The results show a similar height overshoot for the unloaded circuit (green) and the one compensated without a feedback resistor (yellow). With the feedback resistor (cyan), there is a more damped response (little overshoot). Unlike the out-of-loop compensation discussed last month, there is no gain error when a load resistance is present (see the circuit in Fig.7 and the magenta trace in Fig.8) – the output reaches Practical Electronics | May | 2026 100mV, the same as the cases without resistive load. Fig.9 shows the response of the same circuits with a 10V step input. In this case, the resistively loaded circuit produces an output level below the 10V expected from a unity-gain circuit. This looks similar to the gain error discussed last month but it is different. The problem is due to the op amp reaching its maximum output level. The isolation resistor (R4 in Fig.7) and resistive load (R6) form a potential divider in the same way as they do for the out-of-loop feedback circuit, but because the feedback is taken from the final circuit output. The op amp adjusts the circuit output to the required level until it runs out of headroom. The potential divider means that op amp output must go to a higher voltage to control the circuit output to the required level. So, for a given maximum op amp output, there will be a lower maximum circuit output. The traces in Fig.9 show that the op amp can deliver 10V but cannot generate a sufficient voltage to obtain 10V from the potential divider formed by the isolation resistor and the resistive load in this example. AC analysis Fig.10 shows the AC analysis results for the closed-loop gains of the circuits in Fig.6 and Fig.7. The traces have the same colour as in Fig.4. The gain response of the uncompensated capacitively loaded circuit (red trace) shows a large peak, typical of an unstable circuit. The two compensated circuits without resistive loads (cyan and yellow traces) have much smaller peaks. The circuit with the resistive load (magenta trace) has the correct (unity) gain at low frequencies, like the other cases. This confirms the accurate gain, also visible in Fig.8. A similar graph last month for out-of-loop isolation resistor compensation showed the gain error inherent in that approach. Bad values The circuit in Fig.11 is an addition to the schematic in Fig.3. It is a version Simulation files Most Circuit Surgery columns feature the use of the free circuit simulation software LTSpice. It is used to support descriptions and analysis in Circuit Surgery. The examples and files for this issue are available for download: https://pemag.au/link/acb7 41 Fig.12: the simulation results for the circuits in Figs.3 & 10. Fig.13: a transient step response simulation of the Fig.11 circuit. likely to be a problem when using the components and op amp close to its minimum supply load as shown in voltage, where its full swing is needed Fig.11. for the output. Fig.14 shows Users of this approach should also the closed-loop be aware of the possibility of poor frequency restability even if the phase margin is sponse of this apparently good. circuit with the same axis scales as Fig.10. Again, we Snubber network compensation have an indicator Another method of 1 compensating caf ≈ of poor stability – pacitive ploads is to connect 2 π ( R C )( C L +CaCsnubber ) the peak is much network, comprising a resistor (RS ) and larger than the capacitor (CS ) in series, at the output 1 compensated cirof the op amp f z =(see Fig.15). Fig.14: an AC analysis simulation of the circuit in Fig.11. 2 π R cuit responses in Two months ago, we the C Canalysed C Fig.10, although it is much lower than effect of a capacitive load on the op of the in-loop compensated buffer with the peak for the fully unstable circuit. amp. To keep asa feedback resistor, but with different 1+ things 1+0.8 simple, π C L B Rwe O R Cthat ≥ Z O was resistive The results from the circuit in Fig.11 sumed compensation component values. The (as R O ) L B that the show that an apparently good phase loop-gain response is shown in Fig.12 and ignored R L0.4 . Weπ C found margin is not always sufficient to (orange trace) along with the unloadloop gain with the load capacitance 10 R C Cthe guarantee stability. The values of the ed case (green, same as in Fig.4) for is the loop-gain without 1 L load (that C = C components do not conform to the reference. is, -βAOf(s)) the potential R by p ≈multiplied 2 πof:( R C )( CF L +C C ) design guidelines and formulae disThe response has some interesting divider factor cussed above. features; its shape is somewhat differ1/ s C L 1 This example was produced to illusent from those in the other responses f zR=O +1/ s C L trate the fact that this compensation we have looked at. 2 π RC C C technique can give poor results with There is a notch in the gain curve If we include RL, we need to replace some combinations of component around 100kHz – the gain starts to deboth occurrences of1 1÷sCL in the equa1+ 1+0.8 π C L Bcapacitor) RO values, which could be inadvertently crease more rapidly and then quickly tion (the the load 1+ R O / RofL +sR R C ≥reactance OCL chosen. It demonstrates that you should changes direction and increases again 0.4combination π CL B with the parallel of C L check the closed-loop frequency rebefore returning to match the unloadand RL. 10 R1C Cinvolves sponse and step response, as well as ed gain curve. The phase plot shows This means a few f p = the algebra L C = 2C π it( RisO not || R Ltoo C difficult. ) phase margin, when designing coma large and very rapid change, also more terms, but L RF pensation circuits. around 100kHz. After a few steps, we can get the equaThe shape of the loop-gain and phase LTspice reports a phase margin of tion in the form of divided polynomials 1 1/ sC f p= responses in Fig.12 indicates the pres64.5° (Fig.12), which should mean that in the s-domain. This isLneeded to obtain 2 π R || Rbeen ( Ohas L || Rdescribed S)C L ence of a pair of complex conjugate the circuit has very good stability, but poles and zeros, in R Oas+1/ sC L zeros. the gain notch and rapid phase change previous examples. Specifically, we get: 1 This term relates to the s-domain (Lain the loop-gain response should act as f z= 1 place) analysis of circuits, which we a warning that there may be problems R S C SC 1+ R O /2RπL +sR O L introduced in the January 2026 issue with this circuit. and have used to analyse of some of the Fig.13 shows a transient simulation 13 C S= circuits discussed since. We have kept of the step response. The large overf p= 2 π f pk R S – to simple cases; complex conjugates go shoot and ringing indicate that the ZO 2 π ( R O || R L ) C L Vout beyond what we have covered. circuit does not have good stability Vop 1 In summary, the in-loop compensaand would likely be unacceptable in f = 1 RL tion technique overcomes the gain error Vin many designs. f+p = p 2 π CRS E C pCL Snubber 2 π R || R || R C ( O R L S) L problem with an out-of-loop isolation The results in Fig.13 were obtained S resistor, but is more complex and can from a copy of the U4 circuit in Fig.6 Fig.15: snubber 1 f = suffer from a more limited output swing. (with the op amp labelled U6 and output 1 p network f =2 π RF C F The output swing concern is more op6) using the values of compensation compensation.z √ √ 2 π RS C S 42 Practical Electronics 3 | May | 2026 C S= 2 π f pk R S f z= RC ≥ 1 2 π RC C C 1+ √ 1+0.8 π C L B R O 0.4 π C L B 10 R C C L CC= RF f p≈ 1/ s C L R O +1/ s C L 1 2 π ( R C )( C L +C C ) f z= 1 1+ R O / R L +sR O C L 1 2 π RC C C f p= √ 1 2 π ( R O || R L ) C L 1+of LTspice 1+0.8circuits π C L BforR Oinvestigating snubber network compensation. Fig.16: a set RC ≥ 0.4 π C B L As usual, to find the pole(s), we solve for s with the denominator equal to 10 R C C L zero. We then substitute s = jω = j2πf CC= R and find the magnitude 1 F to get a pole f p≈ frequency. 2 π ( R C )( C L +C C ) A trick we need 1/ here s C L is to notice that it is possible to arrange the pole freR +1/ 1s C L quency equation the term f z =O so it contains RLRO ÷ (RL + RO),2which π R C CisCthe parallel combination of RL 1and RO (denoted as R L||R O). 1+ We / Rthen 1+Rcan πwrite C R O pole O1+0.8 L +sR OC L the LB frequency R C ≥ as: √ f p= 0.4 π1C L B 2 π (10 R OR||CRCL )LC L C = C It is this pole, due to R Fthe load capacitance, that increases1 the phase shift f p = instability. and causes 2 π ( 1/ R Os||CRLL || R S ) C L If we add another, smaller resistor in +1/ s C Ljust the snubparallel with R RLO (adding 1 ber resistor, fRS= , and ignoring CS for the z 2 π R moment) then R S 1willS C beS in parallel combination with R L in the pole fre1+ R O / R L +sR O C L quency equation. 3 S = to work through all We don’tChave 2 π f1pk R S the algebra pole frequenf p =for the new cy, because we replace 2 can π ( Rjust C R with O || R 1 toL )get:L L RL||RS in the equation f p= 2 π R1E C p f p= 2 π ( R O || R1 L || R S ) C L p =at a higher frequency, This willf be 2 π R1F C compared F particularly if RS is small to f = z RL. A small RS will 2 πdominate R S C S the paral- lel resistance terms and increase fp due to the reciprocal relationship. Moving 3 the loop-gain C pole S = to a higher frequency 2 π f pk will increase stability (inRother words, S provide a better phase margin) because 1 will be at a the phase shift it causes f p = the op amp’s gain is frequency where 2 π RE C p lower. If we only used a low-value resistor in 1 parallel with f pthe = load, we would shift 2 π R the pole as described,F C but F we would also reduce the gain of the circuit at low frequencies. This would cause gain errors, or even make the circuit unusable. Practical Electronics | May | 2026 1 Adding the 2 π (snubber R O || R L ||capacitor R S ) C L cre- Limitations f = p ates a zero at: f z= 1 2 π RS C S f z= 1 2 π RC C C 1+ √ 1+0.8 π C L B R O R C ≥network can adequately comsnubber 0.4 πopCamp. LB pensate for a given 10 R C Cvalues L Snubber C component = C A trial-and-error approach to selectRF ing snubber values was described in an Elantec application 1/ s C L note from 1998 (https://pemag.au/link/acb9). Intersil/ R O +1/ s C L SemiconducRenesas acquired Elantec tor in 2002. The procedure is as follows. 1 Find the peak frequency (fpk) in the circuit’s closed loop response, 1+ R O / R L +sR O C L then load the amplifier with different snubber resistors, without the snubber the ca1 pacitor, funtil p = an acceptable reduction in 2 π R || R Lresistor ( Owith ) C L value the peak is obtained RS (by simulation or measurement). RS is typically in the 10s 1 to 100s of ohms. p= Thef capacitor needs to have a lower 2 π ( R OR|| (say, R L || Rone S)C L impedance than third the S value) at the peak frequency, so RS ÷ 1 3 = 1 ÷ (2πf f zpk=C S). This is equivalent to making the snubber zero frequency 2 π RS C S three times lower than fpk, so: 3 C S= With the capacitor in place, the 2 π f pk R S snubber is effectively3 open-circuit at C S= sufficiently low2frequencies, so the π f pk R S 1 snubber resistor has little or no effect Simulations f p= there. At higher frequencies, the caFig.16 shows an LTspice 2 π R E C pschematic for 1 f p= pacitor needs to have low impedance investigating snubber network compen2π R E C p loads the so that the snubber resistor sation. The setup is similar to previous 1 op amp, reducing the circuit’s closedclosed-loopf examples, with the U1 cirp= 2 π R F Cbuffer 1 F loop gain. cuit being an unloaded and the f = p Specifically, we need the loading U2 circuit a capacitively loaded ver2 π RF C F effect to become active at around the sion with no compensation. The load frequency where peaking occurs, such capacitance (1nF) is smaller than in as that seen in Fig.9 (red trace) and previous examples, in line with the Fig.13. The resistor needs to load the op limitations discussed above. amp sufficiently to reduce the peaking The U3 circuit includes a snubber reenough to provide acceptable stability. sistor without a capacitor. This circuit The larger C L and smaller R S are is for investigating the effect of the resistor on the gain peaking as described needed to overcome the effects of the above; it is not an implementation of load. Unfortunately, there are problems the compensation. The U4 circuit has if RS is too small. A smaller RS requires the snubber compensation (R2, C3) and a larger CS, but if CS is too large, it will a load resistor (R3) as well as the cahave too low an impedance at low frepacitive load (C4). quencies, affecting the gain, which we Fig.17 shows the peaking in the closeddon’t want. loop response. The red trace (op2) is Also, if RS is too small, the op amp the loaded, uncompensated case with may go into protective current limexcessive peaking at 4.5MHz. The blue iting driving it, which will limit the output voltage (to the current limit t i m e s R S) a n d / or limit the rate of change of the output voltage, because limiting the current will limit the rate of change of the voltage on CS. The impact of these dependencies is to limit the maximum load capacitance that the Fig.17: AC analysis results for the circuits in Fig.16. 43 CC= 10 R C C L RF 1/ s C LAs well as its use for R O +1/ potential sC 1 L instability due to f p≈ capacitive 2 π ( R1C )( C L +C C ) loads, this technique is 1+ R O / R L +sR a l s oO C c oL m m o n l y 1 used to compenf z= 2 π Rsate 1C Cfor C instability f p= capacitance 2 π ( R Odue || R Lto) C L atπthe 1+ √ 1+0.8 C L BopR Oamp’s RC ≥ inputs. This input 0.4 πc1aCpLaBc i t a n c e i s f p= 2 π ( R O || R || R C a comtypically 10 R CL C L S ) ofL the op C C = bination amp’s own input R 1F Fig.18: transient analysis (step response) for the circuits inf Fig.16. capacitance and z= 2 π RS C S the stray (parasitic) due trace (op3) shows the effect of adding 1/ s C Lcapacitance to the wiring and components conjust a snubber resistor (R1 in Fig.16). R O +1/ s3C L nected to the input. The peak is reduced significantly. C Sop = amp’s inverting Parasitic input2capacitance Of course, the decision on what is π f pk R S (CP) creacceptable depends on the context. We ates a pole in the 1 loop gain at: do not have a specific requirement in 1 OCL 1+ R O / R L +sR f p= this discussion, so we are assuming that 2 π RE C p the response with the 30Ω resistor is 1 deemed acceptable. Using the formula Here,f Rp E=is the equivalent parallel π ( gain-setting R O1|| R L ) C L resistors above, we get CS = 3 ÷ (2π × 4.5×106Hz resistance fof2= the p (feedback and input re× 40Ω) = 3.5nF. The yellow trace (op4) 2 π R ForCgrounded F sistor). Recall that for is the response with the snubber ca1 a load capacitor f p= without load resistors, the relevant pole pacitor in place. 2 π ( R. O || R L || R S ) C L is at 1 ÷ 2πR C Using the same approach as in Fig.3 and Fig.4 (and previous examples), we obtain a phase margin of 36° (not shown) for the U4 circuit with the snubber in Fig.16. This is not above the commonly used rule-of-thumb minimum phase margin of 45°, but is significantly better than the 0.5° phase margin without the snubber, so it may be acceptable. Fig.18 shows the step response for the unloaded (op1, green) and uncompensated (op2, red) cases. We can see significant oscillations with the capacitive load. These oscillations do eventually decay (visible using a longer timescale), but the circuit is very close to being fully unstable. With the snubber in place (op4, yellow), there is still a fair amount of overshoot, but the oscillation decays quickly. The blue trace (op3) is for the U3 circuit with just the resistor. This shows the need for the capacitor to prevent gain reduction at lower frequencies. Feedback capacitor compensation Another compensation technique that is commonly used is to place a capacitor (CF) across the feedback resistor (see Fig.19). This could be seen as a simplified version of the in-loop approach, and as such may be less effective. However, for amplifiers with above-unity gain (which already have a feedback resistor), it only requires one additional component and, as previously discussed, higher gain circuits are generally easier to stabilise. 44 O L Typically, CP is much smaller (a few 1than the troubleto tens of picofarads) f z= causing load capacitances 2 π R S C S (CL) we have been looking at in the examples above, but the pole frequency 3 depends on the C Swhich = gain resistors are typically much 2 πamp’s f pk R output S larger than the op resistance (RO), so the effects can be similar. 1 The feedback f p = capacitor introduces a zero in the loop 2gain, π R Ewhich C p can counteract the instability-causing pole: f p= 1 2 π RF C F RF CF RG – Vout Vin ZO + Vop CL RL Fig.19: feedback capacitor compensation. A starting point for component selection is to match the zero frequency from the compensation capacitor to the pole frequency from the load or parasitics. Some experimentation may improve the results, as the overall behaviour is complicated by the higher-frequency poles in the loop gain. Simulation example Fig.20 shows an LTspice schematic for investigating feedback capacitor compensation with a similar setup to previous examples. The circuits are non-inverting amplifiers with a gain of 10. Assuming RO = 54Ω, as used previously, we get the pole due to the load of 30nF (C3) at 1 ÷ (2π × 54Ω × 30×10-9F) = 98kHz. Setting the zero from the feedback capacitor at the same frequency requires CF = 1 ÷ (2π × 98×103Hz × 9×103Ω) = 180pF (the value of C2 in Fig.20). Using the same approach as in Fig.3 and Fig.4 (and previous examples), we can obtain phase margins for the circuits in Fig.20. For the loaded, uncompensated circuit (U2), we get just 17°. This does not imply continuous oscillation, but we might expect significant ringing and Fig.20: an LTspice circuit for testing feedback capacitor compensation. Practical Electronics | May | 2026 Fig.21: transient analysis (step response) for the circuits in Fig.20. Fig.22: the AC analysis results for the circuits in Fig.20. 180pF (op3, yellow trace), indicating that some experimentation with values can optimise the value compared with the calculation given above. Similarly, the frequency responses in Fig.22 show significantly peaking for the loaded circuit without compensation (red trace) and improved bandwidth for compensation with CF = 100pF (cyan trace) compared with CF = 180pF (yellow trace). This completes our look at load capacitance compensation for op amps. Unwanted oscillations are a common problem and, although we have not covered every possible approach, we have looked at many of the key techniques for the potential for full instability with a shift in conditions. With the feedback capacitor (U3), the phase margin improves significantly to 51°. Fig.21 shows the step responses from the circuits in Fig.20, with an additional copy of the circuit using U4 with the same values as the U3 circuit, except CF = 100pF, rather than 180pF as calculated above. The U4 circuit has a better phase margin of 63°. In Fig.21, we see significant overshoot and ringing for the uncompensated capacitive load (op2, red trace), which is eliminated by the feedback capacitor. Using CF = 100pF (op4, cyan trace) provides a faster step response than CF = stabilising troublesome op amp circuits. Conclusion We have looked at several commonly used approaches to improving the stability of op amp based amplifier circuits. Not doubt there are other methods that can be used. Which one you choose will depend on the op amp being used, the closed-loop gain, how much capacitance the output is exposed to and other factors. These methods can be used in combination, if necessary. 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