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By Andrew Levido Power Electronics Part 7: Resonant Converters & Soft Switching Higher switching frequencies can make input and output filters simpler, with smaller magnetics. They also allow a faster response to changes in the load current. Switching losses become a major problem at higher frequencies, but there is a solution. W e saw last month that switching losses in power electronic converters can become dominant as switching frequencies increase. However, higher frequencies are desirable as they allow the designer to increase the bandwidth of the control system, so it can respond to load changes more quickly. We will start with a quick review of how a Mosfet switches on and off. The upper-left part of Fig.1 shows a typical boost converter. We will assume this is operating in periodic steadystate and that the inductor current is more-or-less constant at the timescale of the switch-on and switch-off of the Mosfet, typically in the 10ns range. We will also assume that the Mosfet is off and the full load current is flowing through the diode at the instant of switch-off. I have also drawn the gate equivalent circuit of the Mosfet below the boost converter circuit. When the device is off, the gate voltage is zero, the gatesource capacitance (Cgs) is fully discharged and the gate-drain capacitance (Cgd) is charged to the drain voltage, vd. The gate-drain capacitance is much smaller than the gate-source capacitance, but it plays a big part in switching losses, as we shall see. The resistance Rg is the combination Fig.1: in inductive circuits such as this, a Mosfet’s drain voltage cannot begin to change until the current fully commutates to or from it. This results in significant switch-on and switch-off losses. The diode reverse recovery current makes this worse. 76 Silicon Chip Australia's electronics magazine of the internal gate resistance and the source impedance of the Mosfet driver. The voltage vg(int) represents the voltage at the gate metallisation on the Mosfet die that modulates the conductivity of the channel. The plot labelled “Mosfet switch-on” shows what happens when we switch the Mosfet on. When the gate voltage is applied at time t0, nothing happens immediately because the internal gate voltage (black trace) has yet to charge to the switch-on threshold. Once the threshold voltage is reached at time t1, the drain current (red trace) begins to rise. Because the load is inductive, the drain current must rise to its full extent before the drain-source voltage can begin to fall, at time t2. You can understand why this is the case with reference to the boost converter schematic. When the Mosfet starts to conduct, the current shifts (commutates) from the diode to the Mosfet. Until the Mosfet takes over 100% of the inductor current, the balance continues to flow through the diode, keeping the Mosfet’s drain voltage fixed at the converter’s output voltage. This same phenomenon occurs in many converter types, including buck converters, but it’s easiest to visualise with the boost converter since the Mosfet is grounded. The rate at which the drain voltage can fall is determined by how fast Cgd can be discharged. The only thing discharging Cgd is the current i Cgd provided by the gate drive. While vds is falling, all the gate current is diverted into Cgd due to the Miller effect, so the internal gate voltage remains essentially constant until the drain-source voltage reaches (almost) zero at time t3. This ‘flat spot’ on the internal gate voltage is known as the Miller plateau. After t4, the two gate capacitances are effectively in parallel, and the siliconchip.com.au siliconchip.com.au 20V 18V 16V V(vg) 14V 12V 10V 8V 6V 4V 2V 0V 8kW V(vd)* - I(R1) 6kW 4kW 2kW -2kW 500V 30A 400V 24A 300V 18A 200V 12A 100V 6A 0V 380.96μs 380.97μs 380.98μs 380.99μs 381.00μs 381.01μs 381.02μs 381.03μs 381.04μs 381.05μs -I(R1) 0kW V(vd) gate voltage continues to rise to its final value at t4, where the channel is fully enhanced and the Mosfet’s on-­ resistance is minimised. Switch-off is basically the reverse of this process. The importance of all this is that there is a period, from t1 to t3, where there is significant voltage across and current flowing through the device at the same time, and therefore considerable power dissipated during the relatively short switch-on and switchoff periods. In fact, things are worse than I just described if we take into account the ‘switch-off’ characteristics of the diode. When a diode switches from the conduction state to the blocking state, it does not switch off instantaneously. A large reverse current flows for a short period while the diode recovers its blocking capability – shown in the “Diode switch-off” plot. This ‘reverse recovery’ current occurs because the majority carriers stored in the PN junction have to be extracted when the diode is reverse-­ biased. The amount of this charge (Qrr in the data sheets) is small, but because it moves very quickly, the peak current can be high. This does not have a huge impact on the diode losses, but can contribute significantly to Mosfet losses. When the Mosfet switches on at time t2 and the inductor current commutates from the diode, the Mosfet sees an additional current spike due to the diode’s reverse recovery (bottom chart). This occurs while the drainsource voltage is still high, so it adds to the Mosfet switch-on losses. While it is often convenient to think of power Mosfets as voltage-driven devices, the description above demonstrates the importance of gate current in the switching process. The rate of change of drain-source voltage (dv/dt) during switching depends on the gatedrain capacitance and the gate current that charges and discharges it. You generally need to drive the gate hard if you want to increase the dv/ dt and minimise switching loss. However, a higher dv/dt produces in significantly more conducted and radiated EMI, so finding a compromise is usually necessary. How significant are these switching losses? I made a simulation of the boost converter circuit using the SiHA120N60E Mosfet. This is a 650V, 25A-rated device in a TO-220 package. 0A 381.06μs Fig.2: this simulation of the circuit in Fig.1 uses the SiHA120N60E Mosfet switching 400V at 20A. The switch-on losses peak at 7.5kW, although only for a few nanoseconds. Fig.3: a resonant circuit like this can be described by two quantities: the natural frequency and the damping factor. We often use the ‘quality factor’ or Q to describe the relationship between the two. I set the boost converter input voltage to 200V, the output voltage to 400V and the load current to a slightly unrealistic 20A. I drove the gate to 15V via a 10W gate resistor. The simulated switching waveforms are shown in Fig.2. You can clearly see that the drain current (red) rises fully before the drain-source voltage (blue) can begin to fall. You can also see the Miller plateau in the gate voltage (green). The purple trace is the instantaneous power dissipation in the Mosfet. It peaks at about 7.5kW, although the whole spike is only about eight nanoseconds long. The total energy dissipated at switch-on is about 30µJ. If we assume the same for switch off, the total will be 60µJ per cycle. At 10kHz, this corresponds to a modest 600mW in losses, Australia's electronics magazine but if we want to switch at 1MHz, we are looking at switching losses of 60W – a much less attractive proposition! Resonant circuits Since switching losses are the product of voltage across and current through the switch, one way to reduce or eliminate switching losses would be to ensure that one or both of these quantities is zero at the time of switching. This type of switching is sometimes called zero-voltage switching (ZVS), zero-current switching (ZCS) or just described by the generic term ‘soft switching’. The usual way to ensure that voltage or current is zero when we switch is to exploit resonance. For a quick refresher on resonance, take a look at Fig.3, which shows a simple RLC May 2026  77 filter with a DC source and a switch that closes at time zero. When the switch initially closes, a current will build up in the inductor, charging the capacitor through the resistor. The voltage on the capacitor will continue to rise past Vsrc to the point where the current in the inductor reverses and it begins to fall. When the capacitor voltage falls low enough that the inductor current reverses again, it starts to rise. This oscillation continues, but is damped by the resistance. Eventually, the capacitor voltage settles at Vsrc and the inductor current goes to zero. This is a damped oscillation. If the resistance were zero, the oscillations would continue indefinitely (in theory). If the resistor had a very high value, the circuit would behave like a standard RC filter, with the capacitor voltage rising smoothly (and exponentially) to Vsrc. We can therefore describe these resonant circuits with two quantities: the natural frequency and the damping factor. The natural frequency, designated ω0, is the frequency at which the undamped LC network would oscillate. This is given by ω0 = 1 ÷ √LC. The damping factor, designated by the Greek letter α, is equal to R ÷ 2L. The damped circuit will oscillate at a frequency lower than the natural frequency. This frequency, ωd, called the natural frequency, is equal to √ω02 – α2. These frequencies are expressed in radians per second, where 2π radians per second equals 1Hz. We don’t generally use the damping factor directly in our design process. Instead, we use a related quantity, the ‘quality factor’ or Q of the circuit. Q relates the damping factor to the natural frequency by the expression Q = ω0 ÷ 2α. A resonant circuit with high Q has low damping, and vice versa. Silicon Chip kcaBBack Issues $10.00 + post $11.50 + post $12.50 + post $13.00 + post $14.00 + post January 1997 to October 2021 November 2021 to September 2023 October 2023 to September 2024 October 2024 to August 2025 September 2025 onwards All back issues after February 2015 are in stock, while most from January 1997 to December 2014 are available. For a full list of all available issues, visit: siliconchip.com. au/Shop/2 PDF versions are available for all issues at siliconchip.com.au/Shop/12 We also sell photocopies of individual articles for those who don’t have a computer Fig.4: if we switch this resonant DC-AC converter at its natural frequency, the inductive and capacitive reactances cancel, and maximum power is transferred to the resistive load. By shifting the frequency above or below the natural frequency, we can control the power to the load. of the square wave. This gain is called the ‘tank gain’. If the switching frequency is a little higher or lower than the natural frequency, the circuit looks a bit inductive or capacitive, respectively. The tank gain falls off either way, and the amount of power transferred to the load reduces. We can therefore control the load power by frequency-­ modulating the drive signal. We can choose to use either ‘above resonance’ or ‘below resonance’ control strategies. We will see how this works in practice later. The graph in Fig.4 suggests that switching occurs at the current zero-crossing, but this is a bit misleading. It is true that the current is near-zero at the time of switching if the switching frequency is precisely aligned with the resonant frequency, but we have already discussed that we will operate at a higher or lower frequency to control the output power. However, it is easy enough to modify this circuit to achieve zero-voltage switching. It just requires the addition of a small capacitor across each switch and a short ‘dead time’ during which both switches are off. This is shown in Fig.5. Here, we are using over-­resonance control, so the LC filter looks inductive and the current lags the voltage by the angle θ. The charts to the right of the figure show the load current (blue) and the voltage across the lower switch, S2 (red). During period A, the upper switch S1 is conducting, so C1 is discharged and C2 is charged to Vsrc. At the beginning of period B, S1 opens while the load current is still positive. Capacitors C1 and C2 take over providing the load current, and the voltage across S2 falls while C1 charges and C2 discharges. Australia's electronics magazine siliconchip.com.au 78 Silicon Chip You can play around with substituting these expressions into each other and get two other useful definitions: Q = ω0L ÷ R and Q = 1 ÷ ω0CR. We can use this information to build a resonant DC-AC converter, as shown in Fig.4. A DC source feeds a half-bridge switch followed by an LC series filter and a resistive load. The end of the load is held at ½Vsrc by the two bypass capacitors. These have a value large enough that their midpoint voltage remains more-or-less constant at the switching frequency. The voltage across the filter and load is therefore a square wave with amplitude ½Vsrc, as shown in the red trace. If we switch the converter at a frequency equal to the damped natural frequency of the filter and load, the load current and voltage will be a relatively pure sinusoid at that frequency. With the switching frequency equal to the natural (resonant) frequency, the inductive and capacitive reactances cancel out, so the load looks resistive and the maximum possible energy is transferred to it. We say that the voltage gain of the resonant tank is unity under these conditions. By this, we mean that the AC voltage across the resistive load (blue) is equal to the amplitude of the fundamental If the capacitor values are chosen such that the period B is large with respect to the (~10 nanosecond) switching time, the voltage across S1 at the time it opens will be effectively zero – C1 will hold the voltage across S1 to zero while it opens. At the start of period C, C1 is fully charged to Vsrc and C2 is fully discharged. The still-positive load current now commutates to the freewheeling diode, D2. At this time, S2 can be closed while the voltage across it is zero. When the load current reverses at the start of period D, S2 is closed, ready to take the load current for the bulk of its negative excursion. At the start of period E, S2 is opened, while C2 holds the voltage across it to zero. The capacitors support the load current until the start of period F, when the freewheeling diode, D1, takes over. This is when S1 is closed, while its drain-source voltage is zero. The upshot of all this is that both switches only ever open or close with zero voltage across them, resulting in very low switching loss. The caveats to this are that the device switch-off time is small compared to the charge/ discharge times of C1 and C2, and that there is enough phase lag that the freewheel diodes are conducting when the switches are on. The former is not such a challenge, since the switching time is short, but the latter means that we cannot operate too close to natural frequency so the filter inductance remains high enough. Resonant DC-AC converters like this are pretty common – for example, most induction cooktops work this way. A typical large domestic induction cooktop contains resonant converters capable of a power output up to 7kW at frequencies in the 20-100kHz range. This would not be practical without zero-voltage switching. Fig.5: with the addition of capacitors across the switches and a short deadtime when both switches are off, we can achieve almost lossless switching. The switching frequency must always be a little above the natural frequency for this to work. Resonant DC-DC converters You could also imagine rectifying and filtering the output of a resonant DC-AC converter, perhaps after passing it through a transformer, to produce a DC output, as in Fig.6. Frequency modulation could be used to control the resulting DC output voltage. We can think of this converter as a series of four blocks, each with its own voltage gain. The product of these gains is the voltage transfer function of the converter: Vl ÷ Vsrc = Gi Gt Gx Gr. siliconchip.com.au Fig.6: a resonant DC-DC converter can be thought of as four distinct blocks, each with its own gain. This simplifies the analysis enormously. Australia's electronics magazine May 2026  79 Calculating some of these gains is easy. The inverter puts out a square wave with a peak-to-peak amplitude of Vsrc, so an amplitude of ½Vsrc. The current is sinusoidal, so only the fundamental component of this voltage can transfer real power. We have seen many times before that the amplitude of the fundamental frequency of a square wave is 4 ÷ π times its amplitude. Since the amplitude is ½Vsrc, the gain through the inverter must be Gi = 2 ÷ π. The gain of the tank is much more complex. I won’t go through the derivation (life is too short as it is), but it can be shown to be the ugly expression under the resonant tank block in Fig.6. The important thing to note is that the tank gain depends on the ratio of the damped-to-undamped natural frequencies and the Q of the tank. We’ll look into this more when we get to an example. The transformer’s voltage gain is trivial to calculate – it is just the turns ratio, as you would expect. Calculating the rectifier’s gain is a bit harder, but not much. Fig.7 shows how. The resonant tank current driving the transformer primary will be sinusoidal, so we can model the transformer’s secondary current as a sinusoidal current source, is, with some amplitude I, which will depend on the primary current and the turns ratio. The waveforms associated with this simplified circuit are shown on its right. If we assume the filter capacitor is large enough to make the voltage ripple negligible and the diodes are ideal, the transformer secondary voltage vs will be a square wave with amplitude Vl. Because is is sinusoidal, only the fundamental component of vs can contribute real power to the load. Again using the relationship for the fundamental of a square wave, the gain of the circuit Vl/vs(1) is π ÷ 4. We also need to work out the equivalent AC resistance of the rectifier and load. This is important because it is this resistance, seen through the transformer, that loads the resonant Fig.7: this diagram shows how we calculate the equivalent AC resistance of the rectifier filter so we can understand the damping seen by the resonant tank. Fig.8: the curves show the tank gain vs normalised frequency for various values of Q. The example in the text operates in the region bounded by the dotted lines and the Q=1 and Q=4 curves. 80 Silicon Chip Australia's electronics magazine tank and determines its damped natural frequency and Q, both of which will affect the tank gain. Dividing vs(1) by the secondary current gives an equivalent AC resistance of the rectifier and filter of R(ac) = (4 ÷ π) × (Vl ÷ I). Expressed in terms of the converter’s power output, R(ac) = (8 ÷ π2) × (Vl2 ÷ P). Noting that the last bracketed term is equal to the load resistance, R(ac) = (8 ÷ π2) × Rl. A practical example We now have all the equations we need to look at a practical design example. There is not enough space here for a comprehensive design exercise, but I want to show how one would approach such a design. Let’s imagine we are building an isolated resonant DC-DC converter to operate from rectified mains and deliver 10V DC at 20A (so 200W) into a resistive load. The input voltage range should be 300-400V to accommodate a range of mains voltages (let’s not worry about supporting 110-120V AC mains just yet). Because we are using the frequency to control the output power, we need to specify a minimum load so the frequency range is bounded at both ends. We will use a minimum load of 5A (50W) for this exercise. We will use above-resonance control with a target switching frequency in the range of 500kHz to 1.5MHz, or thereabouts. I will break the design up into steps. 1. We can start by calculating the maximum and minimum load resistances corresponding to the minimum and maximum output currents: Rl(min) = 0.5W and Rl(max) = 2W. We can also choose an undamped natural frequency at the low end of our desired range, say 600kHz or 3.77 × 106 radians per second. 2. We have to design the transformer turns ratio so we can achieve the desired output voltage when the source voltage is at its minimum. The minimum DC voltage times the inverter gain Gi gives us a minimum input voltage of 191.0Vrms. On the other side of the transformer, the 10V output voltage divided by the rectifier gain Gr tells us that the fundamental of the secondary voltage must be 12.7Vrms. The ratio of these values gives us a transformer gain Gx (secondary to primary turns ratio) of 0.067. We actually need a bit more gain than this because I have neglected the rectifier siliconchip.com.au siliconchip.com.au 11V V(vl) 10V 9V 8V 7V 6V 12V 10V 8V 6V 4V 2V 0V -2V -4V -6V -8V -10V -12V 250μs V(vs1)-V(vs2) diode drops and any other losses. I will therefore use a nice round turns ratio of 0.1 (ten primary turns for every secondary turn). 3. Now we can calculate the required tank gain. This is easy because we know the inverter gain, the transformer gain, the rectifier gain and the required end-to-end voltage gain (Vl/Vsrc). Because we have a range of input voltages, we will also have a range of tank gains. It turns out that the tank gain Gt has to range between 0.5 and 0.67. 4. The last thing we have to do before we can calculate the component values is to work out what the load resistance looks like from the primary side of the transformer. This is the resistance that will load the resonant circuit. We saw from the analysis of the rectifier that the secondary-side AC resistance of the load is (8 ÷ π2) × Rl. This transforms our 0.5W and 2W minimum and maximum load resistances to 0.405W and 1.62W respectively. We then have to reflect these resistances through the transformer ratio by multiplying them by (N1 ÷ N2)2, which just means multiplying them by 100 in our case. The effective resistance loading the tank is therefore in the range of 40.5W to 162W. 5. We calculate the resonant tank component values based on the Q. The minimum Q occurs when damping is highest and the resistance is at its maximum, corresponding to light loading on the converter. We can just choose the minimum Q to be 1 and calculate the resonant inductor from Q = (ω0L) ÷ R. Rearranging to make L the subject and plugging in the other values (ω0 = 3.77 × 106 radians per second and R = 162W) gives an inductance of 43.0µH. We can then calculate C from the relationship ω0 = 1 ÷ √LC to give 1.63nF. 6. Finally, we can calculate the maximum Q, which occurs when the load is heaviest and the resistance load on the tank is lowest. We can use the same Q = (ω0L) ÷ R formula, this time plugging in the inductance we just calculated and the 40.5W minimum resistance. This gives us a maximum Q of 4, which is not unreasonably high. 7. You could use the ugly formula for tank gain in Fig.6 to calculate what this means for the damped natural frequency, but it is probably easier to follow if you look at the graph in Fig.8. This plots the tank gain vs the normalised frequency (the ratio of 251μs 252μs 253μs 254μs 255μs 256μs 257μs 258μs 259μs 260μs 261μs 262μs 263μs 264μs 265μs 266μs 267μs 268μs 269μs 270μs Fig.9: this simulation of the example resonant DC-DC converter agrees with the calculations. The upper green trace is the output voltage and the lower mauve one is the transformer secondary voltage. damped natural frequency to the natural frequency) for various values of Q. Our converter will operate in the region bounded by the two horizontal dotted lines (tank gain of 0.5 to 0.67) and the curves corresponding to Q=4 (purple) and Q=1 (blue/cyan). The tank gains correspond to the range of input voltage and the Q values correspond to the load resistance range. We can then read off the minimum and maximum normalised frequencies from the horizontal axis. I have marked these points with large dots. In this example, we expect the resonant frequency to range from 1.15ω0 to 2.1ω0. This corresponds to a frequency range of 690kHz to 1.24MHz. Results I find this type of graph very intuitive. The lowest switching frequency corresponds to a heavy load, low input voltage scenario. The highest switching frequency corresponds to the lightest load and highest input voltage scenario. You can see now why we have to set a minimum load – the switching frequency will go through the stratosphere if the load resistance gets too high. I could not resist simulating this circuit, as shown in Fig.9. The inverter block on the left just contains a behavioural voltage source that produces a 50% duty cycle square wave with the frequency and amplitude specified on the front. The resonant Australia's electronics magazine tank and transformer are obvious, and the rectifier block consists of a full-bridge of ideal diodes and a 10µF capacitor. The simulation run below the schematic was at the highest load, lowest input voltage operating point. The results are a bit unspectacular, with the DC output voltage in green and the transformer secondary voltage in purple. However, it does confirm that this switching frequency is roughly correct to achieve the output voltage we desire. There is obviously a lot more to designing a resonant converter, especially one at this power level. In fact, this article has just given a small introduction to resonant and soft switching converters; there are countless variations out there, including some quite novel and interesting circuits. Conclusion This article concludes our series on power electronics. We have covered a lot of ground, including DC-DC, AC-DC and DC-AC converters. We have touched on control systems, magnetics and EMI filtering, and with this article, resonant converters. As I stated at the outset, this series was not meant to be a university-style course on power electronics. Rather, I hope I have provided some insights and a few tools and techniques that may be useful in exploring this endSC lessly fascinating topic. May 2026  81