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By Andrew Levido Power Electronics Part 2: Controlling DC-DC Converters Last month, we introduced average value analysis and used it to analyse a range of DC-DC converter topologies at a high level. We then looked at a practical example of a buck converter. This time, we will delve into the control systems required to make these converters work correctly. D C-DC converters almost always operate in a closed-loop mode, where some kind of feedback is used to maintain the output voltage at the desired level, despite changes in load or source voltage. Often, the detail of the control loop is hidden from the user because it is incorporated in the driver chip, such as was the case for our buck converter example last month. Even when this is the case, it is handy to have at least a basic understanding of how they work. We will continue using the example of the buck converter we introduced last time. It was designed to convert a nominal 12V input (ranging from 10V to 14V) to a 6V output, to drive a 10W load for a maximum output current of 600mA. The switching frequency was 500kHz. We went through the process of selecting the filter components in some detail. If you want to know why we need to close the loop around our converter, take a look at Fig.1. This is the result of a simulation of the converter with no feedback and a fixed 50% duty cycle. The source voltage (blue trace) is programmed to be 12V for the first 30ms, dropping to 10V thereafter. In contrast, the load is programmed to be 10W for the first 10ms, increasing to 20W thereafter, with the resulting load current shown by the orange trace. The purple trace shows the output voltage. There is a significant transient when the load changes, but no change in output voltage, since the duty cycle is fixed. The transient peaks at about ±300mV, which is not great, and it takes about 5ms to settle. Things get even worse when the input voltage reduces at the 30ms mark. Not only does the output voltage drop because there is no regulation, but the ringing at the transition is horrendous. Again, it takes about 5ms for the result to settle into something close to the steady state value. A properly designed closed-loop control system should greatly reduce or eliminate these problems. Control theory is a huge topic, and one that can be very heavy on mathematics. I will therefore not be giving a control theory tutorial in the classical sense, but rather a practical exploration of some of the techniques that can be employed. If you are a control theory expert, you are hereby warned that I am going to skip some details in the interest of space and simplicity! Creating a mathematical model Fig.1: without a closed loop control system, the output of the DC-DC converter (purple trace) is unstable with changes in load (at 10ms) and input voltage (at 30ms). To create a stable and effective control system, we have to build a mathematical model to describe our DC-DC converter under dynamic conditions. We have already discussed two models for our converter: the very high-level periodic steady state (PSS) model we used for average value analysis, and the very low-level cycle-by-cycle simulation model we used to verify the ripple voltages and currents. We can’t use the periodic steadystate model for the control loop since it is dynamic behaviour we want to take care of. Also, we don’t need to model the cycle-by-cycle behaviour of the converter since the behaviour we are concerned with occurs over much longer time periods than a single 2µs cycle. Instead, we need an intermediate model. Fig.2 shows the block diagram of our converter with feedback presented in the classic control theory manner. Right in the middle is the modulator, which takes a control voltage proportional to the duty cycle (vc) and produces the switching waveform, whose average value, ‹vx›, is applied to the filter. The filter takes this voltage and produces the smoothed output voltage, vo. Each block has a gain, G, which relates its output signal to its input. Australia's electronics magazine siliconchip.com.au 30 Silicon Chip In front of these two blocks is Fig.2: this classic a compensator, which we will depiction of the describe in more detail below. DC-DC converter The input to the compensator is closed-loop an error, e, that is the difference system is useful between the reference setpoint vr to understand and the feedback signal vfb. The the circuit feedback signal is derived from the blocks we need output voltage we want to control to model. by some sensor, with a gain of H. Fig.3: the DCThese blocks are shown in a DC converter more familiar way in Fig.3. The arranged modulator includes the Mosfet and according to the diode switches, plus the circuitry block diagram that converts a control voltage to in Fig.2 is the pulse-width-modulation to drive starting point for the Mosfet. At its simplest, this is the development just a comparator with an output of a control that is high whenever the control model of the voltage exceeds a ramp waveform converter. The compensator is at the switching frequency. the missing piece The modulator therefore takes a of the puzzle at control voltage, vc, and produces this stage. the average voltage, ‹vx›. The modulator has a gain of Gm and it is easy to see that this must be the unitless negative input for the feedback. This quantity Gm = Vsrc/Vramp. If we assume anticipates that the compensator will the ramp voltage is 1V, the modulator probably involve op amps. gain simplifies to the source voltage, Simplifying the complexwhich is 12 in our example. It is worth noting that there is no frequency domain need for any switching to occur in this Describing the filter and compenmodel of the modulator. The modu- sator gains requires us to dip our toes lator produces an output equal to the into something called the complex-­ average voltage over one switching frequency domain, also known as the period. This voltage may vary with s-domain. Analysis of the behaviour time, but the time scale we are con- of capacitors and inductors involves cerned about is much longer than the differential equations, which we usu2µs switching period. ally describe in the time domain – for Because this modulator controls the example, the relationship between average voltage applied to the filter, voltage and current in an inductor is this converter is said to be employ- v = L di/dt. ing voltage mode control. There is We can describe the same equations another way to do it, which we will in the s-domain, which makes the come to later. mathematics much simpler, because The sensor gain is trivial to calcu- differentiation is reduced to multilate. It is simply the divider ratio rep- plication and integration is reduced resented by the two resistors, so Hs = to division. The conversion from the R1 ÷ (R1 + R2), or 0.204 in this case. time domain to the s-domain requires The buffer is there to isolate the com- something called a Laplace transform. pensator from the divider. You don’t need to know how to do We will ignore the compensator for this (unless you are an electrical engithe moment, but notice that I have neering student) because you can write absorbed the error summing junc- the s-domain expression for most comtion into the black box and added a mon components very easily without positive input for the reference and a having to do any maths. Table 1 – passive component complex impedances Component Time Domain s-Domain Complex Impedance Z(s) Inductor v = L di/dt v = iLs Ls Capacitor i = C dv/dt i = vCs 1/Cs Resistor v = Ri v = ir R siliconchip.com.au Australia's electronics magazine The “s” in s-domain is a complex frequency, which is just a way of describing a unit-amplitude sinewave with a given frequency and phase. We won’t, however, have to deal with any complex numbers in this explanation – we can simply treat s like any other algebraic variable. To transform the inductor mentioned above to the s-domain, the time differential (d/dt) is simply replaced by s to get the s-domain equivalent relationship v = i • L • s, which I hope you can see is kind of analogous to Ohm’s law. The complex impedance of the inductor, indicated by Z(s), is therefore simply Ls. Using a similar logic, we can arrive at the s-domain expressions for the voltage/current relationships of common parts, and hence their complex impedances, shown in Table 1. To show just how useful this transformation is, we will use these complex impedances to calculate the transfer function of a simple RC low-pass filter shown at the top of Fig.4. If you substitute in the complex impedances from the table and use the normal voltage divider equation, you get the s-domain transfer function 1 ÷ (RCs + 1) after a little bit of algebraic manipulation. It’s that easy. Poles and zeros You can see that there must be a particular value of complex frequency s that makes the denominator of the December 2025  31 expression equal zero, and therefore the transfer function becomes undefined (but very large). This value, s = -1 ÷ (RC), is called a “pole” because you can visualise it as a spike rising to infinity on the two-dimensional s-plane. The complex frequency domain uses radians per second as the unit of frequency, but converting to Hertz (via the relationship that one cycle is 2π radians), this pole is at a frequency of 1 ÷ (2πRC)Hz. This should be familiar as the corner frequency of an RC filter. If we turn to the RC high-pass filter at the bottom of Fig.4 and go through the same process, we arrive at the s-­ domain transfer function RCs ÷ (RCs + 1). This too has a single pole, at –1 ÷ RC, but the s in the numerator means there is also a value of s where the numerator of the fraction becomes zero, so the transfer function is equal to zero. It may come as no surprise to know that this is called a “zero”. In this case, the zero occurs at s = 0, so the LC highpass filter has a transfer function with one pole at 1 ÷ (2πRC) and one zero at the origin. By origin, we really mean the origin of the s-plane, but you can think of this zero as being at “0Hz”. So, you can easily work out the poles & zeroes of any network by calculating the transfer function in the s-domain as a fraction. Poles are the values of s (frequency) when the denominator is zero, and zeroes are the values of s when the numerator is zero. Poles & zeros have a specific meaning in the frequency domain. When a signal encounters a pole, the slope of the gain reduces by −20dB/decade and the phase shifts by −90°. Conversely, when a signal encounters a zero, the slope of its gain increases by 20dB/ decade and the phase shifts by +90°. Fig.5 shows this in action for the two filters we just analysed. In the case of the low-pass filter, the signal is unattenuated and has a phase shift of zero until it encounters the pole at which point it turns down to a slope of −20dB per decade. At the same time, the phase shifts by −90°. Fig.4: finding the s-domain transfer functions for these filters is as simple as substituting the expressions from Table 1 into the voltage divider equation and performing some elementary algebra. In the case of the high-pass filter, the zero at the origin means that the gain is increasing by +20dB per decade from ‘zero’ and the phase is already shifted by +90°. When the pole is encountered, the −20dB/decade shift puts the gain back to flat, and the −90° shift brings the phase back to zero. In practice, this means that you can work out the transfer function, the pole and zero locations and therefore the gain/phase versus frequency characteristic of any network of resistors, capacitors and inductors with a bit of high-school algebra. No wonder engineers like the s-domain. Thanks, Monsieur Laplace! Buck converter output filter Armed with this new knowledge, we are ready to work out the transfer function, Gf, of the buck converter’s output filter to fill out our control system model. This is shown on the lefthand side of Fig.6. If you have a go at this yourself, you will see I have made a small approximation in the denominator, where an RCs term is dropped because it is very much smaller that the dominant RLs2 term. This kind of simplification is common in complex frequency analysis, so watch out for them. The resulting transfer function has an s2 term in the denominator. This signifies that the transfer function has two poles; in this case, both are at 1 ÷ (2π√LC). This means the roll-off at this frequency is −40dB/decade, and the phase shifts by −180°. There is also one zero at 1 ÷ 2πRC due to the ESR of the of the capacitance. This pulls the gain back up to −20dB/ decade and the phase back up to −90°. This double-pole is a problem for our converter. Gain ‘peaking’, like that shown dotted due to the Q of the LC filter, and the rapid phase transition can cause instability like the ringing we saw in Fig.1. If we compare this plot to the simulation on the righthand side of Fig.6, you can see that the peaking extends to about 15dB, which is potentially quite serious. Designing a compensator Fig.5: the poles and zeros obtained from the s-domain transfer functions in Fig.4 can be easily transferred to the frequency response plots. A pole introduces a −20dB/decade slope change and a −90° phase shift. A zero 32introduces Silicon Chip Australia's electronics a +20dB/decade slope change and a +90° phase shift. magazine Finally, we come to the design of the compensator. There are several ways to go about this, but they all come down to manipulating the poles and zeros of the closed-loop transfer function. Their number, position and relationship can be tweaked to ensure the siliconchip.com.au Fig.6: the DC-DC converter output filter has two poles at a frequency determined by the inductance and capacitance, and a zero at the frequency of the capacitance and its ESR. The resulting frequency response contains a nasty peak & steep phase shift responsible for the ringing in Fig.1. Fig.7: we create a compensator characteristic (▪) to transform the filter response into the dominant pole characteristic (▪). The compensator requires two poles & two zeroes. system is stable and to optimise the transient response. For example, if we are most worried about overshoot, we can set up a highly damped system that will eliminate it at the expense of response time and settling time. On the other hand, we might be concerned about getting to the new voltage quickly, and can therefore tolerate a bit of overshoot. I’m not going to dig into all of that here. Instead, I will demonstrate a simple technique called dominant-pole compensation that focuses on the open-loop poles and zeros. This is the same technique used to ensure op amps are stable in closed-loop applications. The aim is to make the open-loop frequency response look like a single-­ pole filter that rolls off the gain at a steady −20dB/decade until it reaches 0dB at some crossover frequency, fc. This roll-off is required to ensure the gain drops to unity well before the phase shift reaches −180°. The difference between the phase shift at the crossover frequency and −180° is the ‘phase margin’, a measure of the stability of the circuit and its tolerance to external disturbances. We can achieve this roll-off by adding a compensator with the characteristics shown in Fig.7. The modulator siliconchip.com.au and the sensor gains are not frequency-­ dependent, so they don’t impact the shape of the gain/frequency characteristic of the open-loop converter, and can be ignored. They do impact the absolute value of the gain, but we are not concerned with that here. If we want to transform the filter gain/frequency characteristic (in red) into the dominant pole characteristic in blue, we require the compensator to have the green characteristic. It should have a pole at the origin, to set the roll-off to −20dB/decade. We then need two zeroes at the corner frequency of the LC filter to cancel the double-pole in the filter response. The Fig.8: this Type III compensator has the necessary poles and zeroes. The transfer function is calculated in exactly the same way as for the filter; the component values are discussed in the text. Australia's electronics magazine compensator should have another pole at the frequency of the output capacitance/ESR zero to cancel the corresponding zero in the filter. So in total, we need a compensator with two zeroes and two poles, one of which is at the origin. This is known as a Type III compensator, and a suitable circuit is shown in Fig.8. The reference voltage is applied to the non-inverting input of the op amp, and the feedback signal is applied to the inverting input via R3/C3. You can work out the compensator’s transfer function in the s-domain in exactly the same way as we did for the filter. This time, we just assume that vr is zero, and use the usual equation for the gain of an inverting amplifier: G = −Zf /Zi, where Zf is the impedance of C2 in parallel with R1 plus C1, and Zi is the impedance of R3 in parallel with C3. The resulting transfer function (again with a minor simplification) is shown below the circuit diagram. There are two zeros, one formed by R1C1 and one by R3C3, and two poles, one at the origin and one formed by R1C2. The component values shown are calculated by setting the frequency of both zeroes, 1 ÷ (2πR1C1) and 1 ÷ (2πR3C3), to be the same as the LC December 2025  33 seems likely the chip uses a similar compensator internally. Current-mode control Fig.9: compare this closed-loop response to that of Fig.1. The disturbances when the load or supply voltage change are much smaller and settle much faster. The lower graph shows the open loop gain and phase with the compensator included. Contrast this with the filter characteristic in Fig.6. filter’s 1 ÷ (2π√LC), which is 1.56kHz. I chose 100nF and 1kW for nice, round values. The non-origin pole at 1 ÷ (2πR1C2) should be at the same frequency as the zero formed by the output capacitor and its ESR (20.4kHz). Since we have already chosen R1, we can calculate C2 to be 7.8nF. This is not a standard value, so I used 8.2nF, the nearest one. This small error won’t make a huge difference, since the values for output capacitance and ESR we are using (102.4µF and 76mW) are hardly precision values themselves. Simulation I simulated this control circuit to see how it will perform. The result is shown at the top of Fig.9. The stimulus is exactly the same as for Fig.1 – the load resistance changes from 10W to 20W at the 10ms mark, and the source 34 Silicon Chip voltage drops from 12V to 10V at the 30ms mark. The difference is dramatic. There is just a small blip at the 10ms mark, which peaks at about +20mV (+0.3%), and lasts for just 150µs. At the 30ms mark, the voltage dips about 130mV when the input changes, but it recovers without overshoot in around 600µs. I ran a second simulation to plot the open-loop gain of the entire circuit, which is shown at the bottom of Fig.9. While you can clearly see the expected -20dB/decade roll-off from 100Hz to 100kHz, a small amount of gain peaking is still visible, but it is much less pronounced. The simulation also calculates the crossover frequency, which is 4.36kHz, and the phase margin, which is 66°. You may recall that the crossover frequency we calculated from the TPS5410 data sheet was 4.5kHz, so it Australia's electronics magazine We mentioned above that there is a second type of modulator that can be used in DC-DC converters. This is known as current-mode control, and it is shown in Fig.10. In this case, the modulator controls the average current through the inductor, ‹il›, instead of the average voltage at the filter input. At the beginning of every switching period T, the latch is set, so the Mosfet switches on and the inductor current begins to increase. This current is monitored by a current sensor, usually a resistor, and the resulting voltage is compared to the control voltage, vc. When the current reaches the level defined by the control voltage, the latch is reset and the Mosfet switches off until the next cycle. The result is that the peak current is determined by the control voltage and the value of the sense resistor. If the current ripple is small, this turns out to be a reasonable approximation to the average current. This approximation is not perfect, so most real-life implementations use something called slope compensation to avoid a potential instability at very high duty cycles. This is not relevant for the discussion below, so I will not go into it here. Editor’s note: see the LED Dazzler project (February 2011; siliconchip. au/Article/899) for a practical implementation of slope compensation in a switch-mode regulator. The transfer function of a current mode modulator is therefore approximated by Gm = 1 ÷ Rsense. Note that this gain is a transconductance (a voltage to current conversion). Because the output of the modulator is now a current, we have to revisit the transfer function of the output filter and the compensator, since the filter is no longer the voltage divider we modelled earlier. Fig.11 shows the calculation of the filter transfer function, which is performed in exactly the same way as before. What is different is that the inductor is effectively irrelevant, since the modulator current passes through it (you can think of the inductor as part of the modulator if that helps). The output voltage is now dependent on the impedance of the filter capacitor, including its ESR, and the impedance of the load. The upshot of this is that the transfer siliconchip.com.au function is simpler, with a single pole at a frequency dependent on the output capacitance and the load resistance, and a zero at the frequency related to the capacitance and its ESR, like before. It follows that our compensator can be simpler, as it now needs only two poles and one zero, as shown at the bottom of Fig.11. This is known as a Type II compensator, and an example is shown in Fig.12. The component values of R1 & C1 are calculated so that the frequency of the zero (1 ÷ 2πR1C1) is the same as the zero formed by the output capacitor and the load, at 1 ÷ 2πRloadC, which is 156Hz. The pole at 1 ÷ 2πR1C2 should be at the same frequency as the zero formed by the output capacitor and its ESR (20.4kHz). Given that R1 is 10kW, the closest standard capacitor value comes out to be 820pF. The value of R3 should be very low compared to R1, and can even be zero. I simulated this converter as well, although in this case, a change in input voltage was not modelled. Fig.14 on page 36 shows the results with a much magnified scale. The peak excursion and recovery time are very similar to the voltage mode controller, as we would expect. Discontinuous current Before we finish with control theory for now, we have to cover one more topic. So far, we have assumed that the current through the converter is continuous. That is, we have assumed the peak-to-peak current is small compared to the average. But what happens as the average inductor drops to the point it is close to the peak-topeak ripple? Fig.13 shows our old friend, the buck converter, where we have plotted the inductor current and the voltage vx that we have used in all of our analyses. On the left is the case when the inductor current is high enough that the negative excursion of the (exaggerated) current ripple remains positive. This is known as the continuous current case, and has been the assumption we have used to derive the modulator models for both voltage mode and current mode examples above. We could, however, imagine a situation when the load and therefore inductor current reduces to the point that the inductor current ramps down siliconchip.com.au Fig.10: a current-mode modulator controls the average inductor current instead of the average voltage as in Fig.3. This change flows on to the filter and compensator transfer functions. Fig.11: the current-mode filter transfer function is simpler, with just one pole set by the capacitor and the load resistance and one zero due to the capacitor and its ESR. The compensator therefore only needs two poles and one zero. Fig.12: this Type II compensator has the requisite poles (one at the origin) and one zero to compensate the current-mode controller. See the text for the component values. Fig.13: discontinuous mode occurs when the current reaches zero before the end of the switching period. This changes the modulator transfer function, and thus the compensator is required for optimum performance. Australia's electronics magazine December 2025  35 Fig.14: the resulting closed-loop response to a load change is similar to that of the voltage mode controller (albeit with a different scale). Silicon Chip kcaBBack Issues $10.00 + post $11.50 + post $12.50 + post $13.00 + post $14.00 + post January 1997 to October 2021 November 2021 to September 2023 October 2023 to September 2024 October 2024 onwards September 2025 onwards All back issues after February 2015 are in stock, while most from January 1997 to December 2014 are available. For a full list of all available issues, visit: siliconchip.com. au/Shop/2 PDF versions are available for all issues at siliconchip.com.au/Shop/12 We also sell photocopies of individual articles for those who don’t have a computer Compact HiFi Headphone Amplifier Complete Kit SC6885: $70 December 2024 & January 2025 siliconchip.au/Series/432 This kit includes everything required to build the Compact HiFi Headphone Amplifier. The case is included, but you will need your own power supply. 36 Silicon Chip Australia's electronics magazine to zero at some time (Zt) before the end of the switching period, as shown on the right. This is known as discontinuous current operation. When the inductor current falls to zero, the inductor voltage must also be zero, so the point vx will be at the output voltage, Vload. It’s pretty easy to see that the modulator transfer function will not be the same as for the continuous conduction case. The fact that the transfer function changes in discontinuous mode has implications for our control loop. You can design an optimised control loop for a switching converter operating in either mode, but compromises are required if the converter will operate in both modes. Converters are therefore generally designed to work in one mode or the other. High-power converters usually use continuous current mode, and thus have a specified minimum output current. Low power converters (say, ≤50W) often operate exclusively in discontinuous current mode. Of course, depending on what you are powering, it may be necessary to operate in both modes, in which case compromises much be made to ensure stability while keeping reasonably good load and line regulation. Conclusion Whew! This has been a pretty heavy article, but I think it is important to have a basic understanding of the principles of control theory as applied to DC-DC converters. You may never have to completely design a compensator from scratch, as the manufacturers do a lot of the heavy lifting for us, but it is important to understand what’s going on for those occasions when things don’t go to plan. At the very least, we have added yet another tool to our growing set of ways to look at and understand power electronics systems. As the number of models at our disposal grows, I am reminded of the saying, “all models are wrong, but some models are useful”. Knowing just which model or tool to use in what circumstance is the mark of a true expert, and comes only with experience. Next time, we will look at isolated DC-DC converters and reverse-­ engineer a commercial converter to see what we can learn from the proSC fessionals. siliconchip.com.au