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Image source: https://pixabay.com/photos/intel-8008-cpu-old-processor-3259173/ T o r y of t s i h he intel Pa rt 2 b y D r D avid Mad K3D V , n o d is SM The second in a three-part series on Intel, this article concentrates on its projects, manufacturing and events from the early 1990s to the present. Last month’s article gave an overview of the company and its background, plus a detailed history from its early days to the late 1980s. T his article will end with the events of the last few years from Intel’s perspective; the third and final part in this series next month will then look at the technologies they are currently pursuing and what the future may hold. 1990s: PC market dominance In the 1990s, Intel became a household name, partly because of the popularisation of the PC and the “Intel Inside” marketing campaign that started in 1991. This led it to become the most valuable semiconductor company in the world by 1995. “Intel Inside” brought, for the first time, brand recognition of computer components such as CPUs in consumer devices. It also brought billions of dollars of licensing revenue to Intel; Intel co-marketed their CPUs with manufacturers, leading to advantages for both parties. This strategy was quite different from competitors AMD and Cyrix, whose combined market share was around 10-15%, while Intel held The rise and fall of Intel’s value Intel became the most valuable semiconductor company in the world around 1995, a position it held until around 2011. After that, it experienced a period of decline, and was surpassed in sales by Samsung by 2017. It has since been surpassed in market capitalisation by companies like TSMC and NVIDIA. By 2022, AMD surpassed Intel’s market capitalisation. Presently, Intel has just under half of the desktop CPU market, with the other half being AMD CPUs. AMD has been gaining significant market share of late and has made major inroads in the server market, currently capturing around 25% of the highly profitable server CPU market. So Intel remains dominant for the moment, but AMD is now undoubtedly a serious competitive threat to them. 16 Silicon Chip Australia's electronics magazine around 90% of the market. Nowadays Intel doesn’t have as much of a hold on the market (see the panel below). The Pentium The original Pentium processor was released in 1993 as a successor to the 80486 and remained the brand name for Intel’s premium processors until the Core lineup was introduced in 2006. After that, it became the brand for a more affordable line of processors than the Core series. These later Pentiums were discontinued in 2023 and had little commonality with the original except for using the x86 instruction set. The original 1993-2001 Pentium contained 3.1-4.5 million transistors depending on the variant. It was the first Intel processor to use a ‘superscalar architecture’, a form of processor parallelism in which more than one instruction can be executed per clock cycle – see Figs.24 & 25. This is done by simultaneously sending instructions to more than one execution unit within the processor. siliconchip.com.au Intel Pentium Microarchitecture Branch Target Buffer Prefetch Address TLB Fig.24: the Intel Pentium architecture. Source: https://w.wiki/ GZY5 (CC BY-SA 3.0) Code Cache 8 KBytes Branch Verif. & Target Addr. 256 64 Bit Data Bus 32 Bit Address Bus Instruction Pointer Control ROM Instruction Decode Control Unit Address Generate (U Pipeline) Page Unit Bus Unit Prefetch Buffers Floating Point Unit Address Generate (Y Pipeline) Control Register File Control Integer Register File ALU (U Pipeline) 64 64 Bit Data Bus Barrel Shifter 32 32 Bit Address Bus Superscalar vs pipelining Early processors handled instructions one at a time. Each instruction went through a sequence of steps: fetch the instruction from memory, decode it, fetch any required data, execute the operation and write the result back to registers or memory. The CPU could not begin the next siliconchip.com.au Divide 32 32 32 32 This is different from the ‘pipelining’ of the 80386 and 80486, which split instructions up into stages so that they could be executed sequentially without interruption. A later variant of the Pentium added the MMX (Multimedia eXtensions) instruction set, which introduced SIMD (single instruction, multiple data) operations on packed integers – see Fig.26. While not capable of accelerating floating-point workloads, MMX significantly improved performance in multimedia and DSP tasks such as image filtering, video decoding (DCT/ IDCT), audio processing and colour space conversion. Add ALU (Y Pipeline) TLB Data Cache 32 8 KBytes 32 instruction until this entire sequence finished. Any delay – for example, waiting for a value to arrive from memory – stalled the whole processor. Pipelining improves this by dividing the instruction cycle into separate stages. Different instructions can occupy different pipeline stages at the same time; while one instruction is being decoded, another can be fetched, another executed and so on. A non-pipelined CPU must wait for one stage to finish before the next can start, so it can’t take advantage of hardware parallelism like a pipelined CPU can. Once the pipeline is full, the processor can complete one instruction per clock cycle, improving throughput dramatically. A stall in one stage (eg, waiting for memory) still prevents earlier stages from progressing, so the pipeline as a whole does pause. However, stages ahead of the stall continue to finish their in-flight instructions, and the pipeline quickly resumes once the data arrives. Australia's electronics magazine 80 80 Multiply Fig.25: an original Intel Pentium die. Source: https://w.wiki/GZY3 (CC BYSA 3.0) Fig.26: a 166MHz Pentium MMX CPU de-lidded. Source: https://w.wiki/GZY6 March 2026  17 The more advanced ‘superscalar architecture’ allows multiple instructions (or parts of different instructions) to be issued and executed in parallel in the same clock cycle using multiple execution units. A superscalar CPU usually has multiple ALUs (arithmetic logic units) and FPUs (floating point units). In more advanced CPUs with out-oforder execution, independent instructions can continue to execute while the pipeline waits for data, allowing multiple kinds of delays to overlap. Pentium Pro The Pentium Pro was introduced in 1995 and discontinued in 1998. It was the first processor with Intel’s P6 microarchitecture. It had “Dynamic Execution”, which permitted outof-order execution of instructions to improve efficiency, and an integrated L2 cache on a separate die within the processor module connected via a dedicated 64-bit bus so it could operate at the same speed as the processor. L1 cache is the fastest memory available to the process other than registers. It is usually small, integrated into the die (starting with the 80486) and mainly holds instruction code for frequently executed routines and data that’s frequently accessed. L2 cache is a slower, larger memory that’s still significantly faster than main memory and is used to hold instructions and data that still need to be accessed frequently, but will not fit within the smaller L1 cache. Later processors introduced another layer, L3 cache, again larger and slower (but still faster than accessing main memory). The Pentium Pro/P6 also allowed speculative execution, allowing it to predict the result of instructions ahead of time, to keep the processor pipeline full. It was mainly aimed at servers and high-end workstations. It had 5.5 million transistors and was made on a 500nm process, later reduced to 350nm. Pentium II The Pentium II was introduced in 1997. It kept the P6 microarchitecture introduced on the Pentium Pro but added the MMX instruction set that was missing from the Pentium Pro. It had 7.5 million transistors, except for the Dixon variant with a large amount of cache, which had 27.4 million. It was built on a 350nm process, reduced to 180nm for later variants. Its distinguishing features were its availability in a Slot 1 cartridge format, with L2 cache on a separate circuit board within the cartridge – see Fig.27. Unlike the Pentium Pro, that cache only ran at half the speed of the CPU to reduce cost (and because the Pentium II was generally clocked higher than the Pentium Pro). StrongARM As mentioned last month, Intel acquired the rights to DEC’s Strong­ ARM processor design as part of a legal settlement. They produced it from 1997 until 2004. It was the predecessor to Intel’s XScale chip (2002-2006). Celeron As with many Intel product names, Celeron can be confusing. It was originally introduced in 1998 as a lower-­ cost Pentium II with no L2 cache (early variants were famously overclockable as it was usually the L2 cache that limited the processor speed). It was discontinued in 2002. After that, there was a variety of different Celerons, unrelated to the original and ultimately discontinued in 2023. There are too many versions of Celerons to list. However, throughout their history, virtually all Celeron-branded processors have been lower-­ c ost, performance-­ reduced derivatives of existing Core or Pentium chips. The reduced performance was typically achieved through some combination of smaller caches, disabled cores or core modules, locked multipliers, lower clock speeds, missing features (hyperthreading, Turbo Boost, AVX instructions), or the use of partially defective dies that could not meet the speed of the full-specification parts. Hyperthreading is a now-common technique where one CPU core can execute two different instruction streams, sharing the same execution units but with separate pipelines. Its main benefit is that if one hyperthread pipeline stalls due to something like a memory access, the other can continue running, meaning the execution units don’t sit idle. It was introduced with the Pentium 4. Fig.27: a Pentium II CPU installed on a motherboard. Note how it’s plugged in vertically to an edge connector, similar to the RAM sticks near it, and how the heatsink and fan are integrated into the package. Source: https://w.wiki/GZXv (CC BY 4.0) Xeon Xeon processors were introduced in 1998, intended for high-end non-­ consumer workstation, server and embedded applications. They are based on the same cores as desktop CPUs, but have added specialised features such as support for ECC (error correction code) memory, higher numbers of cores, more PCI Express I/O lanes, support for larger amounts of RAM and larger cache memory. Australia's electronics magazine siliconchip.com.au 18 Silicon Chip They may also have extra RAS (reliability, availability and serviceability) features, enabling them to continue to execute code when a normal processor cannot. Xeon motherboards were also usually available with more sockets than regular desktop CPU boards. They are not generally suitable for desktop or consumer use as they have lower clock rates (due to an emphasis on parallel tasking); they usually lack an onboard GPU (graphics processing unit); and earlier Xeon models lacked support for overclocking. Nevertheless, they were used by some desktop users for some specialised tasks such as video editing. Just as Celerons are lower-tier versions of standard processors, Xeons are almost the opposite, being more-or-less higher-­tier versions of the standard processors. Xeons are still in production using the latest cores. Like Celerons, there are too many models to list here. Fig.28: a Pentium III without its heatsink; this generation of processor came on a plug-in card with separate cache SRAM chips (on the right of the core die). Source: https://w.wiki/GZXt (CC BY-SA 3.0) Pentium III The Pentium III was introduced in 1999 and discontinued in 2004 – see Figs.28 & 29. It introduced Streaming SIMD Extensions (SSE), similar to MMX but supporting parallel floating-point operations, leading to a major boost in multimedia performance. A controversial feature that was introduced was a processor serial number, which raised privacy concerns. There were several Pentium III variants with significant differences between them, such as cache size, manufacturing process and clock speed. Katmai used a 250nm process node with 9.5 million transistors; Coppermine, 180nm with 28 million transistors; and Tualatin, 130nm with 47 million transistors. 2000s: Higher clock speeds, challenges, diversification During the 2000s, Intel had an obsession with improving performance via higher and higher clock speeds. This led to the “NetBurst” microarchitecture, which proved challenging and was ultimately unsuccessful, giving way to the entirely new Core microarchitecture. During the early 2000s, the Pentium 4 dominated in PCs, but there was strong price and performance competition from the AMD Athlon series. The Intel Core 2 Duo was introduced in 2006, becoming a performance leader. However, in 2005, AMD introduced siliconchip.com.au Fig.29: a die photo of the Pentium III showing the significantly increased complexity you’d expect with around 40 million transistors. Source: https://w. wiki/GZXu the Athlon 64 X2 dual-core processor, which provided significant competition. Intel faced several major challenges during the 2000s: ● a series of antitrust actions alleging anti-competitive behaviour toward Australia's electronics magazine AMD, including a US lawsuit and fine (active from 2005 to 2010), and similar cases in Japan (2005), South Korea (2008) and the EU (2009, which was partly annulled much later) ● the need to abandon the failing March 2026  19 Table 4: Intel CEOs over the years CEO Years as CEO Background Robert Noyce 1968-1975 Co-founder of Intel; one of the pioneers of the IC. Gordon Moore 1975-1987 Co-founder of Intel and author of “Moore’s Law”; steered Intel during its early growth and increasing focus on microprocessors. Andrew Grove 1987-1998 An early employee (3rd at Intel), previously company president; he led Intel through a transition away from memory (DRAM) toward microprocessors. Craig R. Barrett 1998-2005 Under his leadership, Intel invested heavily in manufacturing and scaling production, maintaining its manufacturing lead. Paul Otellini 2005-2013 First Intel CEO without an engineering background (he held an MBA). Oversaw an era of diversification, cloud and data-centre growth, and global expansion. Brian Krzanich 2013-2018 Long-time Intel engineer who rose through the ranks; became CEO to steer Intel through manufacturing and product-strategy challenges. Bob Swan 2019-2021 Former CFO (and interim CEO) of Intel. Led the company during a turbulent transitional period, trying to stabilise finances amid increasing competition and industry shifts. Pat Gelsinger 2021-2024 Veteran of Intel (early engineer and later CTO), returning to lead an attempted turnaround. Focused on reviving manufacturing strength, launching new fabs, and repositioning Intel for cloud, AI, and foundry services. Lip-Bu Tan 2025-present BSc in Physics, Master’s in Nuclear Engineering and an MBA. Former CEO of Cadence. Faces major challenges after Intel has lost significant market share and market cap. NetBurst architecture (described below) and replace it with the new Core architecture ● the impact of the 2008 global financial crisis Intel made some attempts at diversification during this period, such as the development of XScale ARM processors and the Atom processor. However, Intel misjudged the mobile market in the 2000s and failed in these areas. They saw low profit margins on mobile processors and chose to focus on x86 processors instead. They also sold XScale just before the mobile device boom – a critical error. Intel even declined Apple’s invitation to manufacture iPhone chips (around 2005/2006), as then-CEO Paul Otellini did not believe the iPhone would be a very high-volume business (oops!). ARM, which was specifically designed for low power consumption, became the dominant architecture for mobile devices, and Intel missed the opportunity. chips available at the time were also more integrated than XScale. Intel went on to focus on its own line of x86-based Atom low-power processors for mobile applications. For hardware vendors already partnered with Intel or using its reference designs, there was no need for another chip in their ecosystem. Since the sale of XScale, Intel’s acquisitions have been mostly in the area of software, not hardware; they have remained focused on a more limited ecosystem. Pentium 4 The Pentium 4, introduced in November 2000 and discontinued in August 2008, was based on the Fig.30: an early (Northwood) Pentium 4 CPU die. Source: https://w.wiki/GZXr XScale XScale was a range of ARM-based processors for mobile and other lower-­ power applications developed by Intel and released in 2002. They sold the chip division that produced them to Marvell Technology Group in 2006. According to a former Intel engineer commenting on Quora Digest, Intel saw itself as an x86 company and was not interested in selling other chips for the mobile market. Other mobile 20 Silicon Chip entirely new NetBurst microarchitecture (internal codename P68) – see Fig.30. NetBurst succeeded the longlived P6 microarchitecture used in the Pentium Pro, Pentium II, Pentium III and early Xeon processors. NetBurst was explicitly designed for extremely high clock speeds through a 20-stage (later 31-stage) hyper-pipeline, a double-pumped (running at twice processor speed) ALU, hyperthreading, an Execution Trace Cache that stored decoded micro-operations instead of re-fetching and re-decoding instructions, and a replay system to recover from mispredicted branches. Despite these innovations, Intel never reached its internal target of Fig.31: a Pentium 4 (Prescott) CPU. This is the final version of the Pentium 4, with x86-64 support, before they were discontinued in favour of the Core series of processors. Source: https://w.wiki/GZX$ (CC BY-SA 4.0) Australia's electronics magazine siliconchip.com.au 10GHz; the fastest shipping Pentium 4 topped out at 3.8GHz (with a brief 4.0GHz Extreme Edition), limited primarily by power consumption and heat dissipation. As a result, Intel abandoned NetBurst in 2006 and introduced the power-efficient Core microarchitecture, which formed the basis of all subsequent mainstream Intel CPUs. Depending on the variant, the Pentium 4 contained between 42 million (Willamette) and 169 million (Prescott-2M) transistors, and was manufactured on process nodes ranging from 180nm down to 65nm – see Fig.31. Itanium Itanium was a family of high-end 64-bit processors from Intel using the IA-64 instruction set, completely unrelated to x86-64. It was aimed at enterprise servers and high-performance systems. See Figs.32, 33 & 34. The design originated at HP as a successor to PA-RISC, based on a new paradigm called EPIC (Explicitly Parallel Instruction Computing). Intel joined the project, and the first Itanium was launched in 2001, with the line eventually discontinued in 2020. Itanium’s defining feature was its VLIW-inspired execution model. Instead of relying on complex hardware to discover instruction-level parallelism at runtime, the compiler packed multiple instructions into ‘bundles’, indicating which operations could execute in parallel. In theory, this simplified the processor and allowed many execution units to stay busy. In practice, it proved extremely difficult for compilers to keep such a wide machine fed, and performance often collapsed unless code was tuned for a specific Itanium generation. This inflexibility earned the architecture the unfortunate nickname “Itanic”. Itanium could run x86 applications through hardware and later software emulation layers, but performance was poor. Ultimately, the architecture failed because of its lack of x86 compatibility, inconsistent real-world performance, compiler complexity, high cost, limited software support and (crucially) the emergence of AMD’s x86-­compatible 64-bit Opteron processors. Intel eventually adopted AMD’s AMD64/x86-64 extension, starting with the Pentium 4 “Prescott” in 2004, then fully committed to it with the siliconchip.com.au Fig.32: an Intel Itanium ES processor module viewed from the pin side. Source: https://w.wiki/GZXx (CC BY 3.0) Fig.33: an Intel Itanium 2 CPU module. Source: https://w.wiki/GZXy Fig.34: an Itanium die shot. Source: der8auer (https://der8auer.com) Australia's electronics magazine March 2026  21 Core 2 series (and every mainstream processor since), effectively sealing Itanium’s fate. Other Pentiums The Pentium 4 was succeeded by the Pentium M (“mobile”; 2003-2006) with 77-140 million transistors on a 130nm-90nm process node, and the Pentium D (“desktop”; 2005-2010) with 230-376 million transistors on a 90nm to 65nm process node. The Pentium D was a dual-core design. The Pentium M did not use the NetBurst microarchitecture, it was based on a modified version of the Pentium III’s P6 microarchitecture with optimised power consumption. It formed the basis of the later Core microachitecture. The D was a performance-orientated dual-core model that did use the NetBurst microarchitecture. The D was Intel’s first mainstream dual-core processor. It was not efficient because the cores could only communicate with each other via the motherboard’s relatively slow front-side bus. To add to the confusion, the Pentium Dual-Core (2006-2010) was based on the more efficient Core microarchitecture. It had 376-410 million transistors and was made with a process node of 65nm or 45nm, depending upon the variant. Also, a revision of the Atom design is used as the “E-cores” in Intel’s hybrid architecture in their 12th and 13th generation Core processor, E-cores are used for task where performance isn’t critical, like handling networking, storage and housekeeping. Core Intel Core brand processors were introduced in January 2006. Yonah was the code name for the first generation of Core processors that replaced Atom the NetBurst microarchitecture. It was The Atom line of x86 energy-­ based on an enhanced Pentium M (P6) efficient mobile processors debuted in microarchitecture and was initially 2008, derived from the Pentium M. It 32-bit only. was discontinued in 2016 due to loss The Yonah core was used in the of competitiveness against ARM-based Core Solo and the Core Duo dual-core processors. However, embedded and mobile products, with 151 million industrial versions of Atom processors transistors on a 65nm process. It was are still available, such as the Atom discontinued in 2008. x7000E or Processor N-series. Core 2 Core 2 was released in July 2006 as the successor to Core. Core 2 used a brand new Core microarchitecture and had 64-bit support (x86-64, compatible with AMD64). Core 2 was released as Core 2, Core 2 Solo (2007), Core 2 Duo and Core 2 Quad models depending upon the number of cores. There were also Core 2 Extreme models for enthusiasts, with a higher clock frequency and an unlocked clock multiplier. Fig.36: the modular structure of a Nehalem (1st Gen Core) processor split into “core” and “uncore” sections. Original Source: https://pcper.com/2008/08/ inside-the-nehalem-intels-new-core-i7-microarchitecture/2/ Core i3/i5/i7/i9 – new naming conventions In November 2008, Intel introduced a new microarchitecture for Core series called Nehalem (see Fig.35), later discontinued in 2010. It came with a new naming scheme, with so-called Tiers representing performance levels. i3 was entry level, i5 mid-range and i7 high-end. i9 was added in 2017 as the top tier. Intel also introduced a new term referring to the Generation of a processor, which corresponds to improvements in performance, power efficiency, features supported and microarchitecture – see Table 5 and Fig.37 overleaf. We discuss the various generations of Intel Core processors in the next section. Nehalem processors used a 45nm process node and had 731-2300 million transistors, depending upon the model. These were called 1st Generation Core processors. A “die shrink” improvement to 32nm was made with Australia's electronics magazine siliconchip.com.au Fig.35: a die shot of a typical Nehalem (1st Gen Core) processor showing various functional elements. Source: https://bjorn3d.com/2008/11/intel-core-i7-920nehalem/ 22 Silicon Chip Table 5 – Intel Core processor generations Generation Brand Intro Year Codename Notable features Original Core Core Solo/Duo 2006 Yonah (mobile) First mobile series, one or two cores Core 2 Core 2 Solo/ Duo/Quad/ Extreme 2006 Conroe, Kentsfield, Wolfdale, Yorkfield, Merom, Penryn First 64-bit support and up to four cores. 1st Gen Core i3/i5/i7 2008-2010 Lynnfield, Bloomfield, Clarkdale, Arrandale Nehalem microarchitecture, integrated memory controller. 2nd Gen Core i3/i5/i7 2011 Sandy Bridge Sandy Bridge microarchitecture, new AVX instructions, integrated GPU. 3rd Gen Core i3/i5/i7 2012 Ivy Bridge Ivy Bridge microarchitecture, 22nm process. 4th Gen Core i3/i5/i7 2013 Haswell, Broadwell-Y Haswell microarchitecture, improved power efficiency. 5th Gen Core i3/i5/i7 2014 Broadwell Broadwell microarchitecture, 14nm process. 6th Gen Core i3/i5/i7 2015 Skylake Skylake microarchitecture, support for DDR4 memory. 7th Gen Core i3/i5/i7 2016 Kaby Lake Kaby Lake microarchitecture and first to abandon tick-tock model. Improved performance and efficiency. 8th Gen Core i3/i5/i7 2017 Coffee Lake, Kaby Lake Refresh, Whiskey Lake, Amber Lake, Cannon Lake Various microarchitectures, increased core counts. 9th Gen Core i3/i5/i7/i9 2018 Coffee Lake Refresh Coffee Lake refresh. 10th Gen Core i3/i5/i7/i9 2020 Comet Lake, Ice Lake, Amber Lake Refresh Various microarchitectures. 11th Gen Core i3/i5/i7/i9 2021 (desktop), Rocket Lake (desktop) 2020 (mobile) Tiger Lake (mobile) Introduced PCIe 4.0 support. 12th Gen Core i3/i5/i7/i9 2021 Alder Lake Hybrid architecture (P-cores + E-cores), Intel 7 process, DDR5 & PCIe 5.0 support. First widely adopted hybrid big. LITTLE architecture. Intel 7 node. 13th Gen Core i3/i5/i7/i9 2022 Raptor Lake Raptor Lake microarchitecture (refresh of Alder Lake). Intel 7 node. 14th Gen Core i3/i5/i7/i9 2023 Raptor Lake refresh Last generation to use “Core I” branding. Intel 7 node. Series 1 Core 3/5/7, Core Ultra 5/7/9 2023 (mobile) Meteor Lake New naming scheme and process, launched in 2023 for mobile with NPU (Neural Processing Unit) for AI. First mainstream Intel processor with chipletbased design. Series 2 Core 3/5/7, Core Ultra 5/7/9 2024-2025 Arrow Lake, Lunar Lake Includes Arrow Lake desktop (2024) and mobile HX/H/U series (early 2025). First Intel desktop processor with chipletbased design. Series 3 Core Ultra 300 Early 2026 series (expected) Panther Lake (mobile) Expected to use the 18A process node the Westmere microarchitecture. Features of this series include a modular and scalable design with separate ‘core units’, which were the execution units and L1 and L2 caches, and ‘uncore units’, which were anything siliconchip.com.au else. Uncore included the L3 cache, the integrated memory controller (IMC) and I/O (USB, PCI Express etc) – see Fig.36. The traditional front-side bus was also replaced with the QuickPath Australia's electronics magazine Interconnect (QPI) for faster communication between processors in multisocket systems, as well as with the rest of the system. Hyperthreading was reintroduced, and Turbo Mode allowed automatic March 2026  23 Fig.37: the naming scheme for Intel Core processors. SKU is the “stock-keeping unit” or the specific model number. Source: www.intel.com/content/www/us/en/ support/articles/000032203/processors/intel-core-processors.html Fig.38: Nehalem’s (1st Gen Core) processor design showing modular building block concept. Source: www.techradar.com/news/computing-components/ processors/intel-s-nehalem-is-a-multi-threading-monster-268687 Intel’s tick-tock model overclocking. Other features included a new SSE 4.2 supplemental x86 instruction set. Nehalem’s modular design allowed Intel to scale the same core building blocks across a wide variety of market segments, from dual-core mobile parts to eight-core server Xeons, simply by adding or subtracting tiles on a die. This modular design should not be confused with the later hybrid architecture. In the Nehalem generation (20082010), all mainstream Core i3/i5/i7 processors were monolithic single-die designs; only certain rare high-end desktop and server processors used a multi-chip module that had a CPU die with an optional separate graphics chip. Regardless of whether the final package contained one or two dies, the CPU itself remained a single monolithic die built from individual building blocks (see Fig.38). The general idea of a modular and scalable design, whether implemented on one monolithic die or multiple dies (later called ‘tiles’ internally and ‘chiplets’ in the broader industry), has been used on all Intel Core processors since Nehalem in 2008. True chiplet (multi-die) consumer Core processors only appeared with Meteor Lake (14th Gen, 2023) and became the standard from Arrow Lake/ Lunar Lake (2024-2025) onward. 2010s: 10nm failures, competitors catch up Fig.39: the tick-tock model for all Intel processors of the 2009-2016 era. The even years bring a new process technology, while the odd years bring a new microarchitecture. The 2010s were characterised by Intel’s repeated delays in moving beyond the 14nm node (introduced with Broadwell, 2014), which saw six generations and six years or more of Core on the same basic node with no reduction in feature size. To be fair, it wasn’t the exact same node used year after year; they did make improvements (leading to the famous 14nm++++ process). Intel failed to reach the 10nm mode in a timely manner (targeted for 2016) and suffered from delays, poor process yields and technical flaws that allowed competitors like AMD, Apple Silicon and ARM to take market share, including in the laptop, desktop and server markets. The tick-tock model was finally abandoned (see panel). Intel’s stock price stagnated, and the decade ended with Intel no longer the unquestioned Australia's electronics magazine siliconchip.com.au Tick-tock was a development model introduced by Intel in 2007 and abandoned in 2016. It was a model that alternated in two-year cycles between reducing the process size (the “ticks”) and improving the microarchitecture of the processor (the “tocks”). Both had the objective of performance boosts via lower power consumption, higher component density and reduced costs. Fig.39 shows how the tick-tock model progressed during most of its period of operation. Note the new microarchitecture (tocks) shown in green and the new process size shown in blue (ticks). The tick-tock model was abandoned because it was no longer economically feasible to keep shrinking dies, ie, Moore’s Law ceased to apply around 2016. 24 Silicon Chip performance and technology leader. Some say Intel’s “10nm disaster” was the result of a technology roadmap that was simply too ambitious. Instead of making a modest shrink from 14nm, Intel attempted to jump directly to a very high-density process with multiple cutting-edge features introduced all at once. Among these were self-aligned quadruple patterning (SAQP) for extremely fine metal pitches, contact-­ over-active-gate (COAG), and the use of cobalt for selected interconnect layers. Each of these was challenging on its own; together, they created a process that was extremely difficult to manufacture at acceptable yields. Compounding these difficulties was Intel’s strategic decision to delay the adoption of EUV (extreme ultraviolet) lithography. The company believed that 193nm immersion lithography, extended through increasingly complicated multi-patterning steps, would remain viable. Meanwhile, competitors such as TSMC and Samsung embraced EUV earlier, simplifying several steps in their 7nm processes. This allowed them to avoid much of the patterning complexity Intel was struggling with, and to achieve usable yields sooner. Another problem was that Intel set extremely aggressive density targets for 10nm: roughly a 2.7× improvement over 14nm. To reach those figures, Intel used very dense standard-cell libraries and restrictive design rules, which caused its design teams to struggle with routing, variability, and timing closure. In essence, the manufacturing process and the design methodology were both too constrained and not sufficiently co-optimised, making it difficult to produce chips that could hit Intel’s desired clock speeds. The result was a multiyear delay in the intended 10nm rollout. The first 10nm generation, Cannon Lake, finally surfaced in 2017-18, but in extremely small quantities, and with key features disabled (most notably the integrated GPU) because yields were still poor. Cannon Lake was essentially a symbolic product launch rather than a viable platform. Real, high-volume 10nm products did not appear until the Ice Lake generation in 2019-2020, two to three years later than planned (and arguably four to five years behind the original roadmap trajectory). siliconchip.com.au These setbacks not only disrupted Intel’s product cadence but also contributed to the end of the company’s historical lead in manufacturing technology – an advantage Intel had held for roughly three decades. While Intel’s mass-production of the 10nm node, intended for 2016, was delayed until 2019, competing foundries such as TSMC started shipping 7nm nodes in 2018. Intel’s 7nm node (branded Intel 4) slipped to 2023 with the release of the Meteor Lake processor. TSMC manufactured many of AMD’s processors using its 7nm process, allowing AMD to obtain increased market share and, in many cases, superior multi-core performance. Core processors During the 2010s and subsequently, Core processors evolved through multiple generations, but all share a common lineage. Some things have changed; others have not. We will not discuss each generation of Core processors, as they mainly represented incremental changes, except for the introduction of the hybrid and then tile architectures. Every Intel Core-branded processor from the 1st Generation (Nehalem/ Westmere, 2008-2010) to the current Core Ultra Series 2 (2024-2025) belongs to the same architectural family that began with the 2006 Core microarchitecture. They all have x86-64 instruction compatibility and include integrated memory controllers, PCIe, and (almost always) graphics, making the Core brand the longest continuous mainstream CPU lineage in the industry. Despite 17 years of massive evolution, a 1st-Gen Core i7-920 and a 2025 Core Ultra 9 285K are still members of the same processor family. Every Intel Core-branded processor from 1st Gen (2008) to the present (2025) has the following aspects in common (from 1st Generation to Core Ultra Series 2). ● All are 64-bit x86 processors using the x86-64 instruction set. ● All descend from the 2006 Core microarchitecture. ● All have an integrated memory controller since Nehalem. ● All have an integrated PCIe controller since Nehalem. ● Most have integrated graphics (except F, KF and X suffix parts). ● Most have Turbo Boost. ● From the Core 2, they all support SSE-SSE3. Nehalem and later add SSE4.1, and all 2nd Gen (Sandy Bridge) and newer include SSE4.2, making the Sandy Bridge family (2011) the practical cut-off for Windows 11 compatibility. ● Intel 64, VT-x, AES-NI, TXT technologies are all present from 1st Gen onward (some added mid-generation). ● Core i3/i5/i7/i9 (later Core Ultra 5/7/9) always indicate relative performance tiers within a generation. The following aspects of Core processors have changed significantly: ● Process nodes (from 45nm to 3nm and beyond). ● The move to a multi-chip module design from monolithic. ● Core counts (from 2 to 38+ in 2025). ● The hybrid big.LITTLE design (from 12th Gen onward). ● The branding shifted to “Core Ultra” (2023+). Fig.40: Intel would normally package their flagship i9 CPUs in interesting boxes. For the 9900K, they used a dodecahedron. Source: www. reddit.com/r/pcmasterrace/ comments/1hhug73/ Australia's electronics magazine March 2026  25 ● New instructions (AVX, AVX2, AVX-512, AMX etc) were added over time. ● Recent chips have a dedicated NPU (neural processing unit). Hardware security problems Further Intel problems emerged in the form of major security vulnerabilities discovered in their processors, beginning with Meltdown and Spectre in 2018. These were not isolated issues, but the first widely publicised examples of a new class of hardware-level side-channel attacks exploiting speculative execution; the very optimisation techniques that had driven CPU performance for years. After the initial disclosures, additional vulnerabilities were uncovered throughout 2018-2020. These included several more Spectre variants and more Intel-specific weaknesses such as Foreshadow (also called L1TF, 2018), which compromised Intel’s SGX secure enclaves, and the ZombieLoad, RIDL, and Fallout attacks (2019), collectively known as MDS (Microarchitectural Data Sampling). Later came SwapGS (2019), TSX Asynchronous Abort (TAA, 2019), CacheOut (2020), Snoop-assisted L1D sampling (Snoop MDS, 2019/2020), and others. Each required microcode patches and/or operating system mitigations, in some cases reducing CPU performance significantly. These vulnerabilities highlighted fundamental defects in speculative execution and cache behaviour, and the need for architectural changes rather than simple software fixes. Intel eventually redesigned parts of its cores (starting with Cascade Lake in 2019, and more fully in subsequent generations) to mitigate some of these flaws in hardware. Earlier processors continue to rely on a combination of firmware and operating system patches, many of which come with performance overheads. These didn’t affect only Intel – AMD processors were vulnerable to some issues too, notably Spectre. However, the vulnerabilities affecting AMD chips were generally far less severe and much easier to mitigate, and the episode clearly shifted the competitive advantage toward AMD’s products. This likely reflects AMD’s more conservative architectural approach to speculative execution, which avoided 26 Silicon Chip many of the pitfalls that plagued Intel’s designs. What is an Intel Core Generation? Intel naming conventions and generations can be very confusing (to say the least). Again, to be fair, AMD’s processor naming scheme isn’t much better. The Generation or Series of an Intel processor is a naming convention that primarily applies to their Core range of processors. Other types of Intel processors such as the Xeon, Pentium, Celeron and “Intel Processor” brand also have generations, but the identification with a specific generation is less prominent and not a marketing feature. The Generation of a Core processor refers to the major product family released roughly every 12-18 months, which usually (but not always) involves a new or refined microarchitecture, an updated manufacturing process, higher core counts, new features, or some combination of these improvements. It is indicated by the first number(s) after the brand in the model name (eg, Core i7-13700K = 13th Generation, Core i9-14900K = 14th Generation). Intel stopped using “Gen” with the 14th Gen and started using Series, eg, Core Ultra 7 200V = Series 2 / Lunar Lake generation – see Table 5. In 2023, Intel introduced a new naming scheme for laptops with the Meteor Lake generation, dropping the old i3/i5/i7/i9 branding and replacing it with the Core Ultra name and a new Series-based numbering system (eg, Core Ultra 7 155H). Desktop processors, however, continued to use the traditional 14th Gen style naming for a transitional period. Core Ultra processors also introduced a built-in Neural Processing Unit (NPU) for on-device AI acceleration. The letters at the end of a traditional Intel CPU model name indicate specific features, for example: ● K means the processor is unlocked and suitable for overclocking ● F has no integrated GPU ● S means special edition ● T means power optimised ● H, HK or HX means the processor is a high-performance type ● P means performance-optimised for thin and light laptops ● U means power-efficient ● Y means extremely low power ● G1-G7 means integrated graphics Australia's electronics magazine of different performance capabilities ● E means embedded with various features (UE, HE etc) Significant changes in the Core lineup were the new hybrid core approach in the 12th Generation and beyond, ongoing improvements in energy efficiency and support for newer features, such as the PCIe 5.0 bus and DDR5 memory. 2020s: hybrid technology, foundry ambitions The 2020s to date have been characterised by Intel’s pursuit of hybrid technology (the use of different processor cores in the one package) and their foundry ambitions to become the “TSMC of the West again”, through their Integrated Device Manufacturing (IDM 2.0) strategy. Intel is also fighting to regain manufacturing leadership and relevance in AI, mobile and beyond-PC markets in an era where “Intel Inside” no longer automatically means dominance. Under Gelsinger’s leadership, Intel’s IDM 2.0 strategy was developed in 2021 as a comprehensive strategy to: a. develop more advanced and competitive chips b. expand manufacturing capacity and capability, particularly in the United States c. launch Intel Foundry Services (IFS) to build chips for other companies d. make strategic use of other foundries such as TSMC when necessary e. develop its own internal foundry model to ensure consistent processes throughout its foundries Some of Intel’s new US foundry developments have also been heavily subsidised by US taxpayers, reflecting a political aim to rebuild domestic semiconductor manufacturing. Under the CHIPS and Science Act, Intel has received billions of dollars in grants, tax incentives and low-cost loans to modernise existing fabs and construct new ones in Arizona, Ohio and other locations. Hybrid architecture: E- and P-cores Intel’s hybrid architecture started with the 12th Generation in 2021 and continues today. These chips contain two kinds of cores: high-performance “P-cores” (big cores) optimised for maximum single-thread speed and heavy workloads, and high-efficiency “E-cores” (little cores) optimised for siliconchip.com.au low power consumption and good multi-threaded throughput at much lower clocks and a smaller die area. The use of the two core types allows less intensive background tasks to use the energy-efficient E-cores, while more intensive high-power tasks, such as video editing, 3D games or CAD, can use the faster P-cores. The main advantage of having the two types of cores is improved energy efficiency without a loss of performance, resulting in greatly improved battery life in mobile devices and less stringent cooling requirements for desktop computers. Windows 11 (and modern Linux) and the Intel Thread Director hardware scheduler decides in real time which threads run on P-cores and which run on E-cores. Alder Lake was the first 12th Generation Core, released in 2021 and discontinued in 2025. It used the Gracemont microarchitecture for its E-cores and the Golden Cove microarchitecture for its P-cores, both fabricated on a single monolithic chip, not separate chiplets or tiles – see Fig.41. Alder Lake used a 14nm or 10nm (Intel 7) process node, depending on version, and had up to eight E-cores and eight P-cores per chip. Intel did not release a transistor count for any version of this processor. Following Alder Lake, the design focus moved to chiplets (known as tiles by Intel), which are individual pieces of silicon in one package, designed with efficiency, cost and flexibility in mind. The first chiplet design was Sapphire Rapids, a Xeon processor, released in 2021. Meteor Lake was the first Core processor to use tiles (Core Series 1, 2023). Next month We’ve run out of space this month, but now that we’ve caught up with the present in terms of Intel’s CPU technology, we’ll shift to look at the current and future technologies they are using to remain competitive. That will include tiles, Foveros Direct 3D interconnections, EMIB, PowerVia, RibbonFET, AI acceleration and their work on dedicated GPUs. We’ll also look into their fabrication facilities, other technologies they helped develop (like USB and Thunderbolt) and provide more detail on their CEOs and other notable people SC who worked for Intel. siliconchip.com.au Fig.41: a die shot of an Alder Lake P with six performance cores, eight efficiency cores and 96 execution units (EUs). EUs assist in computation and/or graphics. Source: https://locuza.substack.com/p/die-walkthrough-alder-lake-sp-and Australia's electronics magazine March 2026  27