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Altium Designer 25 Review by Tim Blythman Altium Designer 25 is the latest version of the EDA (electronics design automation) software that we use for all of our PCB designs. This new version was released late in 2024, and we have spent some time putting it through its paces. Here is what we have found. W e have used related products for our PCB designs for over 30 years, starting with Protel Autotrax! So we were keen to see what has been updated since our review of Altium Designer 24 from August last year (siliconchip.au/Article/16425). Since that article was written, there is the news that Renesas Electronics has acquired Altium; the acquisition was completed in August 2024. Renesas is a Japanese semiconductor manufacturer that includes the semiconductor operations of companies like Hitachi, Mitsubishi and NEC. That marks an interesting geographical history for Altium, with Protel Systems Pty Ltd originally founded as an Australian company. For many years, it has been headquartered in San Diego, California. We’re most familiar with Renesas Electronics as the manufacturer of the RA4M1 microprocessor used in the new Arduino Uno R4 microcontroller board we reviewed in December 2023 (siliconchip.au/Article/16047). The Raspberry Pi 5 also uses a Renesas power management IC. AD25 overview Altium Designer 25 looks and feels much the same as previous versions, but like many modern applications, it is constantly evolving. This time we are looking at version 25.0.2. The webpage at www.altium.com/ documentation/altium-designer/new lists details of the various version updates and the versions (and subversions) to which they apply. So you can 42 Silicon Chip easily see which version has a particular feature. Some features that are present are disabled by default but can be turned on via the Advanced Settings window of Preferences. Others are available as Extensions, which can be installed from the Extensions and Updates window. Such features may still be at the beta testing stage. Beta testing means that the feature is essentially complete but not fully tested. It may still be changed if users find bugs. It is a good way to get early access to novel features, and there is usually the ability to toggle these features on and off. Just as with previous versions, it is possible to install multiple versions of Altium Designer alongside each other. You might like to do this to try out the features in a new version without committing to it until you are happy with the changes. Amongst other videos, the new features are also presented at the Altium Academy YouTube channel (www. youtube.com/<at>AltiumAcademy). These and other training materials are also available on the Home Page of the Altium Designer application. Performance Altium Designer 25 claims to have much improved performance, especially with large designs. Our designs are typically on the smaller and less complex side, so we’re not really able to put this aspect to the test. But we were certainly happy with its responsiveness in the time we’ve been using it. Australia's electronics magazine This applies to many aspects of Altium Designer, including the schematic and PCB editors, and Draftsman, as well as in collaborative tools like Altium 365 and PCB CoDesign. Operations like opening documents, repouring polygons, placing stitching vias and bulk copying and pasting have all been sped up. These improvements have been brought about through better memory management and caching of data where possible. On a related note, recent versions of Altium Designer (starting with 24.8) use the newer .NET 6 software framework. Previously, Altium Designer used Microsoft’s proprietary and now obsolete .NET Framework 4.8. Unsurprisingly, .NET 6 is also faster. Interestingly, .NET 6 is fully opensource. It is intended to be modular and works across multiple platforms (including Windows, Linux and macOS). Dare we wonder if this is the first step of being able to run Altium Designer on a Linux PC or Mac? The SI Analyzer by Keysight Another extension that sounds quite handy is the Signal Integrity Analyzer by Keysight, although this is another one that we probably won’t ever need to use due to our modest designs. As the name suggests, it is intended to perform signal integrity analysis on high-speed designs. Fig.1 shows the phases of such an analysis. It can calculate things such as impedance, delay, insertion loss and return loss based on the PCB layout. siliconchip.com.au Fig.1: the Signal Integrity Analyzer by Keysight can be used post-layout to validate signal integrity and provide checks on parameters such as impedance, delay, insertion loss and return loss. This will be very handy to validate high-speed designs before committing to PCB manufacture. Source: www.altium.com/documentation/altiumdesigner/new?version=24#sianalyzer-by-keysight-openbeta-24-10 Fig.2 (below): this trace is ‘necked down’ to fit through a narrow gap between other pads; we did this manually, using an older version of Altium Designer. The new auto-shrink feature allows this to be done automatically during interactive routing. This can help to validate the PCB before it is committed to manufacture. Signal Integrity Analyzer is currently a beta feature and requires the SI Analyzer by Keysight extension to be installed; there is a free 14-day trial available for this feature. Routing When routing the traces on a board, it is sometimes necessary to use a track narrower than the preferred width to fit through a congested or tight area. This is often described as ‘necking down’, where the trace is narrowed down to a thin neck just long enough and narrow enough to fit. Previously, you would have to do this manually, but there is now an option to auto-shrink the width to the minimum you’ve set. This will be handy, since manually creating a neck can be a fiddly process, especially if you want the result to be neat. In addition, a new design rule allows the neck to have a maximum specified length, to avoid having too much resistance or increased fragility. siliconchip.com.au Currently, both these features are in beta and need to be activated in Advanced Settings. The auto-shrink feature is enabled with the “PCB.Routing.EnableAutoShrinking” option, while the neck-down rule follows the “PCB.Rules.RoutingNeckdown” setting. There is also an option to centre traces when routing. Typically, the auto-router will place traces at the minimum allowed clearance from the nearest track, but spreading the traces out may be preferred. It can also make the routing neater, since the traces will be spread out more evenly. This is also a beta feature and is set with the “PCB.EnableTraceCentering” advanced setting. Fig.2 shows an example of a trace necking down through a narrow gap on our Thermal Controller PCB from March & April 2020 (siliconchip.au/Article/12584). Single-layer PCBs For simple designs, a single-layer PCB (with copper on just one side) can be an economical choice, especially for designs on flexible substrates. Large Australia's electronics magazine production runs can warrant the savings in eliminating a copper layer where that is feasible. It’s now possible to lay out single-­ layer PCBs by enabling the “PCB. SingleLayerStack.Support” option in Advanced Settings, then removing a copper layer from a two-layer PCB stack. Constraint Manager The Constraint Manager unifies design constraints from both the schematic and PCB layout. It works in place of the PCB Rule and Constraints Editor dialog (Design Rules). A project can be set up (at creation) to use the Constraint Manager or to use the older Design Rules. There is also a tool that can convert a project from using Design Rules into one that is compatible with the Constraint Manager. It provides a hierarchical system that is automatically translated into the priority in which rules are applied. Constraint Manager can be enabled by setting the “System.ConstraintManager” option in Advanced Settings. June 2025  43 Source: www.altium.com/ documentation/altium-designer/ constraint-manager Fig.3: the Constraint Manager provides a new interface for managing design constraints (design rules) across a project. Older projects can be upgraded to use the Constraint Manager. Fig.3 shows some views of the Constraint Manager. Importing Occasionally, we have to deal with contributed PCBs that have been designed using a different EDA tool, and sometimes we need to change them. This might be as simple as making a small change to the silkscreen markings or could involve a major revision of the copper routing layers. Some changes can be made by directly editing the Gerber files, but having access to fully editable PCB design files is better for many reasons. Firstly, that makes it possible to run design rule checks to validate that any changes do not cause a manufacturing issue like shorted traces. It then becomes possible to make further revisions if needed in the future. Whatever the reason, this means that we need the ability to import designs from other EDA tools into Altium Designer so that they can be turned into native Altium Designer files, such as SchDoc schematic files or PcbDoc PCB files. The latest version of the importer now works with KiCad designs from 44 Silicon Chip KiCad version 7 or 8. This is available as an extension known as the KiCad Importer Extension and can be found in Extensions and Updates. Their website at siliconchip.au/link/ ac41 has more information on importing designs from other tools. Fig.4 shows a screenshot from our installation of the Software Extensions that are on offer. We have previously mentioned the free online Altium 365 Viewer, which is at www.altium.com/viewer This now supports KiCad files, and we had no trouble using it to view some KiCad PCB files that we found online. Wire bonding Altium Designer can be used for designing much more than just traditional planar substrate PCBs. We have previously covered Altium Designer’s ability to work with flexible and hybrid (rigid-flex) PCBs, printed electronics and 3D-printed substrates using the 3D-MID (three-dimensional mechatronic integrated device) process. Another example is the recent Harness Designer. (Also see our article on 3D-MID technology in the April 2025 Australia's electronics magazine issue at siliconchip.au/Article/17936). One of the technologies supported by Altium Designer 25 is COB (chipon-board) using wire bonding. COB involves bare silicon chip dies being bonded directly to a PCB. Connections are made from pads on the die (die pads) to the bond finger pads on the PCB by means of bond wires. The bond wires used in COB applications are much the same as the bond wires used to connect a silicon chip to its leadframe in a traditionally packaged integrated circuit. These are very fine wires of a metal such as gold, copper or aluminium that are welded to their pads using heat, pressure or ultrasonic energy. The process is typically performed by an automated robotic system. You can see some images of a COB design at www.altium.com/documentation/ altium-designer/wire-bonding while the photos at upper right shows two examples of silicon dice bonded to a PCB. Creating a COB design involves adding a Die layer and a Bond wire layer to a PCB document or library. A complete footprint ‘package’ including die pads, bond finger pads, and bond wires siliconchip.com.au Fig.4: numerous Altium Designer extensions can be installed from the Extensions and Updates tab. This shows just some of the extensions available on our system. can be created, in which case the bond finger pads can be simply routed to on the copper layers. Alternatively, a die with die pads can be placed alongside separate bond finger pads. The bond wires are then placed manually. With the current version, wire bonding can be enabled with the “PCB.Wirebonding” option in the Advanced Settings dialog. For manufacture, a wire bonding table report can be generated. As you can see from Fig.5, Altium Designer’s 3D rendering allows you to see all aspects of a wire-bonded design. For example, you can visually check that crossed bond wires pass at different heights to avoid collisions. We find the 3D views invaluable for making sanity checks on our PCB layouts. There are three different subscription levels available for Altium Designer: Standard, Pro and Enterprise. They differ in the number of features that are included and more information is available at www.altium. com/altium-designer/licensing In addition to covering the important aspects of a feature (in this case, Single-­layer PCBs), it follows with a live demonstration of how to use that feature within Altium Designer. The free trial offer that we have mentioned in previous years is still available. It allows you to use a fully featured trial version of Altium Designer for 15 days; see www.altium.com/ altium-designer/free-trial Resources Conclusion Altium offers numerous resources to allow users to make the best use of Altium Designer. You can view a recent webinar (recorded in November) at siliconchip.au/link/ac42 Altium continues to make incremental updates to Altium Designer. While there are some bigger features that we would struggle to use fully, such as wire bonding, they are no doubt useful for larger organisations. It is good to see that they continue to improve usability and work on basic features such as routing. We hope that the switch to .NET 6 is the beginning of cross-platform support. We’re especially keen to be able to use Altium Designer on Linux, since so many of the other programs that we use already allow that. For more information on Altium Designer, visit www.altium.com/ altium-designer SC Licensing Fig.5: Altium Designer 25 now allows wire bonding between silicon dies and PCBs. This image shows an example of two COB (chip on board) dies bonded to the PCB below. Source: www.altium. com/documentation/ altium-designer/wirebonding#placing-wirebonds-in-a-pcb siliconchip.com.au Two examples of chips bonded directly to PCB pads. Source: www.rocket-pcb.com/rocket-pcbwholesale-wire-bonding-technologybulk-fabrication-for-electronics Australia's electronics magazine June 2025  45