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By Andrew Levido Precision Electronics Part 9: System Design In this last article in the Precision Electronics series, we look at the design of a precision electronics system from the big-picture perspective. We have already covered a lot of the building blocks; this will bring them together and show how to approach the design of a whole system. T o do this, we will look at a practical example of moving from a high-level specification to developing design goals for each circuit block, then dive in detail into a couple of the blocks for good measure. Before we get into it, I want to summarise some of the key tips and tricks we have learned from previous articles that might help guide our design. These are not hard-and-fast rules; they are just things I have found it helpful to keep in mind: • Precision and accuracy are different things. Precision is all about errors and repeatability, while accuracy is all about calibration and traceability. • Break circuits down into bitesized chunks to perform error analysis. Things can get overwhelming if the circuit being analysed is too complex. • When like quantities with errors add or subtract, add the absolute errors. When quantities with errors multiply or divide (like an input offset through a gain), add the relative (proportional) errors. • Completely uncorrelated random errors (like white noise) can be added as the root sum of squares – either absolute or relative, depending on the application. This also applies to calculating a DAC’s or ADC’s total unadjusted error (TUE) figure. • You can easily calibrate or trim out fixed errors like offset and gain errors. It is harder to do so for non-­ linearities or errors that change with temperature. The highest-precision devices use this technique extensively, often performing calibration before every reading. • In general, keep the span of precision signals away from the power rails or the ends of ADC and DAC ranges where they coincide with the supply rails. This is one place where non-­ linear errors love to hide. • Read data sheets carefully, including the graphs. Manufacturers don’t usually highlight the shortcomings of their parts in the headline specs. Use worst-case errors (not typical values) unless you have a good reason not to. • Use larger signals and lower gains where you have a choice. Input-side errors are magnified by gain stages. The signal-to-noise ratio can be improved by using larger signals. • Reduce noise by limiting circuit bandwidth and using lower-value resistors where possible. Oversampling and averaging is a useful form of bandwidth limitation. • Reduce cost by using components with no higher precision than you absolutely need. Use an error budget spreadsheet to understand the major contributors to error and focus on these first. The process of top-down design is kind of the opposite of what we have done so far, where we looked at individual circuits and calculated their errors. This time, we will divide the Fig.1 (left): the highlevel block diagram of our hypothetical power supply. This is all we need to start the design process. Fig.2 (below): the error amplifier in the control block will most likely include an inverting, summing amplifier like this. If so, the setpoint & feedback voltages must be of opposite polarity. 46 Silicon Chip Australia's electronics magazine siliconchip.com.au overall system error up to develop an error ‘budget’ that will guide the design of each subsystem. This sounds very straightforward, but in practice there is almost always a certain amount of iteration (even to the point sometimes of revising the top-level specifications). A simple power supply The example I want to work with is a simple power supply that can source a voltage in the range of 0-20V with a maximum current of 1A. We are not going to fully design this power supply here – we are just aiming to develop the error budget and look at the system considerations including coming up with a calibration strategy. I will go through a more detailed component selection and analysis for a small part of the circuit, just to show how I go about it. Let’s start with some target specifications. We want to be able to set the voltage in 100mV steps and the current limit in 10mA steps. This corresponds to a modest precision of ±0.5% for the voltage and ±1% for the current setpoint. However, we want to be able to measure the voltage and current to a precision of ±0.1% (±20mV and ±1mA respectively). These specs are all defined at nominal temperature (25°C). For simplicity’s sake, we will assume that they should be no worse than 150% of nominal over the operating temperature range. This is a laboratory instrument, so I am going to arbitrarily decide that a range of 5°C to 45°C (25°C ±20°C) will be adequate. Two-point calibration The figure below shows a system like the voltage setpoint and regulation circuit in our example power supply. The ideal transfer function for the system is y = kw, where k is the design gain (for example, some number of millivolts per LSB), w is the input digital code and y is the output quantity. There is gain, but no offset, in this ideal system. A real system may have both a gain error and an offset error, as shown on the bottom of the figure. Here, the gain (m) is close but not equal to the ideal gain, k, and there is a non-zero offset, b. The firmware correction block shown on the left takes in the input code w and applies correction gain n and offset c to produce a corrected code x, such that the output of the hardware system y has the ideal relationship with the input code w. If we measure the hardware system’s transfer function (ie, find the gain [m] and offset [b]), we can calculate the compensating gain n and offset c. Twopoint calibration is the simplest process that allows us to calculate these correction factors. The calibration cycle starts by setting the correction gain n to unity and the correction offset c to zero. This means DAC code x will equal the raw code w. The calibration firmware then sets the code to a value near the bottom end of the span (wL), as shown in the figure, and we measure the output quantity (yL) using an external meter. This value is provided to the firmware. Next, the calibration routine sets code w to one near the top of the span (wH). This is also measured and entered into the instrument. Now the firmware can calculate the hardware’s transfer function coefficients using the equations m = (yH – yL) ÷ (xH – xL) and b = yL – mxL. With this done, the correction factors can be calculated from the relations n = k ÷ m and c = –b ÷ m. These factors would be stored in non-volatile memory and used to correct the DAC code to compensate for the gain and offset errors in the hardware. Two-point calibration has the advantage of being very simple to implement. You can improve on it by using more points (called multi-point calibration), and deriving the hardware transfer function from a suitable line-of-best-fit algorithm. High-level circuit design Designs should start with a simplified block diagram, as shown in Fig.1. Here, a microcontroller (not shown) feeds a pair of DACs which, together with the signal conditioning blocks, create the voltage and current setpoints that are applied to the power supply control circuit. This circuit regulates the output voltage and manages the current limiting. Feedback of the output voltage and current is necessary to allow the control circuit to regulate properly. The voltage feedback for the control circuit comes from the power supply output via high-impedance buffer 1. This unity-gain buffer is required to minimise the current drawn from the output terminal, as this will affect the siliconchip.com.au current measurement. The same buffer provides the voltage measurement input to ADC2 via a voltage divider and a second unity-gain buffer. Current sensing is provided via a high-side shunt resistor and instrumentation amplifier. This feeds both the control circuit and the current measurement function via ADC1. We will need two DACs since we have to provide both setpoints simultaneously, but we can get away with one ADC with an input multiplexer, since we can sample the current and voltage alternately. Error amplifier The control circuit is most likely going to contain error amplifiers made Australia's electronics magazine using an inverting, summing amplifier like that shown in Fig.2. This topology has two implications for our design. First, it means that the senses of the setpoint and feedback signals need to be opposite, so the error amplifier sees the difference between the output and the setpoint. If the setpoint is negative, as shown, a setpoint increase (ie, a more negative voltage) will cause the error amplifier output to increase in a positive direction, driving the output voltage or current limit higher. Similarly, if the feedback level increases, the error amp output will be forced lower, reducing the output voltage or current limit. Secondly, the error amplifier summing junction (the op amp’s inverting July 2025  47 input) sits at 0V and actually sums currents determined by the input voltages and the values of the two input resistors, R1 and R2. The result is that the full-scale setpoint voltage and full-scale feedback voltages do not have to be the same, since we can adjust the values of the resistors to make their full-scale currents equal. We do have to be concerned with the precision of the ratio between the resistor values, as any deviation will cause an error in the setpoint. Fortunately, we do not have to worry about anything further into the controller circuity, as any offset and gain errors here are eliminated by the action of the feedback. The same is true for non-linearities in this part of the circuit, although if they are extreme, they can impact control loop stability. Block diagrams & error budget Fig.3 shows the circuit in Fig.1 broken down into four ‘signal chains’, one each for the voltage and current controls, and one each for voltage and current sensing. This is a great way to get a handle on just which circuit block impacts the overall device precision. Some of the blocks appear in multiple chains; for example, the output voltage buffer appears in all the chains. In other cases, like the setpoint signal conditioning block, there are separate but identical blocks. The task, then, is to take the overall precision specification for each signal chain and allocate it to the various circuit blocks. The duplication and repetition of blocks described above makes this a slightly complex process. I used an error budget spreadsheet like that of Table 1. I have listed the unique circuit blocks down the left-hand side and the four signal chains across the top. Where a particular circuit block appears in a signal chain, I entered the appropriate number in the matrix. I then made a stab at setting an error budget for each circuit block down the left side, while checking the totals in blue along the bottom compared to the targets shown in purple. It is best to start from the most difficult chain (the current sensing chain in this case) and work from there. You can see that some of the error budgets end up better than the target, which is OK at this stage. There is no point in allocating the error budget down to the nth degree in this process. You can see that the budget here shows the current-sensing signal chain to be just over the target. This is near enough for this stage in the design cycle. It does take a bit of experience to work out what are reasonable error assumptions for each particular block, but hopefully, some of the previous articles in this series have given you a feel for it. Clearly, a unity-gain buffer using a zero-drift op amp will have a much lower error than a 16-bit ADC. The next step is to work through the design, block by block, selecting components and topologies that will meet the targets for each subcircuit. I recommend starting with the subsection where you think it will be most difficult to achieve the target precision. This may not be the area with the highest precision requirement. Calibration strategy Fig.3: the power supply functions can be broken down into these four signal chains. Some of the circuit blocks appear in multiple chains, complicating the process of assigning error budgets to each one. The errors in Table 1 are trimmed errors, so we need to have some idea of our calibration strategy to translate these to untrimmed errors for the design process. To keep things simple, for this power supply, I plan to perform calibration manually when we build the supply and every now and again thereafter. This eliminates the need for in-system calibration circuitry. However, this implies that our calibration will only be able to improve fixed gain and offset errors at the nominal temperature. The minimum required to do this is two-point calibration (described in detail in the accompanying panel). This means calculating and storing an offset and a gain calibration value for each of the four signal chains. Australia's electronics magazine siliconchip.com.au 48 Silicon Chip In practice, the calibration of the setpoint and measurement chains can be done simultaneously. For example, to calibrate the two voltage signal chains, we would set the voltage at some low value (say 1.0V) and measure the actual terminal voltage with an external meter with sufficient resolution. We would do the same at some high value (say, 19.0V). Once entered into the system, these two values can be used to calculate calibration coefficients for the setpoint chain by comparing them with the nominal setpoint, and the measurement chain by comparing them with the values read by the ADC. Given this calibration strategy, I have made the assumption that we can calibrate fixed offset and gain errors down to 5% of their untrimmed values (ie, we can calibrate out 95% of the error). Non-linear errors and temperature dependent errors are not reduced at all by this method. Voltage setpoint design I will go through the process in some detail for a small part of the circuit to show you the idea, starting with the voltage setpoint circuit, although I have included the full set of error calculations in Table 2. To do this, we need to define some full-scale voltage levels. We will start by assuming that we have a 3.3V logic supply for the microcontroller and ±5V analog supplies, as well as the 24V unregulated supply used for the output. We would like to use a low-cost serial DAC, since the setpoint precision requirements are not strenuous. This will have to run from 3.3V to interface with the micro, so we will Table 1 – error targets for each circuit block (in purple) and the resulting error (in blue) Circuit Block Error <at> 25°C Additional Voltage Current Error ±20°C Setpoint Setpoint Voltage Sensing Current Sensing DAC 0.250% 0.125% 1 1 Setpoint signal conditioning 0.100% 0.050% 1 1 Summing node 0.013% 0.006% 1 1 Buffer 0.013% 0.006% 1 1 2 1 Current sensing 0.040% 0.020% Voltage divider 0.013% 0.006% 1 ADC 0.050% 0.025% 1 Voltage reference 0.003% 0.001% 1 1 1 1 1 1 1 Target error <at> 25°C 0.500% 1.000% 0.100% 0.100% Target additional error ± 20°C 0.250% 0.500% 0.050% 0.050% Total <at> 25°C 0.378% 0.418% 0.090% 0.105% Total additional ± 20°C 0.189% 0.209% 0.045% 0.053% Total error 5°C to 45°C 0.566% 0.626% 0.135% 0.158% be limited to a full-scale analog range somewhere below this level. If we select a full-scale voltage of 2.5V, we will have a wide choice of low-cost external voltage references. One of our precision design rules of thumb is that we should not trust analog values as they approach the power supply limits. We will have a DAC output that varies between 0V and 2.5V, depending on the input code. Given a resistor-string DAC with a 3.3V supply, we can be reasonably comfortable at the top of the range, since there is plenty of headroom between the highest tap voltage (very close to 2.5V) and the analog supply rail (3.3V). However, the bottom end of the DAC’s resistor string will be grounded, as will the DAC’s analog circuitry, so we cannot count on the lower end of the range. This is a problem because it suggests that we will lose accuracy near the bottom of the range and/or might not be able to set the output voltage or current limit right down to zero. You will recall that we need a negative setpoint signal, so we anticipated a signal conditioning block between the DAC and the controller. The simplest way to do this would be to use a unity-­ gain inverting amplifier, as shown at the top of Fig.4. With a 2.5V reference, this gives us an output in the range 0V to -2.5V, as shown in the graph on the right of the figure. Unfortunately, this does nothing to help with our near-zero problem. However, if we use a difference amplifier as shown at the bottom of Fig.4, we shift the DAC output down by Vref, rather than inverting it. The upshot is that we will get very nearly a true 0V output when the DAC is at full scale. As the DAC output approaches At Nominal 25°C Error Additional error over 25 ±20°C Abs. Error Rel. Error Abs. Error Rel. Error 2 DAC Offset Error: ±15mV, 10µV/°C 15mV 0.750% 200µV 0.010% 3 DAC Gain Error: ±1%, 3ppm/°C 20mV 1.000% 60µV 0.003% 4 DAC INL: ±4LSB 2mV 0.098% 0mV 0.000% 5 Trimmed Error: 5% of (Line 2 + Line 3, root sum squares) + Line 4 3.2mV 0.160% 208.8µV 0.010% 1 DAC: MCP48FVB22, 12-bit, Two Channels, SPI 6 Temperature Drift Error: Line 2 + Line 3, root sum of squares Setpoint Signal Conditioning: TPA1834 Op Amp, Quad Zero Drift 1 Op Amp Offset Error: ±7µV, ±0.04µV/°C 7µV 0.000% 800nV 0.000% 2 Op Amp Gain Resistor R1/R2: Vishay ACASA, 0.1%, 0.05% matched, 15ppm/°C 1mV 0.050% 600µV 0.030% 3 Trimmed error 5% of (Line 1 + Line 2) 50.4µV 0.003% 600.8µV 0.030% 4 Temperature Drift Error: Line 1 × Line 2 Table 2 – detailed error calculations each signal block (see overleaf for the rest of the table; LSB = least significant bit). Absolute error values are with respect to 2V out July 2025  49 Table 2 continued... At Nominal 25°C Error Abs. Error Rel. Error Additional error over 25 ±20°C) Abs. Error Rel. Error Summing Node: RN73C2A, 0.1%, 10ppm/°C 1 Summing Node Gain Error 0.200% 2 Trimmed error 5% of Line 1 0.010% 0.020% 3 Temperature Drift Error (Line 1) 0.020% Buffer: TPA1834 Op Amp, Quad Zero Drift 1 Op Amp Offset Error: ±7µV, ±0.04µV/°C 7µV 2 Trimmed error 5% of Line 1 0.000% 800nV 0.000% 0.000% 3 Temperature Drift Error (Line 1) 0.000% ADC: ADS1115, ∆∑, 16-bit, 4CH, I2C 1 ADC Offset Error: ±3LSB, 0.005LSB/°C 114.4µV 0.005% 3.1µV 0.000% 2 ADC Gain Error: ±0.15%, 40ppm°C 3.8mv 0.150% 2mV 0.080% 3 ADC INL: ±1LSB 38.1µV 0.002% 4 Trimmed error 5% of (Line 1 + Line 2, root sum squares) + Line 3 225.7µV 0.056% 2mV 0.080% 5 Temperature Drift Error (Line 1 + Line 2, root sum of squares) Current Sense 1 Shunt Error 1Ω: VMP-1R00-1.0-U, 1%, 20ppm/°C 10mΩ 1.000% 400µΩ 0.040% 2 In Amp: INA821: VOS ±35µv, 0.4V/°C 35µV 0.002% 8µV 0.002% 3 In Amp Input Voltage Error Total: Line 1 + Line 2 10mV 1.004% 408µV 0.041% 4 In Amp Gain Resistor RG: ERA-6ARB333V (0.1%, 10ppm/°C) 0.100% 0.020% 5 In Amp gain error (0.015% ±35ppm/°C) 0.015% 0.070% 6 Total In Amp gain error (Line 4 × Line 5) 0.115% 0.090% 7 Trimmed error 3% of (Line 3 × Line 6) 677.9µV 0.034% 8 Untrimmable temperature drift error (Line 2 × Line 3) 2.6mV 0.131% Voltage Sense Divider: RN73C2A, 0.1%, 10ppm/°C 1 Divider gain error 0.200% 2 Trimmed error 5% of Line 1 0.010% 0.020% 3 Temperature drift error (Line 1) 0.020% Reference: REF3425TD, 2.5V, 0.05%, 6ppm/°C 1 VREF error 0.050% 2 Trimmed error 5% of Line 1 0.003% 0.012% 3 Temperature drift error (Line 1) 0.012% ADC Iteration #2: AD7705, ∆∑, 16-bit, 4CH, SPI 1 ADC Offset Error: 0.0 (with internal cal), 0.5µV/°C 0V 0.000% 10µV 0.000% 2 ADC Gain Error: 0.0 (with internal cal), 0.5ppm/°C 0µV 0.000% 25µV 0.001% 3 ADC INL: ±0.003% FSR 75µV 0.003% 4 Trimmed error 5% of (Line 1 + Line 2, root sum squares) + Line 3 75µV 0.019% 26.9µV 0.001% 5 Temperature drift error (Line 1 + Line 2, root sum of squares) Current Sense Iteration #2 1 Shunt Error 1Ω: VMP-1R00-1.0-U, 1%, 20ppm/°C 10mΩ 1.000% 400µΩ 0.040% 2 In Amp: AD8223: VOS ±100µv, 1.0µV/°C 100µV 0.005% 20µV 0.004% 3 In Amp Input Voltage Error Total : Line 1 + Line 2 10.1mV 1.010% 420µV 0.042% 4 In Amp Gain Resistor RG: ERA-6ARB333V(0.1%, 10ppm/°C) 0.100% 0.020% 5 In Amp gain Error (0.02% ±2ppm/°C) 0.020% 0.004% 6 Total In Amp gain error (Line 4 × Line 5) 0.120% 0.024% 7 Trimmed error 3% of (Line 3 × Line 6) 684.8µV 8 Untrimmable temperature drift error (Line 2 × Line 3) 50 Silicon Chip Australia's electronics magazine 0.034% 1.3mV 0.066% siliconchip.com.au zero, the circuit output approaches -Vref, corresponding to the maximum output voltage. By setting the full-scale setpoint voltage to something less than -Vref; say, letting -2.0V correspond to a 20V output, we avoid the very bottom part of the DAC’s output voltage range and the errors that may lie there. The downside is that the full-scale DAC code now represents a setpoint of zero and a code near (but above) zero represents full-scale. This inconvenience is easy to remove in the firmware with a simple subtraction. So, for the sake of the exercise, we will set the voltage setpoint range to 0V to -2.0V representing, 0V to 20V, and the current limit setpoint voltage to 0 to -2.0V, representing 0A to 1.0A. We can now select a candidate DAC. I chose the MCP48FVB22 low-cost two-channel 12-bit serial DAC from Microchip for this exercise. Its specifications are shown in the appropriate section of the error budget table. Since 2V is our full-scale output, I have used that as the basis for converting between absolute and relative errors. The upshot is a DAC error of ±0.16% at 25°C with another ±0.01% over the operating temperature range, well inside our ±0.25% budget. The errors for the setpoint signal conditioning are calculated as we have shown in previous articles. I used a matched resistor array and a low-cost zero-drift op amp, which gives us an overall 25°C error of ±0.003%. In this case, the resistors’ ±15ppm temperature drift means we have an order of magnitude more error over the temperature range; however, this is still well inside the error budget. The summing node errors are dictated by the matching of the resistors – in this case, I used ±0.1% tolerance resistors with ±10ppm/°C drift. The resulting 25°C and temperature drift errors are ±0.01% and ±0.02%, respectively. The buffer uses the same zerodrift op amp as the signal conditioning, and this circuit yields errors that are so low as to be insignificant in our application. The results for each of these blocks (plus the rest, which I will not discuss in detail) are summarised in Table 3. This is similar in format to the error budget table. The calculated errors for each block are on the left, with the signal chain errors calculated as we did earlier. siliconchip.com.au Fig.4: using a difference amplifier as shown allows us to avoid using the very lowest part of the DAC’s output range (errors lie there). Circuit Block Error <at> 25°C Additional Voltage Current Error ±20°C Setpoint Setpoint Voltage Sensing Current Sensing 2 1 DAC 0.160% 0.010% 1 1 Setpoint signal conditioning 0.003% 0.030% 1 1 Summing node 0.010% 0.020% 1 1 Buffer 0.000% 0.000% 1 1 Current sensing 0.034% 0.131% Voltage divider 0.010% 0.020% 1 ADC 0.056% 0.080% 1 1 Voltage reference 0.003% 0.012% 1 1 1 1 1 1 Target error <at> 25°C 0.500% 1.000% 0.100% 0.100% Target additional error ± 20°C 0.250% 0.500% 0.050% 0.050% Total <at> 25°C 0.175% 0.209% 0.069% 0.093% Total additional ± 20°C 0.072% 0.203% 0.112% 0.223% Total error 5°C to 45°C 0.248% 0.412% 0.181% 0.316% Table 3 – we have met the targets for most errors but the voltage and current sensing circuits All the resulting 25°C signal chain errors are lower than or equal to the targets we set, but the temperature drift errors, and therefore the total errors, for the voltage and current sensing functions (shown in red) are not. Second iteration It is not at all unusual to find some problems such as this on the first pass. The process we have gone through – specifically, the detailed error calculation spreadsheet – makes it easy to spot the problem areas. These are the ADC’s ±0.08% temperature-dependent error, which contributes to both signal chains, and the current-sensing circuit’s temperature-dependent errors. The error calculation table shows us Australia's electronics magazine that ADC error is entirely due to the temperature dependency of the ADC’s gain, so the only real solution is to find a better one. The device I originally chose, the ADS1115, costs around $7 and has a gain drift of ±40ppm/°C, which I thought was appropriate for this design. The table shows us that we need to get the gain drift down to ±10ppm/°C, or ideally lower, if we are to make a meaningful improvement. The slightly fancier AD7705 is a good candidate. It features automatic calibration that all but eliminates fixed offset and gain errors, and an impressively low gain drift of ±0.5ppm/°C. This ADC costs about twice as much as the ADS1115, so we have to decide July 2025  51 Table 4 – by addressing critical areas, we have achieved our targets for all signal chains Circuit Block Error <at> 25°C Additional Voltage Current Error ±20°C Setpoint Setpoint Voltage Sensing Current Sensing DAC 0.160% 0.010% 1 1 Setpoint signal conditioning 0.003% 0.030% 1 1 Summing node 0.010% 0.020% 1 1 Buffer 0.000% 0.000% 1 1 2 1 Current sensing 0.034% 0.066% Voltage divider 0.010% 0.020% 1 ADC 0.019% 0.001% 1 Voltage reference 0.003% 0.012% 1 1 1 1 1 1 1 Target error <at> 25°C 0.500% 1.000% 0.100% 0.100% Target additional error ± 20°C 0.250% 0.500% 0.050% 0.050% Total <at> 25°C 0.175% 0.209% 0.031% 0.055% Total additional ± 20°C 0.072% 0.138% 0.033% 0.079% Total error 5°C to 45°C 0.248% 0.348% 0.064% 0.135% whether the improvement gained from the substitution is worthwhile or not. This is the type of judgement call you will frequently have to make, but with a detailed analysis such as this, we have the tools to decide where to spend money to get the best results. I decided to go for it – an easy decision, because this is just an exercise! The next area of temperature drift error is the current sensing circuit. The error tables show that most of the error comes from the instrumentation amplifier’s gain drift. Initially, I used an INA821 because we used it in an earlier article. However, we could replace it with the similarly priced AD8223. This has a significantly worse offset voltage (100µV vs 35µV), but much better gain drift (±2ppm/°C compared to ±35ppm/°C). Replacing the op amp reduces the current sense circuit’s temperature error from 0.22% to 0.08%. This illustrates another type of trade-off we sometimes encounter – trading off one specification against another in similarly priced chips. Building an error budget like I have done here is extremely helpful in working out which parameters really matter for your application. So, with the changes we have made in iteration 2 (Table 4), we have exceeded our target 25°C specifications by a factor of about two across the board. We have also met the total error over the temperature range across the board, even though the drift figure for the current sense circuit is still a bit higher than the target. This is another useful lesson – while we have to set targets for both fixed and variable errors, we can trade off underperformance in one with overperformance in the other. Conclusions With this, we have reached the end of the Precision Electronics series. If I have one closing message for the prospective precision circuit designer, it would be that a bit of time spent at the beginning with a pile of data sheets and a spreadsheet will be paid back many times over when it comes to building and validation of your designs. I am as keen as anyone to lay out a board, get my hands on a prototype and sit down at the bench, but I have learned from experience that if I skip the homework, I will pay for it later in frustration and avoidable rework! SC Songbird An easy-to-build project that is perfect as a gift. SC6633 ($30 plus postage): Songbird Kit Choose from one of four colours for the PCB (purple, green, yellow or red). The kit includes nearly all parts, plus the piezo buzzer, 3D-printed piezo mount and switched battery box (base/stand not included). See the May 2023 issue for details: siliconchip.au/Article/15785 52 Silicon Chip Australia's electronics magazine siliconchip.com.au