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Circuit Surgery Regular clinic by Ian Bell Logic levels – Part 2 L ast month, we looked at some basic concepts related to logic levels (logic voltages) including (briefly) the concepts of positive and negative logic, the input and output voltage ranges for 0 and 1 for logic gates, and noise margins, which indicate how much voltage shift can be tolerated without causing errors. We looked at the basic internal circuitry of TTL and CMOS gates, and at the history of digital technology that has led to the current situation where the majority of logic circuits are CMOS, but operate on a variety of different supply voltages (however, other technologies such as TTL are still available). The wide range of logic families and operating voltages leads to potential problems when attempting to interface ICs from different families, or those which operate on different supply voltages. This is a common problem in circuit design. For example, having selected a microcontroller we find that the peripheral devices most suited to a project operate at different supply voltages and have incompatible logic levels. Last month, we concluded with a brief discussion on a couple of simple techniques for interfacing old 5V LS TLL to HC CMOS; however, this does not cover all situations that occur with more-modern devices. As we mentioned last month, the best solution to interfacing circuits with incompatible logic levels is often to use one of the many logiclevel-translation ICs which are available. Logic-level translation is a common issue in commercial design, so the semiconductor manufacturers provide plenty of devices that deliver solutions. This month, we will start by looking at the general forms of translation circuit that are S u p p ly 1 S u p p ly 2 available and then consider some example devices from various manufacturers. The devices are simply examples; we are not attempting to recommend these above any others. Often, similar devices will be available from other manufacturers, and, as always, anyone requiring a device for a project should research what is available and select the most appropriate for that design. However, this article will provide you with some idea of what to look for in various circuit scenarios. As just mentioned, there are a number of different types of logic-level-translation circuit, some key examples are illustrated in Fig.1 to 5. In all these cases there are two circuits operating on different supplies (circuit 1 and circuit 2), where either circuit could have the higher supply voltage. In general, translation from a logic level on a low supply voltage to a higher one is called ‘up translation’. For a higher to a lower voltage it is called ‘down translation’. Unidirectional translators Fig.1 and Fig.2 show unidirectional circuits – this is where the signal travels in only one direction – in these examples, from circuit 1 to circuit 2. Unidirectional translators may have power supply connections to both supplies (dual supply) or just to the supply associated with the translator output (single supply). Translators requiring a single supply are convenient in situations where the physical implementation means access to the source circuit supply is difficult. Using dual circuit supplies potentially allows the designers of the translator chip to provide more optimal behaviour, such as low power consumption over a wide range of supply voltages. S u p p ly 1 The unidirectional translation circuit in its most basic form is simply a buffer (a logic gate with a single output, whose value is equal to that of its single input). Translation chips may have several parallel buffers for translating multi-bit data (or multiple individual signals). Functions other than simple buffers are available, including inverting buffers and buffers with tri-state outputs (to facilitate connecting the translator output to a shared data bus). Fig.1 and Fig.2 show a possible enable signal, which would be used by tri-state translators. Multiple-input logic gate translators (eg, NAND or NOR) are also available, which, for example, allow efficient combining of simple ‘glue logic’ with voltage translation using the same IC. Bidirectional translators Fig.3 and Fig.4 show bidirectional logic translators. Bidirectional signals are common in digital circuits, in particular in the context of shared data buses and serial peripheral interfaces, such as I2C, which are used for communication between microcontrollers and peripheral devices. There are two types of bidirectional logiclevel translators – those which have a direction control (Fig.3) and those which automatically sense the signal direction (Fig.4). The controlled-direction level translators may handle multiple bits under a single direction control. Automatic direction sensing is on a per-bit basis. Both types (with and without direction control) may have an enable input to ‘tristate’ (also called ‘three-state’ or ‘3-state’), that is disconnect or set to high impedance all the outputs (in both directions). Finally, in terms of general translator circuit types, there are ICs referred to as S u p p ly 2 S u p p ly 1 S u p p ly 2 D ir C i r cu it 1 L e ve l t r a n sl a t o r C i r cu it 2 E n a b le Fig.1. Dual-supply unidirectional level translator. Practical Electronics | February | 2020 C i r cu it 1 L e ve l t r a n sl a t o r C i r cu it 2 E n a b le Fig.2. Single-supply unidirectional level translator. C i r cu it 1 L e ve l t r a n sl a t o r C i r cu it 2 E n a b le Fig.3. Bidirectional level translator with direction control. 47 3 .3 V S u p p ly 1 L e ve S u p p ly 2 V C C C i r cu L e ve l t r a n sl a t o r it 1 C i r cu it 2 E n a b le syt R 1 10kΩ 3 .3 V e m s I/O g V C C R 2 10kΩ syt d 5 V e m I/O Q 1 Fig.4. Bidirectional level translator with automatic direction sensing. Fig.6. Basic direction-sensing bidirectional level translator. ‘application-specific level translators’. These devices are aimed, as their name suggests, at level translation in specific situations; for example, interfacing a processor to a SIM card. Typically, such situations require a mix of unidirectional and bidirectional level shifters and may also benefit from specific control signals to the level translator (eg, to implement a shutdown mode) – see Fig.5. voltage (3.3V here), so the MOSFET is switched on and the higher-voltage input is pulled down to 0V by the low drain-source resistance of the switched-on transistor. Thus, a logic 0 is seen by the higher voltage system, as required. The circuit in Fig.6 operates as follows for transmission of data from the highervoltage system to the lower-voltage system. If the higher-voltage system outputs a logic 1 (5V here), then assuming (given that the high side is transmitting) that the low-voltage system is not actively outputting a logic 0, the MOSFET will be off, so the input to the low-voltage system will be pulled up to the supply voltage (3.3V here) by R1, giving a logic 1 as required. When the higher-voltage system outputs a logic 0 (0V) the MOSFET substrate diode conducts (via R1), pulling the lower-voltage system’s input down to about 0.7V. This produces a positive gatesource voltage (of about 3.3 – 0.7 = 2.6V in this case), which is sufficient to turn on the MOSFET. The low drain-source resistance of the switched-on transistor is then able to pull the voltage at the input to the lower-voltage system even lower, resulting in a logic 0, as required. A problem with the circuit in Fig.6 is that low-to-high logic-level transitions can be slow. CMOS circuit inputs and the wiring connecting circuits together appears as a capacitive load on the outputs driving them. To change the logic level, this capacitance has to be charged or discharged and this occurs through some amount of output resistance, leading to an RC time constant that determines how fast the logic level can change. The pull-up resistors in Fig.6 are relatively large compared with the effective resistance of typical logic gate outputs, resulting in slow transition when the resistors are relied on to pull up the node to logic 1. Auto-direction bidirectional level translators Although various enhancements are used, the level translators in Fig.1 to Fig.3 can be implemented by circuits that are similar to standard logic gates and tri-state buffers. However, the circuits used for automatic direction bidirectional sensing can be somewhat different, so we will look a commonly used circuit of this type in more detail. The basic form of the circuit is show in Fig.6. This example shows one with 3.3V and 5.0V supplies, but the same approach can be used for other voltage translations, keeping the relative direction for low-tohigh voltage the same. The circuit can be built using discrete MOSFETs and resistors, but is commonly implemented in level-translation ICs, where various enhancements may be included. The circuit in Fig.6 operates as follows for transmission of data from the lowervoltage system to the higher-voltage system. When the lower-voltage system outputs a logic 1 (at 3.3V in this example), the MOSFET gate-source voltage is zero; so it will switch off. Under this condition the input to the higher-voltage system is pulled up to the supply voltage (5V in this case) by R2, and thus sees a logic 1 as required. When the lower-voltage system outputs a logic 0 (0V), the MOSFET gatesource voltage is equal to the lower supply C i r cu it 1 S u p p ly 1 S u p p ly 2 I/O I/O L e ve l t r a n sl a t o r 3 .3 V C i r cu it 2 C o n tro l Fig.5. Application-specific level translator – example with a mix of unidirectional, bidirectional signal translation and translator control signal from circuit 1. 48 L e ve R 1 V C C 3 .3 V syt e m I/O The problem can be overcome using the circuit shown in Fig.7. Here a logic-0to-1 transition on the side of the translator receiving an input triggers a one-shot (monostable) to produce a short pulse (typically in the order of a few tens of nanoseconds). The pulse activates a MOSFET switch, which temporarily bypasses the pull-up resistor on the side of the translator producing the output, increasing available current, and reducing the time taken to charge the capacitance of the output node. When using this translator circuit, care has to be taken not to reverse the signal direction while the one-shot is active, particularly to drive a logic 0, as this will create a signal contention and potentially high current flow. 5 V l t r a n sl a t o r The NLSV8T244 dual-supply unidirectional translator The NLSV8T244 is an 8-bit dual-supply unidirectional level translator from ON Semiconductor. The functional diagram and pin connections are shown in Fig.8. The device has two power supplies: VCCA for the input port (A), and VCCB for the output port (B). Both supply rails can be in the range 0.9V to 4.5V, allowing very flexible logic voltage translation. The NLSV8T244 has an active low enable input (OE) that can be used to set the outputs to a high-impedance state. The outputs also go high impedance if there is no supply on VCCB. As indicated by the circuit structure in Fig.8, the OE input is referenced to VCCB, but this and all inputs are over-voltage tolerant (with respect to the applied supply voltage) up to a maximum of 4.5V. The NLSV8T244 is available in a few package options, including SOIC−20 W, which has a 1.27mm (0.05-inch) pin spacing. There are various ‘244’ devices available from different manufacturers, with the same basic circuit structure and function, but different numbers of bits and supply voltage ranges. Various other dual-supply unidirectional level translators have a similar structure. LV1T series single-supply unidirectional translators The LV1T series of CMOS devices from Texas Instruments provides an example of single-supply unidirectional logiclevel translation. Each chip in the series 5 V l t r a n sl a t o r Q 2 Q 3 O n e sh o t g O n e sh o t s Q 1 d R 2 V C C syt 5 V e m I/O Fig.7. Direction-sensing bidirectional level translator with accelerated switching. Practical Electronics | February | 2020 1.8V to 2.5V 1.8V or 2.5V to 3.3V 2.5V or 3.3V to 5V V C C B V C C A O E Last month we mentioned that a potential problem with up translation is that the low-level input appears as a poor logic 1 or intermediate input level to the device operating on the higher supply. This can cause high current flow because both NMOS and PMOS transistors in the gate may switch on. The low threshold of the LV1T devices avoids this problem and current consumption is at or below the specified value for all valid CMOS logic 1 inputs for the various up translations. The LV1T series devices have 5V-tolerant inputs – the inputs can be at voltages above the supply voltage, up to 5.5V. This facilitates down translation, with the available level conversions being as follows, with, again, the ‘to’ voltage also being the supply voltage: 2.5V, 3.3V, or 5V down to 1.8V 3.3V, to 5V down to 2.5V 5V down to 3.3V T o p vi e w A 1 B 1 V C C A A 1 B 2 G n d 3 A 2 B 2 A 3 B 3 A 4 B 4 A 5 B 5 A 6 B 6 1 2 0 V C C B A 1 2 1 9 B 1 A 2 3 1 8 B 2 A 3 4 1 7 B 3 A 4 5 1 6 B 4 A 5 6 1 5 B 5 A 6 7 1 4 B 6 A 7 8 1 3 B 7 A 8 9 1 2 B 8 1 0 1 1 O E A 7 B 7 G N D A 8 B 8 Fig.8. NLSV8T244 pin connections and logic diagram. V C C 5 1 A B 4 2 2 Y Y Fig.9. Example LV1T device pin connections and logic diagram – the SN74LV1T00 NAND gate. provides a single logic function, together with logic translation – nine different single gates are available in the series – see Table 1. The data sheet descriptions for the NAND, NOR, AND and OR gates include the term ‘positive’ to indicate they are positive logic. As discussed last month, this means the logic 1 is at the more positive voltage level, which is the most common convention. These gates, and the exclusive-OR (XOR), all have two inputs. A possible issue with the LV1T series devices for some home constructors is its small size, although this is a common challenge with many devices which are only available in tiny surface-mount (SMT) packages. From the perspective of commercial designs, the point of producing single-gate ICs if of course the small space they can take up on a board compared with the older series where typically a package contained four 2-input gates. The LV1T series is available in a 5-pin SOT-23 package, which is only 2.9 × 1.6mm, or the even smaller SC70 package which is 2.0 × 1.25mm. The package layout and logic diagram are shown in Fig.9. The output logic levels of LV1T-series devices are typical for CMOS devices and Practical Electronics | February | 2020 are related to the supply voltage, which can be one of the standard voltages: 1.8V, 2.5V, 3.3V or 5V. These devices can perform a number of both up and down logic-level translations. The two-input gates in the LV1T series devices are able to translate two separate logic levels to a third output level (and either can be an up or down translation). Texas instruments suggest that a useful example application for this is in systems where a microcontroller has to monitor multiple power management ICs and needs LV1T up and down translation The LV1T devices achieve up translation because they are Table 1: Devices in the LV1T series of single-gate, designed with input-high logic single-supply logic-level translators levels lower than typical for Device Function the given supply voltage. For example, with a supply voltage SN74LV1T 00 NAND of 3.3V a typical CMOS gate SN74LV1T 02 NOR would have a logic 1 input level of at least 2.3V (about 0.7 of the SN74LV1T 04 Inverter supply voltage). However, the SN74LV1T 08 AND LV1T devices, when operating on 3.3V, have a logic 1 input SN74LV1T 32 OR threshold of about 1.0V. This SN74LV1T 34 Buffer allows a signal from a 1.8V logic output to be translated up to 3.3V SN74LV1T 86 XOR logic levels. The following up SN74LV1T 125 Tri-state buffer active-low enable translations are available – the second voltage is also the chip’s SN74LV1T 126 Tri-state buffer active-low enable supply voltage: P o w e r IC # 1 P G O O D 3 .3 V (1 .8 V ) 5 V C C 1 A 2 B Y P o w e r IC # 2 P G O O D (5 V ) 4 P G O O D (3 .3 V ) M C U 3 Fig.10. Example circuit from Texas Instruments in which a LV1T series AND gate translates two different logic voltage input levels (1.8V and 5V) to a third voltage output level (3.3 V). 49 O E Fig.11. Pin connections and logic diagram for the MC74LVX4245. 2 2 1 1 4 V C C I/O V L 1 2 1 3 I/O V C C 1 I/O V L 2 3 1 2 I/O V C C 2 I/O V L 3 4 1 1 I/O V C C 3 I/O V L 4 5 1 0 I/O V C C 4 N C 6 9 N C 8 T H R E E -S T A T E 2 T /R 3 A 0 2 1 B 0 T o p vi e w M C 7 4 L V X 4 2 4 5 4 A 1 2 0 B 1 5 A 2 1 9 B 2 6 A 3 1 8 B 3 7 A 4 1 7 B 4 8 A 5 1 6 B 5 9 A 6 1 5 A 7 V L V C C A 1 2 4 V C C B T /R 2 2 3 V C C B A 0 3 2 2 O E A 1 4 2 1 B 0 A 2 5 2 0 B 1 A 3 6 1 9 B 2 A 4 7 1 8 B 3 A 5 8 1 7 B 4 A 6 9 1 6 B 5 A 7 1 0 1 5 B 6 G N D 1 1 1 4 B 7 G N D 1 2 1 3 G N D B 6 1 0 1 4 to know when two supplies (other than its own) are up and ready to use. As was indicated last month it is common in modern systems for there to be multiple logic supply voltages. In such situations it is often necessary to correctly sequence their switch-on, or for the main processor to know when all supplies are up before attempting system operations. The example circuit is shown in Fig.10. MC74LVX4245 bidirectional level translator The MC74LVX4245 is a dual-supply, bidirectional, octal level translator with B 7 tri-state outputs. The logic diagram and pinout are shown in Fig.11. This device is from ON Semiconductor and is designed for interfacing between two tri-state buses operating on 5V and 3.3V logic. There are various ‘245’ devices available with the same basic circuit structure and function, but different numbers of bits and different voltage translations. The MC74LVX4245 has two 8-bit input/ tri-state output ports, A and B, associated with supplies VCCA (5V) and VCCB (3.3V) respectively. The T/R (transmit/receive) input is the direction control. When T/R is high, data is transferred from A G N D 7 Fig.13. Pin connections and logic diagram for the MAX3377E and MAX3378E (TSSOP14 package version). to B; when it is low, transfer is from B to A. The OE input is used to enable the output (when OE is low), whichever port (A or B) is currently the output. A high on the OE input puts both the A and B I/O pins into a high-impedance state. The control inputs can be operated at either the low or high voltage levels. ON Semiconductor recommend powering on V CCA before V CCB, as high supply currents can flow if the power-up is in the opposite order – refer to the datasheet for more details. The typical use of the MC74LVX4245 is shown in Fig.12. The device acts as a link between two shared tri-state buses operating on 3.3V and 5.0V. Devices from one bus can read or write data from the devices on the other. Typically, the processor would be on the lowervoltage bus, together with peripherals of a similar generation operating on the same voltage. Other peripherals (possibly older technologies) would be on the higher-voltage bus. MAX3377E and MAX3378E quad bidirectional auto-direction level translators Fig.12. Typical use of MC74LVX4245 as a bus transceiver for connecting two shared buses operating at different voltages. The MAX3377E and MAX3378E from Maxim Integrated are quad bidirectional automatic direction-sensing level shifters. Their pinout and logic diagram is shown in Fig.13. The MAX3377E uses a circuit similar to Fig.6 for each translator. The MAX3378E includes oneshots for accelerating logic switching and each translator has a circuit similar to Fig.7. For both chips, the low-voltage (VL supply pin) side can be from 1.2V to 5.5V and the high-voltage side (VCC pin) can range from +1.65V to +5.5V. There 50 Practical Electronics | February | 2020 B u s A 5 .0 V D i r e ct i o n O u tp u t e n a b le B u s B 3 .3 V + 1 .8 V + 3 .3 V 0 .1 µ F 0 .1 µ F V C C V L + 1 .8 V syt e m co n t r o l l e r 1 µ F + 3 .3 V syt e m co n t r o l l e r T H R E E -S T A T E Using level translators M A X 3 3 7 7 E / M A X 3 3 7 8 E D A T A I/O V L 1 I/O V C C 1 I/O V L 2 I/O V C C 2 I/O V L 3 I/O V C C 3 I/O V L 4 I/O V C C 4 D A T A Fig.14. Typical application circuit for the MAX3377E and MAX3378E. S u p p ly 1 S u p p ly 2 V L V C C T H R E E -S T A T E M i cr o p r o ce so r V L R V H M A X 3 3 7 3 E R P P I/O V L 1 I/O P P V C C 1 R I2 C p e r ip h e r a l S D A V L V H R P P I/O V L 3 I/O P P V C C 3 configuration, external pull-up resistors (RPP) may be required (the internal pull-ups are 10kΩ) – refer to Maxim’s documentation for details on resistor value selection. S C L Like all digital ICs, level translators should have supply decoupling capacitors placed close to them on the circuit board. Dual-supply level-translation ICs should be provided with supply decoupling capacitors on both supply pins. Supply decoupling capacitors filter supply noise and help prevents glitches, which may result in incorrect operation. A typical value for these capacitors is 0.1µF, but device data sheets may make specific recommendations. As with all digital circuit boards, power supplies must be connected via low-impedance routes, typically as wide areas of copper known as ‘power and ground planes’. If level translators are used to provide interfaces to circuits that are not on the same board then it is usually a good idea to provide some form of protection from transient voltage surges. This is particularly the case if I/O connectors will be plugged and unplugged by users. Protection is typically provided by adding reverse-biased diodes between the I/O and both supply and ground, or by using transient voltage suppression (TVS) diodes (bidirectional avalanche breakdown diodes) connected between the I/O and ground (see Fig.16). The protection devices should be placed close to the I/O connector and the route between the translator chip and I/O connector should be as short as possible to reduce both emission of, and susceptibility to, radio interference. Fig.15. Level translation of an I2C bus using a MAX3373E. is a requirement that VL is less than VCC by at least 0.3V, but this does not have to apply during power-up transitions. These devices are available in TSSOP, TDFN and the very small micro (µ) chip-scale package (UCSP), which has ball grid array type connections under the package – see: https://en.wikipedia.org/ wiki/Ball_grid_array Both devices have an active-low tri-state control input (THREESTATE) pin) which puts all the I/O pins into a high-impedance state and reduces the supply current to the chip to less than 1µA. This works by disconnecting the internal 10kΩ pull-up resistors (see Fig.6 and Fig.7) from the supplies. A typical application circuit for the MAX3377E and MAX3378E is shown in Fig.14. This example shows a 1.8V system controller (eg, microcontroller) communicating with a 3.3V system, but other voltage combinations would have a similar structure. Maxim also S u p p ly 1 S u p p ly 2 produce a dual C o n n e ct o r V C C version MAX3378E, the MAX3373E, 0 .1 µ F 0 .1 µ F G N D which is suitable for V C C V L level translation of I2C D 1 IO A 1 IO B 1 buses. An example circuit is shown D 2 IO A 2 IO B 2 in Fig.15, where a microprocessor on a T V S T V S relatively low supply voltage (Supply 1) is C h a si s g ro u n d connected to a highersupply-voltage I 2 C Fig.16. Example circuit of level translator peripheral IC (such handling off-board signals via an I/O connector. as an ADC or DAC) TVS diodes provide protection; also note the via the MAX3378E. Depending on the bus decoupling capacitors. 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