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By Dr Hugo Holden Commodore PET Diagnosing a Vintage Computer – the Display System Troubleshooting vintage computers that use dozens (if not hundreds!) of separate logic ICs can be very difficult unless you know exactly how they work. This article will explain in detail how the PET’s video hardware works, to make diagnosis and repairs much easier. T here are many model variations of Commodore PET computers (the predecessor to the famous Vic 20 and Commodore 64). This article refers to a type of motherboard known as “The Dynamic PET”, characterised by using 4116 dynamic memory (DRAM) ICs and 2114 static video RAM (SRAM) ICs. Also, it does not contain a CRTC (cathode ray tube controller IC). Therefore, it may or may not exactly match your particular PET. This is the only PET I own, so I am not in a position to perform a similar analysis on the other types/models. The intention of this article is to describe how this PET’s character address generator (CAG) system works, and to provide the operating theory and data on it, to help technicians diagnose and repair it. My unit worked well, so there was no specific fault I needed to fix. But I was curious about the design and wanted to know more about how it works. A detailed operating theory is always helpful in making an accurate diagnosis of a faulty circuit. The worst approach is random and haphazard guessing based on hunches and the absence of test data. Especially if that leads to unnecessarily removing good vintage ICs from the PCB and risking PCB damage. To assist in probing this system, I made a pulse-counting logic The Commodore PET CBM Model 3008, released in 1979, was a successor of the PET 2001 (pictured opposite). 58 Silicon Chip probe to verify that brief pulses on various lines were all present and that no narrow events in a pulse stream had been missed on an oscilloscope screen. This logic probe circuit design was published in Circuit Notebook (December 2025 issue; siliconchip.au/ Article/19378). One reason for using this probe is that some of the pulses in this circuit are extremely narrow, in the region of 100-300ns, and relatively infrequent. This renders them not easily seen on an analog oscilloscope (and maybe even some low-end digital scopes at longer timebase settings). They are either not frequent or long enough to excite the screen phosphor on a typical analog ‘scope, or are missed completely by a too-low sampling rate on some digital ‘scopes. The pulse-counting probe won’t miss them, though. More on the Commodore PET The PET computer, in its various forms, has now become quite a collectible item in the world of vintage computers. There are several reasons why. One is, as the photo shows, it has a fantastic retro look to it. It also has a built-in BASIC interpreter, which is a relatively easy language for a programming novice to learn. The other reason is that the PET was gifted with a very nice cathode ray tube (CRT) video display unit (VDU). The charm of a real CRT seems somewhat unmatched by a modern flat panel display and is inescapably attractive to many. Still, that might depend on your age. In many vintage computer systems like the PET, no raster scan oscillators are present in the VDU; timing signals from the computer take their place. They are then called horizontal and vertical drive pulses rather than sync pulses. This creates the opportunity for malfunction and damage in the VDU, especially if the horizontal drive pulses become abnormal in frequency or duty cycle. That is because the horizontal scan output stage in the VDU also siliconchip.com.au Fig.1: the contents of a typical PET computer’s character ROM. The exact contents vary between models and generations. Source: http://cbmsteve.ca/ cbmchr/index.html generates the EHT (extra high tension) voltage and auxiliary voltages for the CRT. In the Commodore PET VDU, the video signal has no shades of grey; it is simply on or off. The VDU therefore only has a brightness control. A contrast control had no application. In a typical composite VDU, the analog value of the video component of the composite signal controls the CRT’s beam intensity, and the magnitude of those excursions is controlled by a contrast control. A contrast control is essentially a video signal amplitude control. In the non-CRTC (CRT controller) PET discussed here, the horizontal & vertical drive pulses, and the video pulses, are derived from some very creative logic circuits using 74-series TTL ICs. As new PET models emerged, Commodore (as many did) switched to using a CRTC chip. In this case, the generation of horizontal and vertical pulses is performed by one IC, eliminating the complex array of 74-series TTL-based circuits and leaving the one LSI chip to do all the heavy lifting. The PET character address generator (CAG) In the PET, the generation of the horizontal and vertical drive pulses and the video pulses is essentially independent of the 6502 CPU. The CPU simply writes data to a part of memory (video memory), which is then used to generate the necessary signals. The video memory buffer is based on a pair of 2114 1024 × 4-bit SRAM memory ICs. Together, these hold a byte for each character on the screen; the screen has 25 rows of 40 characters, so 1000 total character ‘slots’ Each byte value is the address of the character to be generated in the character ROM, similar to the ASCII scheme. Commodore’s scheme was known as PETSCII or CBM ASCII. The 1000 screen locations (from the perspective of the computer user) are siliconchip.com.au stored at decimal memory addresses 32768 through to 33767. To see characters on the VDU at all possible screen address locations, the CAG needs to scan the addresses of every one of the 1000 screen character locations in the 2114 SRAM several times per screen refresh (eight times, in fact, because the horizontally scanning beam crosses each character eight times). A POKE command can be used to inject a byte value into any specified memory location. In BASIC, if the command “POKE 32768,1” is issued, the letter “A” will appear in the first screen character location, in the upper-left corner of the CRT’s display area. That’s because A is in the second character ROM slot (the first slot is numbered 0). If the 2114 video RAM chips are removed from the PCB and their outputs held to +5V with pull-up resistors, a checkerboard will appear on the screen, because every character address location is seen as having the same binary content of 255 (that is, if the video circuitry beyond the 2114 and the character address generator is working). POKEing a zero value, or tying the 2114 chip output pins low, results in the “<at>” character (stored in character ROM slot zero) instead. These tricks can have some applications in troubleshooting the circuitry. Fig.1 shows the typical set of 256 characters in ROM, although not all PET computers will have identical character sets. While the user accesses the display RAM at addresses 32768 to 33767, the 10-bit counter in the character address generator (CAG) circuit uses addresses from 1 to 1000, represented in binary form. The analysis of the CAG might have been easy if it were just a counter, free to count as a binary counter does, over some range. However, its counting sequences are interrupted, manipulated and controlled by various system pulses, such as the HORZ DISP ON pulse, NEXT pulses and RELOAD pulses. These will be untangled in this article. Untangled, because it is a system of pulse feedback and resets, where the logic conditions of the CAG and some other sub-circuits are detected to create special reset pulses, which after deployment, annihilate the logic conditions that created them, in time frames of 300ns or less. To summarise, the CAG has two roles: first, to generate the control signals that cause the CRT beam to scan the display, and second, to generate the video modulation signal that causes the characters in display RAM The first Commodore PET to be released was the Model 2001 in 1976. Source: Rama – https://w. wiki/Hc9Q (CC-BYSA 2.0 Fr) Australia's electronics magazine 59 to appear on the screen in the correct locations. Getting started It is a good idea to begin with a diagram of the video screen to see how scanning lines and time are allocated (Fig.2). Two very important pulses are the HORZ DISP ON pulse and the VIDEO ON pulses. These define the surface area on the video screen where characters are displayed. The temporal width of a character cell is 1μs as the CRT beam scans the screen from left to right. Characters are made of eight pixels horizontally, with eight of those stacked vertically. The illuminated pixels of a character may not fill the whole cell, because space is often left beside and below it to space the characters apart, as shown in the example A character in Fig.2. However, graphics characters (lines, boxes etc) often use the full width and height. of the active video time (the horizontal retrace time), the CAG is paused and the CRT’s beam current is disabled. So video data only controls the CRT’s beam when the HORZ DISP on pulse is high for 40μs per line. The horizontal scan system The vertical scan system The horizontal scan system causes the electron beam to scan horizontally from left to right, then fly back to the left, at 15.625kHz. As the beam is sweeping the screen, when it reaches the active video area, the HORZ DISP ON signal goes high. During this time, the CAG is active and pixel data is presented in the video signal to render the character cells. The rest of the time, during the horizontal blanking periods on either side The vertical scan system is responsible for the CRT’s beam moving from the top of the screen to the bottom or the horizontal scan lines would simply scan on top of each other. The vertical retrace, where the beam moves from the bottom of the raster scan, up to the top of the raster scan, takes 1.28ms, which is the equivalent of the time taken for 20 horizontal scan lines. The video signal holds the electron beam off for the vertical retrace time and for an additional 20 scan lines time before the active vertical component of the video time, defined by the VIDEO ON pulse. After that, the CRT beam is again extinguished for another 20 lines time before vertical retrace begins. Then the counters are reset and it starts scanning the active video area of 200 scan lines. For each scan line, the CAG is active for 320 clocks, meaning the active area has a resolution of 320 × 200 pixels. Each character to be displayed consists of 8 × 8 pixels, meaning that 320 × 200 pixel area shows 1000 characters (40 × 25). After the 200 active lines are scanned, the electron beam switches off and another 20 lines are scanned (the bottom vertical blanking area). Then vertical retrace is triggered and the beam ‘flies back’ to the top of the screen while off. That consumes another 20 horizontal scan periods. That means that each screen refresh is a total of 260 horizontal scan periods (20 + 200 + 20 + 20), so with a horizontal scan frequency of 15.625kHz, the vertical scan (screen refresh) rate is 60.096Hz (15.625kHz ÷ 260). Fig.2: how the PET’s CRT screen is scanned. During the horizontal and vertical flyback periods, the CRT beam is inactive. In the raster scan zones, the ‘beam’ is scanning the screen, but it is not active as it is outside the display area. Character generation Fig.3: this shows the character addresses and how the lines are counted using the H11 IC. The CAG steps through the character address sequence 1-40 eight times, then 41-80 eight times and so on, until the last row of characters, at addresses 961-1000. During the 200 active scan lines, once the electron beam finishes scanning the left horizontal blanking (raster) area, the CAG becomes active. What it needs to do during this time is determine, for each of the 320 × 200 pixels, whether to drive the CRT beam on or off, making that pixel either bright or dark. The pattern of 8 × 8 bright and dark Australia's electronics magazine siliconchip.com.au 60 Silicon Chip Fig.4: a block diagram of the PET’s character address generator, with some extra components shown that affect its operation. It is responsible for driving the CRT screen, reading characters out of display memory, using those to look up the character ROM and displaying those characters on the screen by modulating the CRT beam. pixels in each of the 40 × 25 cells shows a single character (letter, number, punctuation, graphic pattern etc). Do to this, the CAG must: 1. Keep track of which character cell (1-1000) it is currently scanning. 2. Fetch a byte from SRAM for each character cell that indicates which character to show in this particular cell. 3. Keep track of which line within that cell (1-8) it is currently scanning. 4. Using the byte from SRAM and the line number, read a byte from the character ROM that determines the pattern of eight pixels to show for the current row of the current cell. 5. Send that byte, one bit at a time, to the CRT on/off signal to generate the required pixel pattern for this 8-pixel strip. To achieve this, the character cell address (1-1000) needs to start at 1 in the top-left corner, then increase by one for every eight pixels output, reaching 40 in the top-right corner. Then, for the next line (the second row of these characters), it needs to repeat the 1-40 count. It repeats that count eight times for the eight lines of those characters. On the next line, it counts from 41 to 80; the next row of characters. This pattern repeats, counting the same 40 values for each set of 8 lines, until it reaches the final row siliconchip.com.au of addresses 961-1000. After that, it’s in the vertical blanking period as described above. For each set of eight scan lines, the only thing that changes is the 3-bit counter that cycles through 0...7 to select the appropriate line of each character ‘drawing’ from character ROM. Otherwise, the CAG’s operation is identical for each set of eight scan lines. On the 8th line of each set, the counter re-loading is skipped, so the address starts the next line at a value 40 higher than the previous line (see Fig.3). Character generation That just leaves the question of how the electron beam is modulated on each active scan line. At the start of each character, one byte is read out of the display SRAM at the current character address. That byte forms the upper 8 bits of an 11-bit address into character ROM, with the lower three bits being the current line number, 0-7. That gives a single row of 8 pixels to light for the current character. That byte is loaded into a shift register, and the output of the shift register controls the electron beam. That register is shifted by one bit for each subsequent pixel, at a rate of 8MHz. After eight shifts, the character address is incremented by one, the next 8-pixel Australia's electronics magazine pattern is loaded from character ROM, and that byte is loaded into the shift register. This process repeats for the 40 characters and 320 active pixels of each scan line. The CAG The CAG’s labelled outputs, bits 1 (RA1) to 10 are shown in red in Fig.4. Another box in the diagram is the 4-state machine, which will be examined later. The diagram also indicates where the three signals to drive the VDU originate: VERT(ICAL) DRIVE, HORIZ(ONTAL) DRIVE and VIDEO OUT. This simplified block diagram has been created to show how the 10 bits of the CAG sequentially select a specific ‘cell’ or byte of data at a screen address location in the 2114 video RAM ICs. One line of the corresponding character in character ROM is clocked out of the shift register IC, E11, to create the video signal for the VDU. The purpose of the MUX ICs, F3, F5 & F6, is to allow the CPU to select the addresses of the video RAM on the other half of the clock cycle of CLK1 and therefore be able to ultimately read or write any byte value from the data bus BD0...BD7 into or out of any one of the 1000 screen character locations via the READ and WRITE latches of ICs E7 and E8. September 2026  61 HORZ DISP ON 40μs 1 3 39 Video latch “sample points” 2 4 RA1 40 there are 40 characters per row on the PET’s screen Figs.5 & 6: the left scope shows the video latch acquiring characters from display RAM to be shown on the screen. That happens 40 times for each of the 200 scan lines that cover 25 rows of characters. Right: the same waveforms in Fig.5 zoomed in for a closer look. To display the data represented by memory cells of the 2114 on the VDU screen, it is latched by IC F9 and fed to the character ROM as address values. Only seven bits are latched for the character ROM, because the A10 address input on the character ROM is used to select ‘GRAPHIC’, the alternative lower-case character set that lives in the character ROM. The 8th bit of data (LSD7) out of the F9 latch is used to invert the data clocked out of the shift register E11, so that the characters appear as dark on a light background (‘inverse video’). Therefore, byte values of 128 or over result in the same number or character as those specified by 0 to 127, but they are simply inverted video. Normally, pin 19 (A10) of the character ROM is low, which selects the upper-case characters. If you run the command “POKE 59468,14”, it toggles the pin high, and lower-case characters are used instead, from the upper half of character ROM (as seen in Fig.1). If you run “POKE 59468,12”, it goes back to upper-case. The data is latched by IC F9 at a time late in the high part of the RA1 pulse, which forms the least significant bit of the 10-bit CAG. The reason is to make sure that the output data in the 2114 is stable after it has been presented with the new address of each character cell by the CAG. The scope recording in Fig.5 shows the timing of 8-bit latch F9 latching (effectively sampling) the output data from a memory cell in the 2114s. If the pulse-counting logic probe tip 62 Silicon Chip is connected to RA1 and it is gated by HORZ DISP ON, the probe counts a hexadecimal value of 14 (20 decimal) as it is counting the 20 rising edges of RA1. Using the ‘scope to look at RA1 and the VIDEO LATCH pulses fed to F9 gives a clearer view of that timing (Fig.6). NEXT pulses and digital circuit loops In essence, the four 100ns-wide NEXT pulses are a form of RESET pulse. However, they serve other functions too. These pulses are the key to the operation of the entire CAG circuit, despite being the more difficult pulses to view with a ‘scope than any others in this circuit. These pulses are responsible for switching the logic between the four main states: vertical retrace/flyback, pre-display raster scan, scanning the active video area, and post-display raster scan. Raster scan refers to when the CRT beam scans the part of the display that is outside the display area (perhaps even hidden behind a bezel). No characters are displayed there, but the beam must still traverse those areas. The PET’s NEXT pulses are derived from the pulse streams generated by the 20 LINES and 200 LINES detector circuits. When combined, and with some other logic signals, these detect the end of normal scanning, causing the CRT beam to be switched off, the vertical flyback to start and ultimately the resetting of the CAG, ready to draw the screen all over again. There are four digital reset loops Australia's electronics magazine involved in generating the NEXT pulses. At this stage, we need to refer to the full CAG circuit diagram, Fig.7. The most obvious ‘circuit loop’ in Commodore’s circuit is the CAG’s upper 8 bits (outputs) being fed back to the latch inputs of G3, then those latch outputs being fed to the CAG’s jam load inputs on ICs F2 and F4. This arrangement causes the character cell counter to reset at the start of the first seven of each set of eight scan lines, as noted earlier. The other loops involve the NEXT pulses. These can be seen from looking at where the NEXT pulses are fed, because in each case, the feedback results in a change to the digital logic that generated the NEXT pulses. 1. The NEXT pulses are fed to the CAG’s F2 & F4 clear inputs, clearing the upper eight bits of the CAG when they are triggered. 2. The NEXT pulses are fed via H5’s pins 12 & 11 to latch G3. These make the latch transparent, and it acquires (remembers) the zero condition created by the clearing of F2 and F4 by the NEXT pulse being applied to the F2/F4 counters’ clear inputs. 3. Counter H11 is reset (cleared) by NEXT pulses. RA9 contributes to the pulse stream in the 20 LINES detector and ultimately the NEXT pulse extracted from that pulse stream is a reset pulse, which not only resets the CAG but also the three-bit counter, H11, that created the RA9 pulse. 4. The 20 LINES pulse stream can only exist in the VIDEO OFF time, which is the complement of the VIDEO siliconchip.com.au Fig.7: the main part of the CAG circuit. Signals with numbers in brackets go to another part of the circuit. F2, F4 & H11 are four-bit counters, G3 is a latch while F3, F5 & F6 are quad two-way multiplexers. G6 and G8 are flip-flops, while the functions of the other ICs should be evident from their symbols. The quad NAND gates like H5 may be shown as NAND or NOT-OR gates as those functions are logically equivalent. ON time, created by NEXT pulses controlling the 4-state machine (more on this later). The first NEXT pulse is generated by the 200 LINES detector, and this also controls the state machine to create the VIDEO ON pulse. In summary, the latch G3 and CAG logic states are modified by the NEXT pulses, and these modify the production of all pulses derived from the CAG, including the NEXT pulses themselves. You can think of this as siliconchip.com.au a sort of oscillator, as it goes through the same set of states endlessly while powered. The NEXT pulses get formed by flipflop control into four uniform 100ns pulses. This introduces a small delay between the leading edge of the gated pulses and the leading edge of the NEXT pulses themselves. The result is that the logic state detected by the 200 LINES and 20 LINES detector circuits, when Australia's electronics magazine the precursors of NEXT pulses are detected, can persist a little longer than they otherwise would if they were used the reset the CAG directly. This causes the production of the NEXT pulses to become synchronous with the rising edge of the VIDEO LATCH pulse. This pulse clocks the flip-flop that issues the four NEXT pulses. The NEXT pulses are difficult to see on the ‘scope because they are only 100ns wide and they come in groups September 2026  63 VIDEO ON PULSE high for 12.86ms 3.84ms VIDEO OFF vertical scale 2V/cm both channels The 4 NEXT pulses each 100ns wide Storage scope recording of next pulses TEK 464 scope Fig.8: it’s best to use a high-speed digital ‘scope to probe the NEXT pulses (and some other pulses in this circuit) as they are very brief at ~100ns and can easily be missed on an analog ‘scope. lines are the active video lines where characters are presented on the screen while HORZ DISP ON is high. Although it seems unimportant in the scheme of things, because the NEXT pulses are so narrow compared to the VIDEO ON & OFF timing, it pays to note that the 74LS107 flip-flops are a master/slave type. They change state very shortly after the clock pulse driving them falls low. Fig.10 shows this. This has implications in pulse counting, where the VIDEO ON pulse might be used as a gating signal for the pulse counting logic probe, or where it might be used as an oscilloscope trigger. The pulse-counting probe mentioned earlier will count three NEXT pulses if gated to count in the VIDEO OFF time (when the VIDEO ON pulse is low). This is because the first NEXT pulse rising edge occurs at the trailing end of the VIDEO ON time. If the pulse-counting probe is gated to count for the VIDEO ON time instead, with NEXT pulses feeding the probe tip, it will count one pulse. The CAG in detail Fig.9: this state machine is responsible for disabling the CRT beam and triggering flyback at the end of the vertical scan period. of four at a relatively infrequent interval of around 16.64ms. The energy delivered to the screen phosphor on a standard oscilloscope is barely enough to see them. A storage ‘scope or high sampling rate digital ‘scope is better to view them. A recording is shown in Fig.8. The 4-state machine This circuit, a two-bit counter, is a well-known circuit in the field of amateur radio. It is a quadrature pulse generator, sometimes used for SSB radios. It produces a form of Gray code, where the counter moves through a series of values that differ only by one bit at a time (in this case, 00, 01, 11, 10 and then repeating). 64 Silicon Chip If it was continuously clocked, it would produce pulses in quadrature, but in this case, its operation is interrupted every 16.64ms and it is clocked only by groups of four pulses to produce the VIDEO ON pulse for the CAG and the VERT(ICAL) DRIVE pulse for the VDU. The later VIDEO ON pulse is responsible for gating the second, third and fourth NEXT pulses. That is due to the digital reset loops in the CAG circuit. When the VIDEO ON pulse is low, the four NEXT pulses appear to divide that time into three 20-line or 1.28ms boundaries. From the 4th NEXT pulse to the first one of the following group of four NEXT pulses, it is 12.8ms or 200 horizontal line periods. These 200 Australia's electronics magazine The clear (CLR) inputs of the 74177 counters are active low (they are labelled CLK in the original Commodore diagram for some reason). The jam load control inputs on pin 1 are also active low. While HORZ DISP ON is low, counters F2 and F4 are loaded with whatever values are held in 8-bit latch G3. Each flip-flop within the 74177 is forced to a preset or cleared condition (depending on whether the load bit is high or low). During this ‘load’ time, they cannot count. Latch IC G3 is made transparent when its pin 11 input is high. This means that its outputs simply follow its inputs. It latches (remembers) the current value feeding the latch when pin 11 goes low. Bits 3 to 10 of the CAG loop back to feed the latch inputs. Starting with what could be called line 1 at the top of the screen, the first character location and the start of the first line of that character is character #1. Immediately prior to the first active video scan line, RA1 is high and all the other bits of the CAG, bits 2 to bit 10, are low. This is because when HORZ DISP ON was off (low), this cleared flip-flop G6, making bit 2 low. Bits 3 to 10 are also low at this time because siliconchip.com.au both of the 74177 counters, F2 and F4, were cleared by the 4th NEXT pulse via H5’s pins 12 & 11. At this starting time of the first line of the 200 line character block, the data in the G3 latch is zero, because the 4th NEXT pulse made the latch transparent for 100ns, via H5’s pins 12 & 11, ‘remembering’ the zero condition of the cleared F2 and F4 counters at that time. So, initially: 1. The binary value of the CAG is 1, because RA1/bit 1 is high and all the latches are cleared. 2. The Q output of flip-flop G6 (pin 3), bit 2 of the CAG, is low (0). 3. The value held in 8-bit latch G3 is low for those bits. 4. All outputs of 74177 counters F2 and F4 are low. 5. The 3-bit binary counter H11 (shown added to the CAG circuit) also starts at zero because it was cleared by the NEXT pulse too. This counter is clocked by the HORZ DISPLAY ON pulse when it falls low at the end of active horizontal video time. G11 decodes the 3-bit count of H11 to create a RELOAD pulse that deploys on the 8th repeat of the screen address row, for all 25 rows of characters. When HORZ DISP ON goes high, the CAG then begins counting on negative edges of RA1 pulses, which changes its state every 1μs. Fig.3 shows how the CAG counting This board has the CPU, RAM, ROM and most of the logic ICs that run the computer. it’s laid out in a grid so letter/number pairs are used to refer to specific chips. siliconchip.com.au Australia's electronics magazine Fig.10: the relationship between the very brief (100ns) NEXT pulses and the VIDEO ON signal. starts on the left-hand side of line 1. The counting continues along the first line until the total count is 40 decimal, indicating that one row of all 40 columns of characters has been generated. At that point, HORZ DISP ON goes low, clearing bit 2 of the CAG and activating the jam load inputs on counters F2 and F4, and the counters stop. Since the load value from latch G3 is zero at this time, the CAG total count (the whole 10 bits) returns to 1. The counts on the second line are thus a duplicate of the first. This occurs until 7 lines in total (most of one character row) have been completed. On the 8th line, things change. 3-bit counter H11 is incremented at the end of a line, when HORIZ DISP ON falls low. At the start of the 8th line, H11, has a binary value is 111. To generate a RELOAD pulse, it also requires that the HORZ DISP ON signal is HIGH (due to gate G11). This condition occurs at the start of the 8th line. Therefore, for the whole of the 40μs of the 8th line’s active time, the RELOAD signal is low, making latch G3 transparent so it follows the outputs of counters F2 and F4 over that time. At the end of that 8th line, the HORIZ DISP ON signal goes low, which jam loads the last count value into the counters F2 and F4. The HORZ DISP ON pulse going low clocks the 3-bit counter over to state to 000 and HORZ DISP ON terminates the RELOAD pulse because of gate G11. When latch G3 is released from being transparent, it remembers the final value it had, which was the value of the upper eight bits of the CAG, at the end of the 8th line, ie, 40 decimal. When HORZ DISP ON falls low at the end of that 8th line, this takes the jam load inputs of counters F2 and F4 low; the counters are updated (loaded) with the latched value of 40, hence for the next block of eight lines, lines 9 to line 16, the CAG count starts at 41. September 2026  65 The point of all this is that the CAG has to start at the same value for each set of eight lines as it’s rendering the lines of the same set of characters. It runs from 1 to 40 eight times, then 41 to 80 eight times, then 81 to 120 eight times and so on. While the counts along the first eight lines are being repeated, the output of 3-bit counter, H11 is keeping track of which line within each character is being output (0 to 7), with the three bits being fed into the LSBs of the character ROM, to select the appropriate row of the character to send to the display. The CAG holds the address of a particular screen character cell in video memory. Seven bits of the byte content of that cell are used as the address for the upper seven address lines of the character ROM, A3 to A9. The lower 3 ROM address lines get scanned along the individual eight bytes by 3-bit counter H11, to make up the particular character. Ultimately, one row of each character is presented on the VDU screen via shift register E11 (which serialises it), and it is clocked out along the horizontal scan line to produce the appropriate pixel pattern. Generating the vertical video timing The CAG also produces the vertical video timing via the 4-state machine, which generates the VIDEO ON timing and the VIDEO DRIVE pulse for the VDU. The NEXT pulses are derived from the 200 LINES and 20 LINES pulses. Although the CAG is only able to count when the HORZ DISP ON pulse is high, the CAG is free to keep counting during the vertical interval when the VIDEO ON pulse is low (provided HORZ DISP ON is high). In other words, it still counts in the vertical time window when no characters are being displayed on the CRT. This time window outside the character display time corresponds to the 20 lines of time (1.28ms) prior to the active video area, the 20 lines of time after the active video area and the 20 lines of time for the vertical retrace. During this non-character display part of vertical counting time, which could be called the ‘VIDEO OFF’ time, the same once-per-eight-line RELOAD pulse is applied from the 3-bit counter H11 to the CAG system. It counts in blocks of eight lines, going over the same addresses, just as it does to generate the screen character location addresses in the VIDEO ON time. The 200 LINES pulses are created by gating five of latch G3’s output bits. Since the latch holds character address 961 in the first of the seven lines of the last character block, no 200 LINES pulses occur. Pulses on H5’s pin 6 occur only on the 8th line of a character block, and only on the last row of 40 characters on the 200th line, when the count has reached 968 or over. This is because G2 (pins 9, 10, 12 & 13), I1 (pin 9) and H5 (pins 4 & 5) gate the upper four latched bits and bit 4 of the CAG address – see Fig.11. When the G3 latch is made transparent by the RELOAD pulse, as it is on the 8th line of every block, the latch outputs correspond to the CAG’s upper 8 bits. Bits 4, 7, 8, 9 and 10 of the latch output are fed to the inputs of those gates. The 200 LINES pulse at pin 6 of H5 is generated when all five cited CAG bits are high. Adding their values up, 512 + 256 + 128 + 64 + 8 = 968. So, at character address 968, on the last line of the bottom row of character cells, the 200 LINES line goes low. Pulses then appear there with a width of 8μs on pin 6 of H5 because bit 4 of the CAG address is going low and high every 8μs, while bits 7 to 10 remain high, as shown in Figs.11 & 12. At the end of the 200th line, the CAG does not return to 961; the first NEXT pulse that is generated by the 200 LINES detector results in a reset of the CAG to binary value 0000 0000 01. The NEXT pulse is produced before the ‘time is up’ for the following CAG address value after 1000, which is reset to an address of 1 by the NEXT pulse before a 2μs time frame. The address of 1000 in the CAG at the end of the 200th line is allowed to persist for longer than most of the address states, for around 1.84μs (rather than the usual 1μs) but the CAG address has already been reset to 1 before the end of 2μs corresponding to the next address state for the CAG. The 8μs pulses that lead to the NEXT pulse precursor are fed to the D input of flip-flop G8 from HORZ DISP OFF pulse, 20 LINES and 200 LINES signals via gates H5 & G1. Comparing the last Fig.11: the 200 LINES signal first goes low on character 968, but because RELOAD is low and HORIZ DISPLAY ON is high, it has no effect until just after character 1000 has been fully displayed. 66 Silicon Chip Australia's electronics magazine siliconchip.com.au 1.8μs Pin 6 H5 Pin 6 H5 1.5μs 100ns Pulse terminated by B02H Pin 11 H5 Pin 11 H5 NEXT pulse approx 100ns wide Fig.12: the timing of the NEXT pulse at the end of the main display period relative to pin 6 of IC H5. low-going pulse on 200 LINES at pin 6 of H5 with pin 11 of H5, which controls latch G3, gives even more timing detail – see Fig.12. Not only does the NEXT pulse (inverted by gate H5 at pin 11) allow latch G3 to become momentarily transparent with the new CAG address value, it also clears counters F2 and F4. Fig.13 shows the first 100ns-wide NEXT pulse; it appears to straddle the rising edge of the last 200 LINES pulse. This is because flip-flop G8 is cleared by pulse B02H, which falls low around 40ns afterwards. The leading edge of the first NEXT pulse is created by the leading edge of the VIDEO LATCH pulse, which clocks HIGH data to the Q output of flip-flop G8 at pin 9. The first NEXT pulse going high is the cause of pin 6 of H5, the 200 LINES pulse going high again, because NEXT pulse Fig.13: a zoom-in of Fig.12 so you can see the timing clearly. the logic conditions that caused pin 6 of H5 to be low are eliminated by the reset trigger. It shows a loop propagation delay of something in the order of 50ns after NEXT goes high, or half a NEXT pulse width before the CAG is reset. The end of the NEXT pulse does not extend past what would be the time position for the following address. The address value of 1 would persist for around 160ns before being clocked to 2, 3, 4 etc with the usual 1μs timing stable on each address. The 20 LINES detector The second, third and fourth NEXT pulses are produced by the 20 LINES detector. This is an interesting detector because a unique address did not exist inside the main F2 and F4 counters or the G3 latch system to fully encode it. This is because a 20-line boundary falls inside a zone of repeating CAG addresses. As previously explained, the CAG, regardless of the VIDEO ON or OFF timing, is relentlessly repeating groups of eight-line counts. Therefore, pulse RA9 had to be acquired from the 3-bit counter (H11), which controls the low ROM addresses and generates the RELOAD signal. The 3-bit counter circuit and reload gate are shown in Fig.14. The RO1 and RO2 inputs of 74LS93 counter H11 are active-high to clear the flip-flops within. It was previously noted that the NEXT pulses reset (clear) this 3-bit counter. Scope grab Fig.15 is triggered from VIDEO ON and shows RA9, the MSB of the 3-bit counter (H11, pin 11), and CAG address bit 7, which feeds the 20 LINES gate at pin 1 of G2. For the 20 LINES detector to be 280ns wide pulses not visible on current scope setting RA9 Bit 7 CAG VIDEO ON pulse used to trigger scope Fig.14: how the RELOAD and 20 LINES signals are generated. siliconchip.com.au Australia's electronics magazine Fig.15: the relationship between the MSB of 3-bit counter H11 (RA9) and CAG address bit 7. September 2026  67 Delay timebase recording Hitachi V509 RA9 3.84ms VIDEO ON Pulse Bit 7 CAG 20 LINES pulses G2 pin 6 2V/Div vertical sens. Fig.16: a zoom-in of Fig.15, annotated to make it clearer. operational, it must be outside the VIDEO ON time where characters are presented. Therefore, the VIDEO ON pulse is inverted by gate I1 (pins 5 & 6) to become VIDEO OFF and applied to pin 2 of gate G2. The RA9 pulse stream appears as a chain of two pulses followed by an apparent missing pulse (it is there but not easily seen). This sequence repeats three times during the VIDEO OFF time. Bit 7 of the CAG appears as a chain of seven 17μs-wide high-going pulses Fig.17: like the NEXT pulses, the pulses that trigger them are brief and hard to see on an analog ‘scope. as the count increases, with a broad 8th pulse approximately 256μs wide at the end of the seven pulses. This pulse array again repeats three times in the VIDEO OFF time window. A very narrow 280μs pulse is present in the RA9 pulse stream, noted on the recording with white arrows. This is the precursor pulse to the three remaining NEXT pulses, which reset the 3-bit counter that created the RA9 pulse. This results in rapid termination of the RA9 pulse after it goes high. Fig.16 shows an expanded view of Narrow pulse not seen in this trace Fig.18: this shows how the bit 7 pulses that occur while RA9 is low are ignored; it’s only the four that occur while RA9 is high that trigger the four NEXT pulses. 68 Silicon Chip NEXT pulse precursors 280ns each Australia's electronics magazine the relationship between RA9 and bit 7 of the CAG. Four of the initial pulses of the bit 7 pulse stream occur while RA9 is low. Thus, these four pulses do not make it out of pin 6 G2, into the 20 LINES pulse stream. RA9 falls low again just after the start of the 256μs block of the bit 7 pulse. This shortens that pulse, so that what remains in the 20 LINES pulse stream are three groups of four pulses, each close to 17μs wide, with a gap leading to the difficult-to-see 280ns precursor of a NEXT pulse (Fig.17). The 280ns precursor to a NEXT pulse has its leading edge created by RA9 and its trailing edge terminated by the NEXT pulse it creates, resetting H11 and the CAG; hence, both RA9 and address bit 7 go low. Fig.18 shows how the remaining four pulses leading to each 280μs pulse are eliminated by the HORZ DISP OFF pulse and gate G1. The recording is faint, but when the numbered pulses are high, the HORZ DISP OFF pulses are low, thereby eliminating these 4 pulses at the pin 3 output of G1 feeding flip-flop G8, which issues NEXT pulses. This whole process is summarised in Fig.19. The expected counting probe values are shown. With the probe counting in active video time, by connecting the probe’s gate input to VIDEO ON, and the probe tip is connected to HORZ DISP ON (or HORZ DISP OFF), the count will be hexadecimal C8 (200 decimal) as you would expect given that the active area of the display is 200 lines. If the probe’s GATE is connected to siliconchip.com.au VIDEO ON, it is counting in the VIDEO OFF time, so it will then count to hexadecimal 3C (60 decimal), as there are 60 lines outside the active area. The first NEXT pulse is not counted by the probe in this VIDEO OFF time window because, as previously noted, its rising edge resides inside the VIDEO ON time window. Summary The PET’s character address generator is a master class in glue logic design using 74-series TTL ICs. Due to its complexity and paucity of information provided by Commodore on how it worked, technicians have struggled to repair it. The situation is not helped by the very narrow pulses in parts of the circuit, which are difficult to see with an analog oscilloscope. If you know what pulses are supposed to be there and why, then it makes it much easier to find them. Hopefully, this description of the CAG above will help in fault finding and repairs. Generally, vintage 74-series TTL chips are fairly reliable, but they can occasionally fail. Even one logic gate failing in a circuit like this can result in very complex malfunctions. Also, TTL chips can have various failure modes. It is usually fairly obvious when their output stage fails and the output voltage goes outside the range of standard TTL logic highs and lows. One interesting failure is that sometimes a gate input can go open circuit inside the package. When that happens, the chip’s die assumes the pin is logic high, so a multi-input gate chip can still produce normal-­looking output pulses, but they are the wrong pulses. The only guaranteed method of ensuring a logic chip is working properly is to verify that it is obeying its logic table. Other ICs in the PET are not as reliable as the 74-series TTL parts. In many vintage PET repairs, the 2114 SRAM ICs have been found to be defective. There is also a fairly high failure rate of the 4116 DRAM ICs, and the PIA and VIA chips occasionally fail. The MC3446 GPIB bus driver ICs can also fail occasionally. Mostly, the 6502 CPU remains reliable. I aim to present further articles later to help with PET repairs. One will be on testing the dynamic RAM (DRAM) siliconchip.com.au Fig.19: the CAG address counter continues to run during the vertical retrace and raster blanking periods, but the values are not meaningful. Still, they are shown here, along with the various pulses, to aid in debugging in case something has gone wrong. A missing signal may be the key to diagnosing the fault. memory chips. It uses a diagnostic system based on an added hardware module and some custom firmware held in a ROM that is plugged into the board. Another will be on the Dynamic PET’s 9-inch CRT VDU. This article will describe how to restore Australia's electronics magazine and improve the VDU, including a detailed analysis of flyback transformers and how to test and diagnose them. It will also cover possible non-standard part replacements because the original parts are very SC difficult to find now. September 2026  69