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Part 2 by Dr David Maddison, VK3DSM Analog Computers A recreation of Charles Babbage’s Difference Engine at the Computer History Museum in Mountain View, California. Source: Jitze Couperus – www.flickr.com/photos/jitze1942/4304353299/in/album-72157623284316506 Analog computers are making a comeback because they are well-suited to neural network processing. We’ll cover some of the theory behind that, then look at some of the new analog computers that are being developed. T he extremely high speed of modern digital computers and the relative ease of programming compared to analog computers accelerated the decline of the latter in the 1970s. However, analog computing is experiencing a major resurgence, albeit in a somewhat different form from traditional analog computers. While modern analog computers still rely on analog signals (voltages, currents, resistances or even light) to perform calculations, their design bears little resemblance to the analog computers of the mid-20th century. 12 Silicon Chip Instead of racks of discrete op amps wired via patch panels and potentiometers, today’s implementations are built on silicon chips using memristors, floating-gate transistors, switched-capacitor arrays or photonic waveguides. They are often digitally programmable. They are also far smaller than the analog computers of yore, and more precise, being targeted at specific tasks like AI matrix-vector multiplications or AI inferencing (using a pre-trained AI model to produce an output). That makes it possible to use them in Australia's electronics magazine smartphones or embedded devices, alongside existing digital processors. The main benefit of modern AI analog computing is high energy efficiency and high processing speed for specific AI tasks, like inferencing and matrix-vector multiplication. These functions are implemented in AI accelerator chips. One common feature of AI accelerators (hardware optimised for AI tasks) is their massively parallel nature. By using many parallel units operating at a high speed, they can perform thousands of calculations simultaneously siliconchip.com.au and complete billions per second. They are designed for linear alegbra and the tensor mathematics used in AI applications. Digital AI accelerator chips include GPUs (graphics processing units, widely used for training), TPUs (Google’s tensor processing units for neural networks), NPUs (neural processing units for on-device AI), ASICs (application-specific integrated circuits for specific AI functions) or FPGAs (field programmable gate arrays, reconfigurable chips for various tasks). On the other hand, modern analog accelerator AI chips generally fall into the following categories: • Resistive/electrical AIMC (analog in-memory computing). • Neuromorphic (analog, digital, or mixed; when analog, they often overlap with AIMC). • Photonic analog AIMC is ideal for matrix-vector multiplications directly in memory arrays using resistive devices like PCM (phase change memory), RRAM (resistive random-access memory) or flash memory. Examples include IBM’s PCM-based chips, Mythic’s M1076 (flash analog), EnCharge AI’s capacitors and Peking University’s RRAM prototype. These focus on efficient deep learning inference. We will describe in-memory computing later. Neuromorphic chips emphasise brain-inspired designs, often with spiking neural networks (SNNs), event-driven/asynchronous processing and sparsity. These can be analog, digital or hybrid. Sparse models and SNNs will be described shortly. Photonic chips use light-based processing, like Lightmatter and Microsoft’s AI chip. They have the potential to use even less power than the other types of analog AI chips. Features of modern analog AI Modern analog AI computing has the following characteristics. that have been trained using digital AI. Currently analog AI computers are mostly used only for energy-­efficient inferencing, not training. However, research is underway to develop analog AI training models, and it has been experimentally demonstrated. Analog computing suits specific AI workloads For specific AI workloads, especially inferencing, in-memory matrix operations and ‘sparse’ models such as ‘mixture of experts’ (MoE) or spiking networks, analog computing offers dramatic efficiency gains. In sparse models, a significant portion (often the majority) of connections (weights) or activations are intentionally set to zero or left inactive to boost efficiency in terms of memory, computation and energy without drastically harming performance. Dense models, by contrast, maintain near-­ complete connectivity, which can capture more complex patterns but at a higher resource cost. Sparsity is especially beneficial in contexts like analog AI, where it aligns with the nature of the analog hardware. Analog AI has been suggested as being highly suitable for MoE models. These are neural network architectures in which a large model is split into many smaller sub-networks. An ‘expert’ is a small specialised part of the overall neural network model. A lightweight routing network dynamically decides, for each input, which expert (or experts) to activate for a particular problem. So, instead of running the entire massive model for every input, only a small subset of experts is used. This makes the system much more efficient than traditional dense models (where everything runs every time). In analog implementations of MoEs, the unused experts can be completely powered down, leading to even greater Analog AI is not a complete replacement for digital AI Analog (or analog-inspired neuromorphic/mixed-signal) computing cannot yet fully replace a digital GPU cluster like xAI’s Colossus because it is not a drop-in replacement for general large-scale AI training. Due to present limitations of analog AI, for inferencing, analog AI uses models Fig.37: the model of experts (MoE) concept. siliconchip.com.au Australia's electronics magazine power savings. These analog MoE systems can be fully analog or hybrid (for example, with digital routing and analog experts). In reference to Fig.37, a gating network uses weights to adjust each expert’s contribution to the final answer. The gating network learns from experience and decides which is the most appropriate expert to send the data to. By sending the data to the ‘best’ expert, the processing is more effective. This is more effective than just using a single expert. Analog MoE models have been implemented by IBM using phasechange memory (PCM) crossbars for the expert model weighting; a small analog router selects 2-4 experts per input for vision tasks. Mythic’s analog matrix processors use flash memory to carry the expert weighting. Lightmatter is using optical routing to switch light paths to different refractive expert layers. A spiking neural network (SNN), or spiking network, is a type of neural network that mimics how biological brains work more closely than standard artificial neural networks. With analog AI, the reported possible savings in power consumption are 10× to 100× (or even as much as 1000× for analog-optimised tasks) for inference applications compared to digital AI. Edge computing Because analog AI chips consume so little power, they allow advanced AI models like large language models (LLMs) to mimic the human brain’s efficiency and to run on small ‘edge’ devices like smartphones, autonomous robots, UAVs, wearables etc without the need for a ‘cloud’ connection. Energy efficiency Currently, xAI’s Colossus AI training supercluster in Memphis, Tennessee is June 2026  13 recognised as the world’s most powerful AI compute facility with around 200,000 NVIDIA H100/H200 GPU equivalents. It consumes 280-300MW peak power. Meta’s clusters and Microsoft/OpenAI facilities are in the 100-200MW range. US data centre power consumption today, a large portion of which is due to AI, is around 40GW and is projected to reach 78-123GW by 2035. Even with the low cost of electricity in the USA compared to Australia, with such high power consumption, the running costs are significant. In a hypothetical 300MW data centre with an inference-heavy workload, partial analog adoption could reduce power consumption by 50-90% (eg, 30-150MW). For full training, that is not as feasible today, but perhaps a 20-50% reduction is possible with hybrid computers. Matrix operations A fundamental operation in neural networks is matrix-vector multiplication (often matrix multiplication in layered neural networks). Analog circuits can perform this extremely efficiently and in parallel by exploiting natural physical laws such as Ohm’s law (V = IR) and Kirchhoff’s current law (the total current entering a junction must equal the total current leaving), which are intrinsic to electronic circuits. Inputs are applied as voltages across a resistive ‘crossbar array’ (typically memristors, resistive RAM [RRAM] or resistor grids), and the resulting currents at each column naturally sum to produce the dot-product outputs, which represent the matrix multiplication result instantaneously (limited only by circuit settling time, typically nanoseconds to microseconds). A dot product is a simple mathematical operation involving multiplying two vectors to form a single vector. A basic 3×3 crossbar array is shown in Fig.38. The inputs are voltages V1, V2 & V3 on the rows representing the input vector (eg, pixel brightness values from an image being analysed). The matrix weights (obtained via prior training representing the importance of an association) are the conductances (Iij = 1 / Rij) at each crosspoint of the matrix elements (higher conductance = more weight). The outputs are currents I1, I2, I 3 down the columns, which are 14 Silicon Chip Fig.38: a 3×3 resistive crossbar array, the core of many modern analog AI accelerators (eg, the memristor or resistor grids in Mythic or IBM chips, respectively). It performs vectormatrix multiplication instantly via physics. automatically the matrix-vector product with no mathematical operations used; just Ohm’s and Kirchhoff’s laws doing the work in parallel. By Ohm’s law, the current through each crosspoint Iij = Vi × Iij. By Kirchhoff’s current law, the output current Ik = ∑(Vi × Iij) for j = k. Thus, Ik is the dot product of the input vector V with column k of conductance matrix G. Matrix multiplication is the mathematical powerhouse behind nearly every modern artificial intelligence system, especially deep neural networks (the foundation of models like GPT, BERT, Stable Diffusion and computer vision). Matrix operations are how neural networks ‘think’. A neural network layer takes an input vector, such as numbers representing pixel values in an image or words and produces an output vector. This transformation is almost always a matrix-vector multiplication: output = weights_matrix × input_vector + bias. The weights matrix contains millions (or billions) of learned parameters that encode what the network has ‘learned’ during training. Each layer performs this operation, stacking many layers to create complex representations (eg, recognising a cat from pixels). The bias is an extra adjustable parameter added to each neuron (or node) in a layer, alongside the weighted sum of inputs. It provides a ‘starting point’ for any opinion the AI might formulate, and this is the basis Australia's electronics magazine for any political or other bias that AI engines are deemed to have. In simplified terms, a neural network layer can be thought of as a team of experts (neurons). Each expert gives an opinion weighted by their expertise (matrix weighting values) on every piece of input data. Matrix operations are the bottleneck for speed and energy use in AI training and inference. Around 90-99% of computation time and energy in deep learning is spent on matrix multiplications. That’s why in digital AI, GPUs (with thousands of cores for parallel maths) and specialised chips (eg, TPUs, NVIDIA H100s) are designed to accelerate matrix operations. Analog AI computing is ideal for matrix multiplication because it utilises physical laws, as explained above, allowing it to perform billions of multiplies/adds in parallel instantly and with little power consumption. After the matrix operation, the resulting current (or voltage after conversion) can then be fed to an analog-­ to-digital converter (ADC) for further processing, in the case of a hybrid computer, or it can pass directly to the next layer of the neural network. Such analog circuits are ideal for real-time audio or video processing since they lack the delays inherent in digital conversion and processing. In-memory computing means the computation occurs directly within memory cells, using phase-change memory or RRAM, eliminating the need to shuffle data out of memory for processing. The challenges of analog AI processing This is not without its challenges, which include: Precision and noise Analog signals are susceptible to noise and non-repeatability due to the variable values within the tolerance of electronic components. Thus, a calculation won’t necessarily give the same result every time, although it will be close enough for some purposes. Digital computers in contrast are precise and repeatable. Programmability Software development tools for CUDA (NVIDIA’s programming model) have been in development for decades. siliconchip.com.au Whole new software suites have to be developed for analog computing; companies like IBM have open-sourced toolkits such as aihwkit (https://github. com/IBM/aihwkit) to ease the transition. close to a large source of power, and the electrical grid doesn’t have to be extended to accommodate it. Circuits for modern analog AI • Optical components in photonic chips; microLED arrays for light sources to represent the input vector or neural network activations; spatial light modulators to store neural network weights and perform multiplication with incoming light; photo-­ detector arrays to convert light signals back into electrical signals for further processing; and photonic waveguides as conduits for light that steer and manipulate it to perform mathematical operations. • Phase change memory – described in the IBM entry later. • Resistive RAM (RRAM) – the practical implementation of a technology that uses memristors to store information. • Switched-capacitor arrays – described in the EnCharge entry later. We will now look at some modern experimental or commercial chips analog computing chips and systems. Key electronic components in modern analog AI chips are: Hybrid necessity • Analog-to-digital converters AI systems involve two main (ADCs) and digital-to-analog convertphases: training and inferencing. ers (DACs) to interface between the Training is the computationally digital and analog worlds. expensive phase where a model (gen• Calibration circuits, to mitigate erative or discriminative) learns pat- the natural variability in analog comterns from massive data, often requir- ponents, noise and thermal drift. ing hyperscale data centres. Infer• Field programmable analog arrays encing is the computationally lighter (FPAAs) – more on these later. phase, where the trained model is used • Ferroelectric devices (emerging) – on new inputs to produce outputs, these use ferroelectric materials where eg, answering questions, generating the polarisation state can be switched images, or classifying objects. to modulate conductance or capacThe two major model categories are itance, enabling non-volatile analog generative models, which create new weight storage. content, and discriminative models, • Floating-gate transistors – stanwhich make decisions or classifica- dard transistors with a ‘floating’ gate tions. that traps a variable amount of charge, While analog computing excels at storing information. This charge modACCEL siliconchip.au/link/aca7 edge AI inferencing (eg, on smart- ulates the transistor’s conductance, The All-analog Chip Combinphones or IoT devices) and lower-­ allowing precise analog storage of neu- ing Electronic and Light computpower tasks, it is not yet suitable for ral network weights. They are used in ing (ACCEL) is an experimental hyperscale training. flash memory, such as by Mythic. photonic-­ electronic chip from ChiA full switch to 100% analog is • Gain cells (emerging) – a type of na’s Tsinghua University, announced speculative; a hybrid digital/analog memory with two or three transistors in 2023. It is claimed to classify highapproach is a possible short-term path. and possibly a capacitor that can store resolution images over 3000 times In a hybrid system, a digital processor a variable amount of charge represent- faster and with up to four million times handles logic and control, while ana- ing the stored information. less energy than state-of-the-art GPUs log accelerators do the maths. • Memristors – resistors with a like NVIDIA’s A100. memory. Their resistance depends on An input image is processed in the The AI scaling crisis the amount of charge that has flowed optical domain for feature extraction; This is the realisation that simply through them in the past, so the resis- the resulting light field strikes a phoadding more data, computing power tance can be adjusted to the desired todiode array, converting it to phoand electrical energy to AI models value. tocurrents that feed directly into an will hit physical, economic and practical limits. AI-driven data centres use Ternary computing so much electricity that the availabilTraditional digital computers use ‘binary’, with memory cells and logic lines ity of electricity in specific regions (‘bits’) being in one of two states (0 or 1). In contrast, analog computers operis the limiting factor, not chips. As ate with a continuum of values. a result, companies like Amazon are An intermediate concept is ternary logic, which uses three possible states purchasing nuclear-powered data for a bit or ‘trit’, typically -1, 0, +1. They could be encoded electrically as (for centres. example) 0V, half supply and full supply, or even active low, high-impedance There is also the problem of ‘plaand active high. teauing intelligence’. Simply increasOne of the earliest examples was Thomas Fowler’s mechanical ternary caling the AI model size does not result culator in 1840. The first electronic ternary computer, Setun, was built in the in much increase in reasoning ability. Soviet Union in 1958 by Nikolay Brusentsov. Fifty units were produced until Also, the AI industry is running out of 1965. It was a remarkably balanced and efficient design that unfortunately high-quality data to train models on. lost out to the mass production of binary systems. Analog AI computing offers a possible Interest in ternary computing largely faded in the West due to the domisolution to these problems. nance of binary hardware, but like analog computing, it is attracting renewed We’ve already discussed how research interest today for much the same reasons as analog, primarily for analog AI techniques overcome the its theoretical energy efficiency (fewer state transitions per information unit) power consumption problem. Another and potential advantages in certain algorithms. advantage of this is that decentralisaHowever, practical AI applications remain experimental and far less develtion becomes possible; it will no lonoped than analog or neuromorphic approaches. ger necessary for data centres to be siliconchip.com.au Australia's electronics magazine June 2026  15 Fig.39: an example of emulating convolutional neural network (CNN) layers in the optical domain using diffractive layers. Original source: www.mdpi. com/1424-8220/23/12/5749 electronic analog computing unit for final classification, all without the need for an ADC. The front-end uses diffractive optical analog computing. An input optical image shines through a series of engineered diffractive layers. Each layer causes light waves to interfere and diffract in a way that naturally performs linear transformations (dot products & convolutions). The final light pattern at the output plane encodes the result, with no active electronics involved. It is completely passive (like a lens), ultra-fast (limited only by the speed of light), and consumes almost zero energy in the optical part. The resulting light field hits a photodiode array, converting it to analog electrical currents that feed into the electronic analog computing unit for final classification, keeping the entire pipeline analog end-to-end. Its main advantage is that the diffractive part handles the bulk of the matrix multiplications passively at light speed. The ACCEL chip mimics convolutional neural network (CNN) operations of a digital or modern analog computer in its optical front-end. This diffractive optical neural network (DONN) performs feature extraction equivalent to convolutional layers in a CNN, while the electronic analog backend handles non-linear classification – see Fig.39. ACCEL is currently specialised for vision tasks (static images), but could be scaled to other linear operations. Anabrid https://anabrid.com Anabrid has several analog computing projects. In 2024, it produced their 16 Silicon Chip ABRGPX1 Anabrid General Purpose Experimental Test Chip analog multiplier (see Fig.40). It is a test chip for the upcoming commercial offerings, a hybrid digital/analog chip that allows analog capabilities to be integrated with digital systems. Anabrid are also the makers of The Analog Thing, the open source analog computer mentioned last month. lucidac is a reconfigurable analog/ digital hybrid computer intended for early adopters and educational purposes. It has suggested uses in robotics, speech recognition and automotive electronics – see Figs.41 & 42. redac (Fig.43) is said to be the world’s first reconfigurable analog supercomputer. It has six modular clusters with 432 multipliers, 864 integrators, 1728 summation lanes, 124,416 switching elements and 3456 scaling elements. It has digital interfaces for programming and control, using the Python and Jupyter languages. Its purpose is to solve complex ordinary and partial differential equations, solve optimisation problems and act as a testbed for unconventional computing. It is claimed to be significantly faster than conventional computers for certain problems and can provide real-time solutions that are difficult to achieve with conventional computers. Uses proposed for anabrid products are real-time flight wing adjustments, motion control in automation and energy-efficient supercomputers. Aspinity www.aspinity.com Aspinity produces ultra-low-power analog machine learning (analogML) chips for always-on edge AI applications. It claims to have produced the Australia's electronics magazine Fig.40: the Anabrid ABRGPX1 chip ‘floorplan’. Source: https://anabrid. dev/about/news/2024-09-19-tc01press-release world’s first fully analog machine learning chip, the AML100, from 2022. Its technology processes raw analog sensor data in the analog domain, detecting relevant events with nearly no power consumption, waking digital processors only when needed, thus achieving a 10-20× battery life extension. The chip’s current draw is only about 20-100µA. Applications include security monitoring of a parked vehicle using up to four sensors; monitoring of smart homes for events such as glass breaking, smoke, carbon monoxide, leaks, intruders, a baby crying etc; or waking IoT devices for voice/keyword, vibration, or other movements; all with low power consumption. Fig.44 compares conventional Fig.43: the redac analog supercomputer, which is used to solve differential equations. siliconchip.com.au Fig.41: the lucidac software editor. Source: https://anabrid.com/lucidac Fig.42: the lucidac analog/digital hybrid computer. Source: https:// anabrid.com/lucidac monitoring vs monitoring with the AML100 analog processor. analog AI inference is used to identify only relevant data to pass on to the digital processor. The avoidance of unnecessary analog-to-digital conversion saves a lot of power. Aspirare Semi www.aspirare.io This Canadian company has developed a range of hybrid neuromorphic AI accelerators using analog compute cores and digital components. Their Gen 1, Gen2 and Edge models and are commercially available. Blumind https://blumind.ai Another Canadian company that has developed all-analog neuromorphic processors such as the BM110 for low-power edge tasks like always-on voice (eg, keyword detection) and sensor processing. The BM110 is in volume production, while the BM210, intended for video image classification, is scheduled for volume production. BrainScaleS-2 siliconchip.au/link/aca8 BrainScaleS-2 from Heidelberg University is part of the EU Human Brain Project. It is a mixed-signal/ analog-emulated accelerated neuromorphic system using analog circuits to emulate neuron/synapse dynamics up to 10,000× faster than biology, with digital connectivity. It is ideal for large-scale spiking neural network simulations. DYNAP-SE2 siliconchip.au/link/aca9 DYNAP-SE2, developed by the Fig.44: a comparison of the AML100 senses (bottom) with conventional methods (top). With the AML100, unnecessary analog-to-digital conversion is avoided. Source: www.aspinity.com/aml100 siliconchip.com.au Australia's electronics magazine Institute of Neuroinformatics (INI) at the University of Zurich and ETH Zurich, is an experimental mixed-­ signal neuromorphic chip designed for real-time, low-power spiking neural network processing. It features 1024 analog neurons, each with up to 64 programmable synapses, combined with digital event routing for flexible connectivity. The chip is reconfigurable, supports adaptive and learning behaviours (eg, spike-timing-dependent plasticity) and operates at extremely low power, typically below 1mW for many workloads. SynSense markets and sells related development kits or boards featuring the DYNAP-SE2. EnCharge www.enchargeai.com EnCharge announced the EN100 commercial accelerator chip in 2025. It uses analog in-memory computing for high-performance AI applications. In the EN100, neural network weights are stored in digital SRAM, while computation is performed by charging capacitors to various levels and then connecting them together to redistribute the charge. This mechanism avoids the noise problems of other analog AI designs. The M.2 laptop chips can deliver >200 TOPS (trillions of operations per second) using just 8.25W of power. There is a PCIe card version of the processor for AI workstations that delivers >7.4 PetaOPS of capacity (1000 trillion operations per second). Compared to other forms of in-­ memory computing (see Fig.45 overleaf), EnCharge claims a superior signal-­ to-noise ratio, compatibility with standard CMOS 4nm technology June 2026  17 nodes, broad support for existing AI models and scalable technology. IBM siliconchip.au/link/acaa IBM is using phase-change memory (PCM) devices for analog in-­ memory computing (AIMC). These are nanoscale resistive elements that store neural network weights as varying resistance states and perform matrix-vector operations in-place. Prototypes include multi-core chips with tens of millions of PCM cells, achieving high accuracy on tasks like speech recognition and image classification while using far less power than digital equivalents. In PCM, an electrical pulse is applied to a material, which causes heating and changes its conductance by switching the material between its amorphous (glass-like) and crystalline phases. A small pulse results in there being more crystalline material and lower resistance. A large pulse results in The resistance value corresponds to a neural network weight. The PCMs are arranged in a crossbar configuration – see Fig.46. This enables analog matrix-vector multiplication in a single-­step as explained before. Fig.46: IBM’s PCM crossbar configuration that allows matrixvector multiplication in one step. Source: https://research.ibm.com/ blog/the-hardware-behind-analog-ai more amporphous material and more resistance. Between pure crystalline and pure amorphous phases, there is a mixture of both, representing a continuum of resistance values between 0 and 1. Imec www.imec-int.com/en They produced the experimental AnIA (Analog Inference Accelerator) chip in 2020, which uses analog in-memory compute (AiMC) architecture. The AnIA has reached a high efficiency of 2900 TOPS per watt for vector matrix multiplications. The technology is intended for pattern recognition with tiny sensors and other edge devices. Lightmatter https://lightmatter.co Lightmatter makes the Envise photonic analog AI accelerator chip, which is in a late prototype stage. It is a photonic chip like ACCEL, but while ACCEL relies on diffractive optics, Envise relies on ‘Mach-Zehnder inter- Fig.45: EnCharge’s comparison of traditional AI accelerators, other in-memory computing (IMC) and their own IMC model. NVM is non-volatile memory, MAC is memory and compute and SNR is signal-to-noise ratio. Source: www. enchargeai.com/technology 18 Silicon Chip Australia's electronics magazine siliconchip.com.au ferometers’ to perform light manipulation. Also, ACCEL is intended for research and is not a commercial product. Envise has a hybrid design, with photonic circuits handling the heavy analog computation and digital silicon parts managing control, memory (eg, SRAM) and digital tasks. Lightmatter has announced a multi-chip package with six dies, 50 billion transistors, and one million photonic components using 3D stacking. This chip achieves 65.5 trillion operations per second using just 78W electrical and 1.6W of optical power. Microsoft siliconchip.au/link/acab Microsoft produced an experimental Analog Optical Computer (AOC) in 2025. Like the products from ACCEL and Lightmatter, it is photonic, although it is not a chip but built with discrete components. It aims for a 100× improvement in energy efficiency for large language models (LLMs). The AOC combines 3D optics (lenses, micro-LED arrays) with analog electronics (eg, CMOS sensors from smartphone cameras) to perform computations directly with continuous light intensities, bypassing binary digital conversions and the von Neumann bottleneck. It excels at massively parallel vector-­ matrix multiplications (core to neural networks) and iterative operations, using physical properties of light for addition/multiplication via interference and detection. Nonlinearities are handled electronically, making it a hybrid analog-optical design that runs at room temperature with consumer-­ grade parts. Fig.47 shows a simplified view of the vector-matrix multiplication unit in the foreground. This consists of a linear array of micro-LEDs, a 2D modulator array (using display projectors), and a linear array of silicon sensors. Fig.48 shows the actual computer. For more information, see the video at https://youtu.be/cswAkdU_6yk Fig.47: a simplified diagram of Microsoft’s AOC setup. Source: www.microsoft. com/en-us/research/project/aoc Fig.48: Microsoft’s AOC computer. Source: https://news.microsoft.com/source/ features/innovation/microsoft-analog-optical-computer-cracks-two-practicalproblems-shows-ai-promise/ An analog computer kit from 1961 An article from Popular Electronics describes two simple analog computer kits, one from Edmund Scientific (Figs.49 & 50) and one from General Electric, both available in 1961. You can read it at siliconchip.au/link/acah The Edmund Scientific computer, based on a voltage divider circuit using three potentiometers, is described in more detail at siliconchip.au/link/acai That page describes how to build your own, with modern components; there is even a file to download for the front panel and potentiometer discs. Mythic https://mythic.ai Mythic produces the M1076 Analog Matrix Processor (Fig.51), a single-­ package analog AI accelerator. It is designed primarily for edge AI inference (running trained neural networks efficiently on devices like cameras, drones, robots or servers with low power consumption). Figs.49 & 50: an original Edmund Scientific analog computer kit and matching circuit from the 1960s. Source: www.servomagazine. com/magazine/article/ alternative-computingmodels-part-3-electronicanalog-computing siliconchip.com.au Australia's electronics magazine June 2026  19 Fig.51: the Mythic M1076 on an M.2 card, the same format used for many modern plug-in solid-state storage drives. Source: https://mythic.ai/products/ mm1076-m-2-m-key-card Fig.52: the operation of a Mythic AI processor. X and Y are row and column addresses. Original source: https://mythic.ai/technology/analog-computing It delivers up to 25 TOPS while typically consuming only 3-4W (a comparable GPU might use hundreds of watts). The chip can store about 80 million weight parameters onboard and performs computations without external memory. The M1076 contains 76 tiles (small chips inside the main package) each comprising one Analog Compute Engine (ACE). Each ACE has an analog flash memory array that stores neural network weights as varying resistances, and it performs matrix multiplications in-memory, using physical currents with low power consumption and at high speed. ADCs read out the results precisely. Each ACE has a small digital subsystem for support: a 32-bit RISC-V processor (for control/tasks), a SIMD (single-instruction, multiple-data) vector engine (for non-matrix ops), 64kiB of SRAM (local scratchpad) and a network-on-chip (NoC) router (to connect tiles efficiently). The flash memory cells are used as tuneable resistors to store the weights of a neural network. This can be achieved by controlling the charge stored in each cell. Input data is represented by voltages across the memory cells (in rows). These voltages across a known resistance produce a current determined by Ohm’s law, the product of the input voltage (the data) and the neural network weight. By summing all currents in a column, a vector-matrix multiplication can be performed. The result of the matrix multiplication is then read with the ADC (see Fig.52). Neurogrid siliconchip.au/link/acac Neurogrid from Stanford University is a mixed-signal experimental 20 Silicon Chip multichip neuromorphic system capable of simulating one million neurons and billions of synaptic connections in real time with very low power (about 3-5W). It is primarily used for large-scale brain simulations and employs analog computation to emulate synaptic connections and neuron dynamics. It is a landmark example of early mixed-signal neuromorphic hardware from around 2014. NeuRRAM siliconchip.au/link/acad NeuRRAM from UC San Diego/ MIT is an experimental neuromorphic mixed signal analog computein-­memory chip using resistive RAM (RRAM) for energy-efficient AI inference on edge devices. It runs a wide variety of AI tasks (eg, image classification, speech recognition and reconstruction) directly in memory with far less power than traditional methods. Okika https://okikadevices.com Okika acquired Anadigm and now produce field-programmable analog array (FPAA) chips (see Fig.53). These are not specifically designed for analog computing but can be used for such. FPAA chips contain configurable analog blocks like op amps, differential amps and programmable capacitor arrays that can be programmed as capacitors or resistors. Fig.53: an FPAA from Okika Devices mounted on a PCB. Source: https:// okikadevices.com Australia's electronics magazine A capacitor can emulate a resistor by switching it at high speed with two transistors or some other technique. This technique is called switched-­ capacitor resistor emulation. These chips can be used for sensor interfacing, audio processing, industrial control and low-power analog computing. They are the analog equivalent of a field programmable gate array (FPGA). There are a large number of analog components available for programming from the FlexAnalog FPAA Design Library – see Fig.54. Peking Uni siliconchip.au/link/acae Peking University announced a prototype analog AI chip using resistive random-access memory (RRAM). It achieved high accuracy with 24-bit precision (comparable to 32-bit floating-­ point digital systems) and claims 1000× faster speed and 100× less energy consumption than digital AI computing. Sagence AI www.sagence-ai.com This Silicon Valley company has developed analog in-memory computing chips, particularly for large generative AI models like Llama2-70B. The chips are currently in the customer evaluation phase. SynSense www.synsense.ai A leading manufacturer of ultralow-power mixed-signal neuromorphic chips and sensors, targeting edge applications such as audio processing and keyword detection, gesture and scene recognition, wearables, bio-signal analysis (eg, ECG, EMG, breath, and gait), behavioural monitoring, smart toys, home automation, security systems, industrial siliconchip.com.au Fig.54: the many different design elements that can be programmed into Okika FPAA, from the FlexAnalog FPAA Design Library. These include filters, op amps, differential amps, sample-and-hold circuits, differentiators, integrators and more. Source: https://okikadevices.com/collections/an231e04-reconfigurable-flexanalog-fpaa-chip-with-4-cabs testing, robotics, drones and more. AI research in Australia UWS Deep South (siliconchip.au/ link/acaf) is a neuromorphic computer to simulate the human brain, but is entirely digital and uses FPGAs. Conclusion We have traced the development of analog computing from its mechanical origins through the electronic era, siliconchip.com.au followed by a long period of dormancy as digital computing came to dominate. Today, we are witnessing a modern revival driven by the need to overcome digital computing’s limitations, particularly its high power consumption for AI workloads. The dramatically lower power requirements of analog and analog-­ inspired AI systems open the door to intelligent local ‘edge’ devices, such as smartphones and sensors. If these Australia's electronics magazine technologies fulfil their potential, they could usher in a new golden age of efficient, brain-like computing. For anyone interested in learning more about analog computers, we recommend checking out the two links below: • An analog computing book collection: siliconchip.au/link/acaj • Introduction to Analog Computer Programming by Dale I. Rummer: SC siliconchip.au/link/acak June 2026  21