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Circuit Surgery Regular clinic by Ian Bell Timing and metastability in synchronous circuits – Part 1 L ast month, we looked at a digital (frequency) divide-by-two circuit from Ken Wood. Ken found that his circuit operated correctly when constructed, but a simulation in MicroCap 12 oscillated. Ken was inspired to try the simulation after reading in Circuit Surgery (December 2020) that this one-time $4500 professional software had been made freely available in July 2019. Ken’s problems raised some interesting issues. First, the fact that unexpected simulation results can occur in some situations where two or more components are identical, leading to very specific circuit behaviour – these results are not really wrong, but may be extremely unlikely to occur in a real circuit. It was equal gate delays in Ken’s simulation that created the conditions for oscillation. Second, looking in more depth at what might happen in Ken’s circuit we identified the possibility of metastability in an SR flip-flop. A flipflop should either store a 0 or a 1 (its stable states), quickly updating when required. Metastability can be thought of as flipflop ‘indecision’ – it gets stuck half-way between 0 and 1, and takes much longer than usual before finally settling in one of the stable states. We saw this in LTspice analogue simulations of a flip-flop storage loop last month. Ken’s circuit was unusual in that he was specifically trying to create the divide-by-two circuit directly from a minimum number of NAND gates, using asynchronous design techniques, rather than just using an existing flip-flop. Our focus last month was on the specifics of Ken’s circuit; however, metastability, and timing issues in general, are important when working with the much more I nputs (asynchronous) In Out S ub system 1 In Out S ub system 2 common situation of synchronous digital circuits built from clocked flip-flops and larger blocks such as registers and counters. This month, we will look at timing and metastability in the context of synchronous digital circuits. We will start by looking at the general structure of these circuits and the timing conditions needed to make sure they operate correctly. Synchronous circuits and clocks The majority of digital circuits have one or more clocks – a regular train of pulses that controls the overall timing of (that part of) the circuit. The clock is like a drill sergeant who is barking ‘left, right’ at a group of soldiers so they all march in a synchronised fashion. Circuits whose timing is coordinated by a clock are described as ‘synchronous’ – this applies to the majority of digital circuits. We often break larger circuits down into smaller blocks or subsystems, and in the simplest cases these will all have the same clock. Fig.1 shows a simple example – real circuits will usually have a more complex structure. Often, the clock is basically a square wave at a specific, often accurately controlled frequency. In simple systems, the clock frequency may be fairly arbitrary, but in other cases may be determined by very specific constraints; for example, for visual display signals or data communication protocols. A complex system may have a number of such subsystems requiring different timing, and therefore may have multiple clocks (see Fig.2). The circuitry associated with a given clock is said to be in a particular clock domain. Transferring data across clock domains must be done carefully to avoid potential timing problems and consequent errors. In Out Outputs I nputs (asynchronous) In Digital circuit operations that are not under the timing control of the clock are described as ‘asynchronous’. Circuits can be mainly synchronous but also feature some asynchronous operations or functions. Perhaps the most common example is an asynchronous reset, which puts the circuit into a well-defined state at power up, or after a crash when a user ‘hits the reset’. Asynchronous resets are common in flip-flops and other devices in the 4000 and 7400 logic families; however, resets can also be synchronous. It is common for external inputs to clocked digital systems to be asynchronous – the external system will not be related to the internal clock timing unless the system’s clock is from a source where it is already coordinated with the other inputs. The fact inputs are often asynchronous, and therefore may change at the ‘wrong’ time, means that there is always the potential for timing problems to occur – more on this later. The circuit in Fig.1 is synchronous. The operation of each stage is stepped forward by a specific transition of the clock (0 to 1, or 1 to 0) – known as the active clock edge – thus all operations are synchronised by the clock. The fact that an edge triggers the operation is often indicated by a small triangle next to the input on the circuit symbol for the block/ component, as in Fig.1 to Fig.3. If there is a small circle (‘inversion bubble’) between the triangle and input wire a negative edge trigger (1 to 0) is indicated, otherwise the edge trigger is positive (0 to 1). Block symbols for positive and negative edgetriggered circuits are also shown in Fig.3 – the blocks could represent individual flip-flops or larger more complex circuits. Out S ub system 1 In Out S ub system 2 In Out Outputs S ub system 3 S ub system 3 Clock 1 Clock Clock 2 Fig.1. Single-clock subsystem drawn as a block structure. 42 Fig.2. Synchronous system with more than one clock domain. Practical Electronics | March | 2021 In Out In S ub system 1 Out D S ub system 1 Clock Clock Cycle 1 Cycle 2 Cycle 3 . . . Cycle 1 Cycle 2 Cycle 3 . . . Q R 1 In Out CL D Q R 2 Clock Fig.5. Register-to-register transfer (R1, R2) via a block of combinational logic (CL) is the key structure in a synchronous circuit. Clock period, T P ositive edge (active clock edge) Clock period, T Fig.3. Some definitions relating to clocks. The repeating part of a clock waveform is referred to as the clock cycle. If circuit activity is edge triggered then the cycle is usually considered to start at the active clock edge. Clock waveforms with clock cycles identified, for both positive and negative edge systems, are shown in Fig.3. The time duration of one clock cycle is called the clock period, TC. The frequency of the clock is given by: fC = 1/TC. The stages (in Fig.1) operate simultaneously, so stage 1 is processing new data while stages 2 and 3 work on older information. This is a bit like an assembly line in a factory, where the finishing touches are applied to one copy of a product at the end of the line simultaneously with starting the production of another copy at the other end (and simultaneously with all the intermediate steps on other copies too). The clock sets the points in time when all ‘items’ (information) on the ‘production line’ move from the current stage to the next. As indicated above, the structure of real circuits is often more complex than that shown in Fig.1 and Fig.2, with feedback and feedforward of information, D0 D Q Q 0 D1 D Q Q 1 D2 D Q Q 2 D3 D Q Q 3 Clk Fig.4. A four-bit register built from D-type flip-flops. Practical Electronics | March | 2021 N egative edge (active clock edge) and multiple different paths through the system, rather than the simple ‘straight through’ structure depicted in Fig.1 and Fig.2. However, a simple structure is sufficient for our purpose of discussing the basics of timing in synchronous circuits. Although the production line analogy does not quite fit more complex structures, it reminds us of the step-by-step processing and the fact that it takes a number of clock cycles before an input at a given time will influence values inside the circuit and at the output. This processing delay is referred to as latency and should not be confused with throughput, which is the number of new input values/conditions per second the circuit can handle – often equal to the clock frequency. Register to register In order to consider the timing in more detail we need a slightly lower-level picture of the typical circuit structure than provided by Fig.1, where each block could have a complex internal structure. In general, a synchronous digital circuit comprises data storage, called registers, and function blocks which manipulate information. The function circuits are implemented with combinational logic. Combinational logic circuits do not contain any memory elements (flipflops or latches) so their outputs depend only on the current value of their inputs. Registers are sets of D-type flip-flops – one for each bit of data stored (see Fig.4). Of course, other types of flip-flop can be used in circuits, but the same basic principles of timing will apply. The functions are many and varied and include coding, decoding, finding the next value in a sequence and arithmetic functions such as adding. The information being processed by any function circuit is held in one or more registers connected to its inputs and the results, when ready, are stored in one or more resisters connected to the function block outputs. This is illustrated in its simplest form in Fig.5, where register R1 holds the data being worked on by the combinational logic CL, and R2 holds the results. This circuit is suitable for defining timing requirements in synchronous digital circuits. For the circuit in Fig.5, when the active clock edge occurs the register R1 loads new data. Specifically, the data on its D inputs is stored in the register and appears at its Q outputs. The register is not infinitely fast, so its outputs change a short time after the clock edge, this is referred to as the propagation delay of the register (we will call it TDR). Given that the register is typically a set of identical flip-flops, we can often assume that all its outputs update at more or less the same time. In Fig.5, when register R1 updates the inputs to the combinational circuit change, and after some time, its outputs will respond. Unlike the register, we cannot generally assume that all combinational logic outputs change at about the same time, in fact each output bit may change several times, producing various intermediate output values for a while, until all the effects of the input change have propagated though and the circuit settles. These intermediate outputs are called hazards or glitches. In terms of timing, we are mainly interested in the longest possible time the combinational circuit will take to fully settle in response to any input change. This value is referred to as the propagation delay of the circuit (we will call it TDCL). Unless the circuit has been specifically designed to be guaranteed ‘hazard-free’, we generally have to assume that the outputs may change somewhat unpredictably from the moment any input changes until the propagation delay time has passed. In a circuit in which information is fed back, R1 and R2 in Fig.5 may be the same physical register. This does not change any of the arguments made here about timing. A counter circuit provides a typical example of fed-back data – the combinational logic takes the current count value, adds 1 to it and presents this to the input of the same register. At the clock edge the register loads its own current value plus 1, thus incrementing the count. Delays and timing constraints Again, with reference to Fig.5, we know that the after an active clock edge the outputs of register R1 will update after delay TDR and the combinational logic will be outputting the final, stable value after a further delay of TDCL. On the next active clock edge, the output of the combination 43 is the hold time (Thold). Setup and hold times are illustrated in Fig.6. This timing diagram is for the purposes of defining timing parameters, it is not showing Data D0 D1 D2 expected circuit operation. Normally, data changes would TSet up TH old not be exactly on the setup and hold times as that would V alue of data is sampled/ stored Clock be too risky – some margin of at data edge error is needed. Designers must ensure that TDR circuits are configured so that Q D1 the setup and hold times for Data D1 appears all flips-flops are met under all at Q output operating conditions. For small simple circuits this may just Fig.6. Definition of setup and hold times (D-type flip-flop). be a matter of making sure the clock is not too fast, but in large complex designs timing analysis software logic will be loaded into register R2. It tools (not the same thing as a simulator) might seem that as long as the clock period can be used to find potential violations is greater than TDR + TDC, R2 will load the of these timing requirements. The values correct value. In reality, the clock period for the setup and hold times can be found has to be a bit longer than this because in flip-flop datasheets. of the way R2 (or any register or flip-flop) Fig.7 shows the various delays responds to changes on its data input. associated with register-to-register transfer A clocked flip-flop only changes its in a synchronous circuit. The minimum output under the control of its clock input. clock period must be greater than TDR + Changes on the data input have no effect on the output if it is not clocked. However, TDC + TSetup to make sure that the data data input changes do affect the internal loaded into R2 is valid. The crosshatched circuitry. If the data changes, the flip-flop’s part of R2’s D input waveform (which is internal circuitry takes time to settle in the combinational logic output) indicates response to that change. If the clock is the period when the combinational logic activated just after a data change, before may be outputting intermediate values or the internal circuitry has settled, the flipglitches before is settles. This value must flop may not function correctly. It may be guaranteed to settle before the setup load the wrong value or go metastable, time before the next active clock edge. potentially resulting in a much longer than If we find the value of TDR + TDC + TSetup normal delay before the output changes. for every register-to-register transfer in To help prevent these problems, flipthe circuit then the slowest value (plus flops are specified in terms of the time some margin for uncertainty) gives us that must pass after the data is changed the minimum clock period and hence before the active clock edge occurs – this maximum clock frequency for the circuit. is called the setup time (TSetup). Similarly, The discussion so far has simplified things a bit. In particular, the fact that the the data must not change for a certain schematic in Fig.7 shows the clocks wired time after the active clock edge – this together and depicts a single D Q In Out D Q clock waveform. In reality, the R 1 CL R 2 clock will arrive at every flipflop at a slightly TDC L TDR TSet up different time Clock because each path the clock Minimum clock period TC takes will have a slightly different Clock delay. In small circuits this TDC L TDR m ight not be TSet up noticeable, but it is a potential R 2 D input D0 D2 problem in larger Data must b e stab le b efore the setup time b efore the clock edge circuits (such as on ICs) where the clock is not Fig.7. Detailed timing for register-to-register transfers. Data must not change b etween these time 44 distributed simply by a wire to each flipflop but goes through sets of buffers (a clock tree) and/or relative wiring distances may be significant. Variation in clock arrival times is called clock skew and needs to be taken into account when working out if timing violations may occur. Asynchronous signals and metastability The previous discussion covers the basic requirements for preventing timing problems in synchronous circuits. If the requirements are met (with sufficient margin to account for any variability) then the circuit will not suffer timing problems – this is effectively guaranteed by design. The same does not apply when we have external asynchronous signals – they can change any time in the clock cycle, which means it is possible for them to change close enough to the active clock to cause timing violations (ie, within the ‘must not change’ time in Fig.6). Similarly, when signals cross clock domains, as outputs from stage 2 to stage 3 do in Fig.2, there is a possibility of timing violations. The situation is more complex than with asynchronous input because the clocks might have a specific relationship. If the clocks are derived from the same source and are powers of two different in frequency, then the situation is like the synchronous case and can be problem-free. More complex relationships may result in specific periodic violations. In cases where the clocks are independent and are likely to have some shift in relative phase and frequency with time, the situation may be similar to the asynchronous input case. Last month, we looked at the structure of latches – the basic circuits which can store a single bit. The fundamental operation is shown in Fig.8 – when the clock (or SR inputs) changes state (so as to store a bit) a closed loop of two inverters is created that is isolated from the input(s). Two such data latches in series, controlled by opposite clock levels, are used to form the edge-triggered flip-flops that we have focused on this month. Under normal operation the loop stores a good logic 1 or 0 (on the Q output, with the other inverter outputting the opposite logic level). In this situation the loop is in a stable state and will stay as it is, storing the bit, until the clock/SR inputs update the stored value, or power is removed. However, we have to remember that the circuit is actually handling voltages – what happens if the voltage at the input to the loop is not a good logic 0 or 1 when the loop is formed? If the loop happened to capture exactly equal voltages on the two inverter outputs, then it would be in a perfect state of balance and could, in theory, stay that way permanently – this is the Practical Electronics | March | 2021 Clock Data Q Data Q Fig.8. Fundamental operation of a latch circuit – the clock switches the circuit into closedloop form to store the data. The mechanism by which this is achieved depends on the type of latch/flip-flop (see Circuit Surgery, February 2021). metastable condition that we discussed in the context of the SR flip-flop last month. In last month’s example the problem was caused by forcing an SR flip-flop to store a logic 1 on both inverter outputs. The design of data latches prevents this from happening, but voltages part way between good logic 0 and 1 can be stored by a data latch if the input voltage is changing between 0 and 1 when the loop is closed. As discussed last month, the potentially infinite time in the metastable state will not happen in a real circuit – some difference or perturbation will result in the latch moving to one of its stable states. However, this may take much longer than the normal propagation delay of the latch. We illustrated this last month with an LTspice transistor-level simulation of the latch loop. That example used the two-1s SR scenario, but a data latch storing a mid-supply voltage will behave in a similar way with a long delay. The loop circuit in Fig.8 will store an intermediate voltage if metastability occurs, but in a typical flip-flop the loop is not directly connected to the outputs – it may be the first of two latches and there are likely to be buffer gates at the output. This means that a metastable flip-flop may always output a good logic level but could exhibit behaviour such as very long delays or initially outputting one value and then changing. The waveforms in Fig.9 show how a data latch may go metastable. There is a period of time as the data changes (metastability window, T0) when clocking the latch will result in metastability. If metastability occurs then the latch will take an amount of time, called the ‘resolution time’ (TR), before it returns to one of the stable states. For asynchronous inputs we have no control over the relative signal timing, so we cannot guarantee to prevent metastability. We have to deal with it in terms of probability. The probability of errors occurring in the circuit is related to the probability of a latch becoming metastable and the probability that it is then still metastable after the point at which this may cause an error. The probability of a latch becoming metastable is basically the proportion of the clock cycle taken by T0, that is T0/TC. If we know the longest resolution time that can occur without causing a circuit failure, we can find the probability of this occurring – it is an exponential function related to the RC time constant of the latch loop. Such probability calculations can guide designers to reduce expected error rates to acceptable levels; for example, by adding synchroniser circuits. We will look at this in more detail in a future article. TC Clock T0 D1 Data L atch captures intermediate voltage TR Exi t from metastab ility Q Fig.9. Latch metastability waveforms. ESR Electronic Components Ltd All of our stock is RoHS compliant and CE approved. Visit our well stocked shop for all of your requirements or order on-line. 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