Static Timing Analysis

Project : Liquid Crystal Display
Build Time : 04/07/17 12:15:12
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock_1(FFB) Clock_1(FFB) 1.000 kHz 1.000 kHz N/A
CyHFCLK CyHFCLK 3.000 MHz 3.000 MHz N/A
Clock_1 CyHFCLK 1.000 kHz 1.000 kHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 3.000 MHz 3.000 MHz N/A
CySYSCLK CySYSCLK 3.000 MHz 3.000 MHz N/A