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Actual size of this
1974 core memory
“card” – 245 x 280mm
– is a little larger than
this page. Capacity is
a whopping (for the
time!) 4KB x 9 bits and
it consists of 36,864 of
the tiny ferrite beads
enlarged in the
inset below.
By contrast,
here’s a modern
4GB memory card
– one million times
more capacity –
shown at about the
same scale (it’s
actually 15 x 11mm)!
The latest iterations
of this card offer up to
256GB of memory.
While cleaning up the garage, I came across this 40-year-old ferrite
core memory module, removed from a Mohawk MDS2400. Its capacity
is 4KB (of 9 bits). In these days of hundreds of gigabytes of memory in
cards no bigger than your fingernail, I wondered how many SILICON
CHIP readers would have ever seen this type of memory, or even seen a
‘bit’ in its rawest form.
By Brian Armstrong
96 Silicon Chip
Photos by Geoff Barton
siliconchip.com.au
Here’s the type of equipment this core memory card came from, the Mohawk MDS2400. This is
actually a 1975 model, even later than we’ve been talking about – but is typical of the era (where
are the dudes with the white dustcoats?). The most amazing part of it all is that your pocket
calculator probably has more computing power and memory than this room full of equipment.
siliconchip.com.au
would do an emergency retract, then
scare you as they nearly took off your
hand at the same time.
What is core memory?
Core memory, or more properly
ferrite core memory (but sometimes
referred to as magnetic memory), was
first developed during the late 1940s
and early 1950s.
Some references claim this was part
of the “Whirlwind” computer project
at MIT; others state that An Wang (of
Wang Computer fame) was responsible
while working at the Harvard Computing Laboratory.
As late as the 1970s, equipment was
still being made which used a form of
core memory. It was renowned for its
reliability but was very expensive to
build, as it is based on thousands of
tiny ferrite cores with (normally) three
wires passing through every one.
When magnetised, each core held
a single bit as a 0 or 1, based on the
direction of the magnetic flux around
the core (clockwise or anti-clockwise,
respectively).
The magnetic orientation was
changed by current running through
the core in a particular direction. This
current was controlled by an arrangement of “X” and “Y” wires, both of
which passed through the core.
Two half-strength pulses
The way a particular core was
selected was to send a half-strength
Y LINES
I
n 1974, one of
these 4K cards,
or panes, would
have set you back around
$4500. Given the average Melbourne house price in 1974 was
about $25,500, it gives you some idea
of their value. In 2014 dollars, think
somewhere north of $100,000 per card
and you’re not far wrong!
Apart from their physical construction, there are two fascinating aspects
of core memory. One is that it is nonvolatile (ie, it holds memory when
powered off) and two, you can actually
see it. Bit by bit!
Companies could also supply and
ship core memory pre-programmed.
I worked on mid-range servers and
accounting machines in the eighties, which used both core and MOS
memory.
When I think back, I also remember
working on the old CDC 14-inch drives,
which had a fixed and removeable
platter and were a total of 20MB (yes,
that’s written correctly – 20MB, not
GB) in capacity.
Those days, we also fixed a majority
of the items to component level, and
aligned servo and data heads on the
disk drives with an oscilloscope and
an Allen key.
I will never forget this, as the alignment was such a fine adjustment that
if you moved it too fast, the heads
LOGIC
“0”
LOGIC
“1”
Fig.1: whether the ferrite core stored
a “0” or “1” depended on its magnetic
flux, which in turn depended on the
direction of the current pulse that
was originally sent through it. Once
magnetised, the core maintained the
memorised state almost indefinitely,
even if power was removed.
X LINES
Fig.2: the magnetising was actually
controlled by two wires, each
being fed half the current required
to magnetise the core. When two
energised wires passed through a
core, the currents added and the core
was magnetised.
March 2014 97
SENSE/INHIBIT LINE
Y SELECT LINES
1/2
Y LINES
4
3
2
1
1
2
4
3
1/2
X LINES
SENSE
WIRE
In this extra close-up, you can clearly see the X and Y lines passing through their
rows of ferrite beads, along with the sense wire passing through all the beads.
Pairs of beads were oriented so that, as far as possible, they were opposite to
their neighbours to minimise the chance of magnetic interference.
pulse down the relevant X wire and
a corresponding half-pulse down the
Y wire.
Half-strength currents were not
enough to fully magnetise the core
but the coincident-currents of both
lines would be enough to then fully
magnetise the targeted core and change
that bit’s magnetic flux direction accordingly.
Putting this simply, only where
these wires intersected, would the
total amount of current be enough to
magnetise the polarity of that bit. All
others would not be impacted as they
would either not receive a pulse, or
only a half strength pulse if in the
same X or Y lines.
Once a core was magnetised with
sufficient current, the magnetic
properties were so strong that they
would hold there almost permanently,
just like a normal magnet, until “rewritten”.
Sense wire
Core memory also had an additional
‘sense’ wire that ran through all cores
in the same pane (window). This was
used to read (sense) magnetic properties to identify the bit state.
In early core memory, another separate wire, called the inhibit line, was
also used when multiple panes were
interconnected.
The inhibit line would be used
when multiple panes of memory were
connected together to save X/Y selection lines.
This was performed by joining all
corresponding X lines together, and
98 Silicon Chip
all corresponding Y lines together,
then selecting the individual pane
by enabling a reverse current on the
inhibit line on all other panes. This
effectively dropped the current on the
ones not required to a point where the
core would not be magnetised.
Later releases of core memory incorporated the inhibit and sense functions
in the same wire as they were used at
different times.
To read a single bit of core memory,
the circuitry attempted to flip the bit
to whatever polarity the machine regarded as a 0 state, by driving current
down the selected X and Y lines that
intersect at that core in one direction.
(See Fig.3).
If the bit was already 0, the physical
state of the core was unaffected and
no change pulse was received on the
sense line.
If the bit was previously 1, then the
core changed magnetic polarity. This
change, after a short delay, induced
a voltage pulse into the ‘sense’ line.
This is due to the hysteresis of the
core material. It’s like a light globe: if
it’s off and you apply power (change
state), there’s an initial spike due to
the extra power on current.
However, if it was already on, and
you applied the same power, then no
extra current would be required and
therefore no spike. Although not quite
the same, it was a simple way to think
of it operationally.
Detecting the pulse meant that the
bit contained 1. Absence of the pulse
meant that the bit contained 0. The
delay in sensing the voltage pulse
X SELECT LINES
Fig.3: an additional wire which
passed through all cores sensed any
change in the cores and identified
the bit state of the changed core. This
sense wire can be seen through some
of the cores in the enlargement pic
above left (the blue wire). In most
cases it’s hidden underneath.
is called the access time of the core
memory.
Following any such read, the bit
was set to 0 regardless of its original
state, which is why core memory had
the term ‘destructive reads’: An operation that reads the contents of a core,
erasing the contents while doing it.
(see Fig.5).
This is also why it was immediately
followed by a write, which would reset
its original state if found to be a one.
This ensured that the initial state
of the memory was not changed by
reading it, as long as power was not
interrupted immediately following the
read operation (see Fig.6).
To write a 1 bit, the required X and
Y lines were pulsed with current in
the opposite direction of the read operation. As with the read, the core at
the intersection of the X and Y lines
changed magnetic polarity. This then
magnetised the corresponding core,
in the opposite direction (see Fig.4).
For multiple panes configured in
word arrangements, each corresponding pane row was connected to the next
and each corresponding pane column
connected to the next.
A zero was then accomplished by
using the inhibit line. To write a 0 bit
(in other words, to inhibit the writing
of a 1 bit), the same amount of reverse
direction current was also sent through
the Inhibit line. This reduced the net
current flowing through the respective
core to half the select current, inhibiting change of polarity on that pane.
The access time plus the time to
rewrite is the memory cycle time.
siliconchip.com.au
SENSE/INHIBIT LINE
SENSE/INHIBIT LINE
3
2
1/2
4
Y SELECT LINES
1/2
4
Y SELECT LINES
Y SELECT LINES
1/2
SENSE/INHIBIT LINE
3
2
4
3
2
1
1
1
1
2
3
4
Fig.4
1
2
3
4
Fig.6
Fig.5
1
2
3
4
1/2
1/2
1/2
X SELECT LINES
X SELECT LINES
X SELECT LINES
Fig.4 (left) shows the initial state of a sample memory address. Notice in this scenario address X3:Y4 state=1. This was
previously selected by driving half current down theX3 line and half current down the Y4 line in a 1 state polarity.
Green=1, Red=0. Fig.5 (centre) shows a destructive read. Address X3:Y4 is sent half current zero state polarity down the
Y4 line and another half down the X3 line. As the bit was effectively ‘flipped’, where the state changed from a 1 to 0, a
delayed pulse is received on the Sense line. The sensing circuitry then knows that the read state was initially a one. Had
the initial state been a zero, there would be no change and therefore no sense pulse. Fig.6 (right) shows a write after the
read in Fig.5. In this scenario, the bit is set back to its initial state of 1. A pulse on the sense line will also be received after
the change as confirmation, as the bit flipped back.
It sounds strange to comment on
now, but I do remember when I have
seen people repair memory at times.
This was normally caused by a dry
joint, or by dropping the actual PCB
and dislodging parts.
A magnifier was required, along
with special tools. The first magnetic
cores were also much larger than the
ones pictured. The layout of each core
was also paramount to stop interference between them.
Core memory and “core” chips
Who could have imagined then, that
miniscule integrated circuits would
be created that could replace these
that were massively larger in capacity or even today, where the complete
memory chip can basically detect and
repair bad reads itself (EDAC) and be
a complete throwaway on failure – at
a cost of a cup of coffee!
While the names might be the same,
magnetic core memory and modern
“core” chips have virtually nothing
in common – for a start, core chips
are microprocessors, not memory. The
still-used term “core dump”, though,
does have its origins in ferrite core
memory, where all contents were
erased by a special command.
Some may say that we do not need
to know the finer details of ‘what’s
inside’ but I am sure that a majority
of readers would have opened a working electronic device, just to see how
it worked.
Whether they ever got it back together again – and it worked – well,
who knows!
SC
siliconchip.com.au
DIGITAL ELECTRONICS
– circa 1974
We couldn’t resist making mention of
this authoritative reference book, written
by our own Jamieson Rowe, first published as a series in “Electronics Australia”
during the late 1960s and then reprinted
in several editions up to the mid 1970s.
The field of digital electronics was still,
if not in its infancy, a very young child and
Digital Electronics, the book, was used
by many universities, TAFE colleges and
trade schools as a major textbook for students cutting their teeth on matters binary,
programming and the still black science
of computers and computing.
It’s quite enlightening reading through
this book to see what was then “state
of the art” in equipment – including a
detailed description and analysis of
Ferrite Core Memory (on page 85).
It’s right up there with Fortran, Cobol and Algol, with punched cards,
with drum memories and PDP/8
computers! Even Cathode Ray Tube
monitors were described as a recent
invention. . .
While now out of print for a few
decades, the principles and theories
explained in Digital Electronics still
hold good even today, even if techniques and equipment have long been
superseded and consigned to history,
seen only in museums and in nostalgic
articles, as the one presented here by
Brian Armstrong.
March 2014 99
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