Fullscreen HTML5Med Res (??MB)HTML4

CLASSiC DAC Pt.2 Build it & get better sound from your TV, DVD/CD player or set-top box Last month, we introduced our new CLASSiC DAC which has three TOSLINK inputs, three S/PDIF inputs, a USB input, SD card playback and is based on a Cirrus Logic CS4398 DAC chip. Unless you have absolute top of the line equipment, the CLASSiC DAC will improve audio performance and eliminate hum loops which can occur when using analog inputs in a multi-source system. T O SUMMARISE the most important features of our new DAC design, it supports sampling rates up to 192kHz, has a built-in hifi headphone amplifier, seven digital inputs including USB from a PC, plays WAV files from an SD card at up to 96kHz/24-bit resolution and has LED indication of the current sampling rate. It is powered by an AC plugpack so no mains wiring is required and fits into a slimline instrument case with custom front and rear panels. While the double-sided PCB is quite 18  Silicon Chip compact, the circuit is quite large. This month we will describe it in detail, as well as presenting some performance graphs and data. Circuit description The circuit for the CLASSiC DAC has been split up into four diagrams. Let’s start with the digital audio receiver portion, shown in Fig.4. At left are the seven digital audio inputs. The first three are TOSLINK inputs which convert light pulses on optical fibres into a square wave out- put, available at pin 1. These signals are AC-coupled to inputs 4, 5 and 6 of the CS8416 digital audio receiver (pins 10, 11 & 12). These inputs are shown as 1-3 by the status LEDs and are at the left rear of the case. As mentioned last month, the CS­ 8416 has internal input amplifiers which provide a DC bias level so we can simply AC-couple the outputs of the TOSLINK receivers to it. The TOSLINK receivers contain high-gain, high-bandwidth amplifiers which can be upset by power supply siliconchip.com.au By NICHOLAS VINEN noise. As a result, the power supply for each is isolated using a 100µH RF choke and bypassed by a 100nF ceramic capacitor. Power comes from the 3.3V or 5V rail, depending on what type of TOSLINK receivers are fitted and this is selected using link JP1. The micro uses P-channel Mosfet Q13b to switch off this supply (by switching off the ±15V rail) when the unit is in standby. The three S/PDIF inputs are numbered 5-7 and connect to inputs 1, 2 and 3 of IC1 (pins 3, 2 & 1). Each has a 75Ω termination resistor to set the correct input impedance and the signals are coupled directly to IC1 via 10nF capacitors. The signal level is typically 0.5-1V peak-to-peak and the CS8416’s internal amplifiers boost it to 3.3V to suit its decoding circuitry. USB audio CON5, a full-size Type-B socket for connection to a PC, is the USB audio siliconchip.com.au input. The USB signal is decoded by IC2, a PCM2902E USB digital audio receiver chip. It has minimal support components, mainly consisting of bypass capacitors. 10µF capacitors are connected between IC2’s analog inputs and ground so that should your computer be set up to monitor the inputs, you will get silence rather than noise. The USB GND (shown with a different symbol) is not directly connected to the circuit ground; it is joined by a 100µH axial RF choke (L7) which prevents high-frequency ground noise from the USB line from coupling into the DAC. IC2 connects to the USB signal lines via 22Ω series resistors, to set the correct line impedance, plus a 1.5kΩ pullup to indicate its presence to the host PC. A 12MHz crystal provides the USB clock. The PCM2902E is powered from USB 5V, with an RC filter (2.2Ω/1µF) to limit the in-rush current and provide a degree of supply rail filtering. When a PC is connected and playing audio, IC2 transmits S/PDIF data from pin 25 (Dout). Like the other S/PDIF signals, this is coupled to IC1 via a 10nF capacitor, in this case to its input 0 (pin 4). However, it is numbered input 4 on the front and rear panels. We have also connected IC2’s digital input (Din, pin 24) to the GPO0 output of IC1 via a 470Ω resistor. We can configure GPO0 to transmit the signal from another input. This may be useful for monitoring or recording from one of the signal sources without having to unplug it from the DAC and connect it directly to the PC. The series resistor prevents damage to IC2 if USB power is not present, limiting the current in such a condition to 7mA peak and 3.5mA RMS. In practice though, we turn off the GPO0 signal when IC2 is not active. Note that the protection resistor forms a low-pass RC filter in combination with the Din pin capacitance but the corner frequency March 2013  19 The rear-panel view of the CLASSiC DAC. There are three TOSLINK (optical) inputs, a USB audio input, three S/PDIF (coaxial) inputs and two audio output sockets. The power socket (to connect a 9VAC plugpack) is at far right. is high, allowing the S/PDIF signal to pass through unaffected. The SSPND-bar output of IC2 (pin 28) indicates whether it is powered and connected to the PC. A 1MΩ pull-down keeps it low when IC2 is not powered. When it goes high, the DAC automatically switches to the USB input. IC2 supports a maximum sampling rate of 48kHz. If the selected input has a higher sampling rate, the computer cannot monitor or record the audio. If you want to play back audio with a higher sampling rate from your PC, you must have a capable sound card with its digital output connected to one of the other inputs. Digital audio receiver chip Digital audio receiver IC1 is powered from the 3.3V rail, with its analog voltage at the VA pin (pin 6) filtered using a 100µH RF choke and parallel 100µF and 100nF capacitors. The analog pin powers its internal phaselocked loop (PLL) which recovers the audio clock rate. It’s important that this supply is quiet and ripple-free for low clock jitter and thus low audio distortion. The PLL filter components are connected between the FILT pin (pin 8) and analog ground (AGND, pin 7). We are using the recommended component values to suit the widest range of sampling rates, ie, 32-192kHz. The VA supply bypass capacitors are also connected directly to AGND. 20  Silicon Chip The digital supply pins (VL & VD, pins 21 & 23) share 220nF and 100µF bypass capacitors. The 47kΩ pull-up resistor at pin 26 (SDOUT) sets IC1 into software-controlled control mode while a 100kΩ pull-down on reset (RST-bar, pin 9) disables the chip until the microcontroller is ready and pulls RST-bar up. Note that IC1’s eighth input, RXP7 (pin 13), is connected to the microcontroller (shown elsewhere) via a capacitor. It receives audio on this input from the micro when it is playing WAV files from an SD card, via a track labelled SPDIFO. Regardless of which input is active, once IC1 has received and decoded the digital audio stream, it produces an I2S (inter-IC sound) serial output on three lines: audio signal data (SDOUT, pin 26), bit clock (OSCLK, pin 27) and sample clock (OLRCK, pin 28). These are routed to the DAC IC, which we will look at later, using tracks labelled DASD, DABCLK and DASCLK respectively. IC1 also generates a master clock at RMCK (recovered master clock, pin 24). This is at a fixed ratio to the bit clock of either 128 times or 256 times, depending on how it is configured. Virtually all oversampling DACs require a master clock to run their internal digital circuitry. IC1 has a clock input, OMCK, which can be used for various purposes. We are using it as a reference clock; IC1 can calculate the ratio of OMCK to RMCK and this allows the microcontroller to determine the sampling rate of the incoming audio stream. We’ll explain how the reference clock is generated later. The remaining pins on IC1 are used to control it. Specifically, there is an SPI bus which the micro uses to read and write its internal registers, comprising CSDO (data to IC1), CSDI (data from IC1), CSCK (bit clock) and DARCS (chip select). There are also three general purpose output (GPO) pins. As mentioned, GPO0 is used to send digital audio data to the USB interface. GPO1 and GPO2 are connected to the microcontroller and are used to signal any errors or changes in the audio format. They also allow the micro to monitor the state of the unselected inputs, which it can do by routing the signal, one input at a time, to a GPO pin. Digital-to-analog converter Now take a look at Fig.5, which shows the DAC circuitry at left and the headphone amplifier on the right. The I2S audio signals are fed into pins 3-6 of IC3, the CS4398 DAC. Digital audio serial data (DASD) goes to SDIN, the bit clock (DABCLK) to SCLK, the sample clock (DASCLK) to LRCK and the master clock (DAMCLK) to MCLK. IC3 shares the SPI control bus with IC1, ie, CSDO, CSCK, CSDI are connected in parallel while DACCS is its dedicated chip select line from the micro. Only one chip select line siliconchip.com.au Q13b Si4804 L1 100 H TOSLINK INPUT1 S2 3 Rx1 L4 100 H +3.3V JP1 +3.3V +3.3VF +5V 100nF 100 F G2 10nF 1 D2 10 11 L2 100 H 12 3 3 100nF 2 10nF 1 Rx2 1 TOSLINK INPUT3 9 8 3 5 100nF 10nF 1 Rx3 RXP5 RXP6 SDOUT RXP1 OSCLK RXP2 OLRCK RXP3 OMCK IC1 CS8416-CZ L3 100 H 4 10nF 10nF 2 13 220nF CON1 AD1/CDIN SCL/CCLK FILT SDA/CDOUT RXN AD2/GPO2 RXP0 GPO1 RXP7 GPO0 AGND 7 10nF S/PDIF INPUT1 RMCK AD0/CS RST 1k 100k 47k RXP4 DARRS 2 23 VD 21 VL 6 VA 2 TOSLINK INPUT2 220nF 100nF +15V 100 F 16V 26 DASD 27 DABCLK 28 DASCLK 25 OMCK 24 DAMCLK 14 DARCS 15 CSDO 16 CSCK 17 CSDI 18 DARGP2 19 DARGP1 20 DARGP0 DGND 22 10nF SPDIFO 75 10nF S/PDIF INPUT2 470 10 F 75 10 VccI 28 CON3 10nF S/PDIF INPUT3 27 1M 75 8 1 F 9 2.2 3 1 F CON5 1 2 3 4 USB 10nF SSPND CON2 2 22 1 5 USB GND 6 7 12 L7 100 H 13 D2 D2 D1 D1 G2 G1S2 S1 SC 2013 CLASSIC DAC 25 Din 24 23 VccxI VddI SEL0 SEL1 Vccp2I Vbus Vccp1I 19 1 F 14 10 F 10 F 10 F 1 F IC2 PCM2902E D– 1 F 17 1.5k 22 4 Si4804BDY Dout SSPND Dgnd D+ VoutL DgndU HID0 VoutR HID1 HID2 XTO VinL XTI VinR 26 16 15 20 21 1M X1 12MHz Vcom AgndC AgndP AgndX 11 18 22 33pF 33pF DIGITAL AUDIO RECEIVER SECTION Fig.4: the digital audio receiver circuit of the CLASSiC DAC. It has seven digital inputs (three TOSLINK, three S/PDIF & one USB), shown at left. Six of these feed directly into digital audio receiver IC1, while IC2 is required to convert USB audio to S/PDIF before IC1 can decode it. IC1 outputs I2S serial audio data on the five lines shown at upper-right while communications with the microcontroller is via the seven pins below them. siliconchip.com.au March 2013  21 +15V 100 µF 2x 100 µF 100nF 100nF 7 VD DASD DABCLK DASCLK DAMCLK CSDO CSCK CSDI DACCS +5V 2x100nF +3.3VF 3 4 5 6 9 10 11 12 27 17 14 22 VLC VLS VA VREF AmuteC SDIN AoutA+ SCLK LRCK AoutA– MCLK VQ CDIN CCLK CDOUT DAC RST 13 28 1 100k 2 23 DSD_A 24 18 20 19 DSD_B 6 .8 nF 1.5k 1 G1 47 µF 100Ω 4 ZD1 18V Q1b S2 S1 D1 K Q1: Si4804 Q1a CON6 L OUT 10nF –15V 1.5nF BmuteC +5V 470Ω 1.5k 100k B 240Ω 6 .8 nF 1.5k K 100pF 100Ω 6 A ZD4 18V D2 Q2b G2 –15V 5 A Rmute 4.7nF 750Ω 100 µF Q4 BC559 100k 470Ω 22nF E C 15 100nF 8 750Ω 26 G2 100nF IC4a 2 A D2 ZD2 18V Lmute 3 220 µF 1.5k A –15V 220 µF FILT+ DSD_SCLK DGND REFGND AGND 8 21 16 100Ω 100k 4.7nF 22nF K 100pF 470Ω 10k AoutB– Q3 BC559 C 10k 470Ω AD0/CS RST E 25 10 µF AoutB+ B 240Ω IC3 CS4398-CZ BmuteC AmuteC 100k G1 S2 S1 IC4: LM833 IC4b 7 47 µF 100Ω D1 K ZD3 18V Q2: Si4804 Q2a CON7 R OUT 10nF 1.5nF +15V 10 µF 50V –15V SC 2013 CLASSIC DAC DAC, LINE OUTPUT & HEADPHONE AMPLIFIER SECTIONS Fig.5: the I2S serial audio data stream is fed into DAC IC3 and the resulting analog signals are filtered by dual op IC4 and associated passive components. IC4a & IC4b then feed the line outputs, CON6 & CON7. Dual Mosfets Q1 & Q2 provide output muting. The headphone amplifier shown at right is based on dual op amp IC6 plus six transistors. It has a selectable gain of 0dB or 12dB. The output signal is fed to headphone socket CON8 via two RLC filters to ensure stability. is pulled low at a time so the other chip ignores any data on the bus. As with IC1, the micro controls the reset line which is pulled low by a 100kΩ resistor, disabling the DAC until the micro is ready. IC3 has a 3.3V supply for its digital circuitry and 5V for analog. The “3.3VF” supply is derived from the main 3.3V supply via an additional LC filter (shown on Fig.10), to minimise the chance of any digital supply noise coupling into the analog portion of the circuit. Both supplies have multiple ceramic bypass capacitors located close to the IC, as well as larger electrolytics in parallel. Both the FILT+ pin (pin 15) and VQ pin (quiescent voltage, pin 26) have external capacitors connected 22  Silicon Chip to filter the internal IC voltages. The audio output appears at pins 23 & 24 (left) and 20 & 19 (right). These are differential outputs and are fed to identical filters. In the article last month, we explained how we tweaked these filter component values to give better rejection of any common mode signal between the differential outputs, as well as a flatter frequency response. Dual op amp IC4, an LM833, is the active part of these filters and also converts the differential signals to single-ended outputs. The filters remove as much of the high-frequency switching artefacts as possible while leaving audio-frequency signals intact. The outputs are biased to +2.5V so they are AC-coupled using 47µF capacitors and DC biased to 0V. Following this, an RC filter (100Ω/10nF) further reduces the remaining DAC noise. While the outputs are silent, IC3 drives the AmuteC and BmuteC lines low (pins 25 & 18). These are also held low while IC3 is reset by 10kΩ pull-down resistors. In this condition, current is sunk from the bases of PNP transistors Q3 & Q4 and these then charge up the gates of dual Mosfet pairs Q1a/Q1b and Q2a/Q2b to +5V. Q1 & Q2 are thus on and they short the audio outputs to ground. The 100Ω resistors limit the current from IC3 in this condition to a low level. By shorting the outputs to ground, any clicks or pops that might be generated from the DAC when powering up or down or switching sampling rates, etc are suppressed. A pair of 47µF casiliconchip.com.au +15V 10 µF 50V 4.7k 100nF C B E K –15V 10k 100Ω VR1b 10k LOG 100 µF 4.7k ZD7 10V 8 3 IC6a 2 VR2 2k C B 1 Q7 BC337 4.7 µH * A 22Ω K ZD8 10V 10 Ω* 22Ω D1 0.1V Q16a G1 A E B –15V Q6 BC327 G2 S1 Q16: Si4804 S2 Q16b C 4.7k 1k 0.1V 10 µF E 4 Q5 BC337 D2 3.0k HEADPHONES 100nF –15V 12dB 0dB JP2: LEFT GAIN Lmute CON8 100nF +15V IC6: LM833 4.7k C Q8 BC337 B ZD5 10V 10k 100Ω VR1a 10k LOG 100 µF VR3 2k 5 IC6b 4.7k 7 B C E Q10 BC337 4.7 µH * A 22Ω 10 Ω* K 22Ω 4.7k A E siliconchip.com.au Q15b C D2 Si48 0 4 BDY Rmute * 10 Ω 1W RESISTOR WITH 1m LENGTH OF 0.4mm DIA ECW WOUND AROUND IT (70T APPROX). The two audio outputs are also connected to potentiometer VR1 (the headphone amplifier volume control) via another pair of 100Ω resistors. G2 S1 Q15: Si4804 S2 –15V 12dB 0dB JP3: RIGHT GAIN Headphone amplifier Q15a Q9 BC327 3.0k pacitors block the +2.5V DC bias from those same outputs. The 100Ω series resistors isolate any capacitance connected to RCA outputs CON6 & CON7 (eg, cable capacitance) so it won’t destabilise the op amp filter circuits. Back-to-back 18V zeners (ZD1-ZD4) prevent the gate-source voltages of the output Mosfets from exceeding the ±20V rating. This should not happen during normal operation but since the supply rails are ±15V (ie, 30V total), this could possibly happen under some circumstances. D1 0.1V G1 B 1k 0.1V 10 µF ZD6 10V 6 PHONES DETECT E K ZD1–ZD8 A K These are intended to prevent any noise that may be picked up in the tracks to VR1 from being fed back to the line outputs. VR1’s tracks also form the current path to ensure that the DC at the line outputs is 0V. The audio signal is attenuated by VR1 (depending on the pot setting) and then fed to the non-inverting inputs of op amps IC6a & IC6b via 100µF capacitors. DC bias is provided by a 4.7kΩ resistor. The capacitor values are high and the resistor values low because, like IC4, IC6 has bipolar input transistors and so has a relatively high input bias current. A low bias resistor minimises DC offset at the output, for reasons we’ll explain shortly. IC4 & IC6 are both LM833 low-noise op amps, still among the best available. BC327, BC337, BC559 D2 D2 D1 D1 G2 G1S2 S1 B E C The two halves of dual op amp IC6 each drive a current booster circuit in order to deal with headphone impedances as low as 8Ω. The two circuits are identical so we’ll just look at the left-channel circuit based on IC6a. The headphones plug into CON8 and are driven by a standard emitterfollower pair consisting of Q5 (NPN) & Q6 (PNP), each with a 22Ω emitter resistor. These provide some local feedback for Q5 & Q6, limit peak current and dissipation during output short circuits and help to stabilise the quiescent current by providing some negative feedback for the bias circuit. Q5 & Q6 can handle up to 500mA each but can only safely dissipate 625mW continuously. The 22Ω emitter resistors and 10V zener clamps limit March 2013  23 1 CLASSiC DAC THD vs Frequency 05/02/13 11:18:09 1 0.5 0.5 0.2 0.2 Line Outputs, 80kHz BW 32 Headphones, 80kHz BW Crystal DAC, 80kHz BW (APx525) Line Outputs, 20kHz BW 32 Headphones, 20kHz BW 0.02 0.01 0.1 2 x 32Ω 2 x 16Ω 2 x 8Ω 0.05 THD+N % 0.1 0.05 THD+N % THD vs Power, 1kHz, 20kHz BW, 2ch 05/02/13 11:29:09 0.005 0.02 0.01 0.005 0.002 0.002 0.001 0.001 0.0005 0.0005 0.0002 0.0001 0.0002 0.0001 .1 20 50 100 200 500 1k 2k Frequency (Hz) 5k 10k 20k Fig.6: total harmonic distortion plus noise (THD+N) vs frequency. The three main curves shown are for the new DAC from its two outputs (line out and headphones) plus a comparison with the previous Crystal DAC design. Headphone power level is 10mW per channel. The thin lines show show the results with a 20Hz-20kHz bandpass filter, to remove most of the ultrasonic noise. .2 .5 1 2 5 10 20 Power (Milliwatts) 50 100 200 Fig.7: THD+N vs power for the headphone output into three different common load impedances. For head­ phones with impedances above 32Ω, performance should be similar to (possibly, better than) the 32Ω case up to 50mW. In all cases, we are showing continuous power with both channels driven; for program material (ie, not just a sinewave), more peak power will be available. CLASSiC DAC Performance Graphs While the design of the CLASSiC DAC is much more compact and only uses one double-sided PCB compared to our origi- nal design back in 2009, its performance is considerably improved. The two main contributing factors to this improvement is the use of the Cirrus Logic CS4398 in place of the Burr-Brown DSD1796 DAC chip and the careful layout of the PCB. peak current to around (10V - 0.7V) ÷ 22Ω = 423mA but under this condition, the dissipation in Q5/Q6 will be around 423mA x (15V - 10V) = 2W and even more in the emitter resistors. However, the ±15V rails will quickly collapse under this sort of load so this brief period of high dissipation shouldn’t cause any damage. small standing current through the emitter resistors. A 10kΩ resistor across VR2 prevents excessive current through Q5 and Q6 should VR2’s wiper briefly go open circuit while it is being adjusted. Q7’s collector current (and hence some of the drive current for Q5 & Q6) is provided by a pair of 4.7kΩ resistors from each supply rail. A 10µF capacitor across Q7 prevents signal modulation of these currents affecting AC performance. Op amp IC6a drives Q6’s base directly and it also drives Q5’s base through a 10µF capacitor (ie, it’s AC-coupled). It also drives Q5 via a DC path through VR2 and Q7. With this configuration, in the quiescent condition, IC6a’s output is slightly below ground (by around 0.6V). Since the feedback voltage for IC6a comes from the junction of the emitter resistors rather than the op amp output, this is automatically compensated for. Normally, the headphone amplifier stage operates with no gain. With a full-scale input of 2V RMS from the DAC, it can deliver a maximum of 2V2 ÷ 32Ω = 125mW into 32Ω headphones before clipping. Power delivery for lower load impedances is less due to power supply current limiting. The gain is set to one by a jumper link on JP2, shorting out the 3kΩ resistor. For higher impedance headphones (eg, 600Ω), a higher output voltage is required to get a decent amount of power. In this case, JP2 can be moved to the other position, inserting a 4:1 voltage divider in the feedback path (3kΩ/1kΩ) and thus increasing maximum output to over 8V RMS. However, this also amplifies the DAC and op amp noise, so it should be avoided when driving lower impedances. The amplifiers are isolated from the headphones with RLC filters, each comprising a 4.7µH inductor in parallel with a 10Ω resistor, with a 100nF capacitor to deck. This is primarily so that any reactance connected to CON8 (again, cable capacitance, or whatever) doesn’t destabilise the amplifier circuits. Bias voltage For good performance, the amplifiers are operated in Class B mode with about 10mA through transistors Q5 & Q6 in the quiescent condition. We have seen and published circuits in the past which use a pair of diodes or LEDs to set this current but that’s a bit hit-and-miss. Instead, in this circuit, we are using a traditional Vbe multiplier consisting of NPN transistor Q7 and trimpot VR2. Q7 is the same type as Q5 and is thermally bonded to it so that their base-emitter voltages track closely. VR2 is adjusted so that the voltage between Q7’s collector and emitter is just high enough to give a 24  Silicon Chip siliconchip.com.au +3 Frequency Response, 10mW 05/02/13 13:49:14 +2 +1 Relative Power (dBr) 0 -1 Line outputs Headphones, 32Ω Headphones, 16Ω Headphones, 8Ω -2 -3 -4 -5 Fig.8: the frequency response is flat from less than 10Hz up to 20kHz. High-end rolloff is greater for lower load impedances such as 8Ω but there’s really nothing to write home about here. Deviation is less than 0.1dB over the audible frequency range. -6 -7 -8 -9 -10 10 20 50 100 200 500 1k 2k Frequency (Hz) 5k 10k 20k 50k Figs.6-8 show the critical performance figures for the CLASSiC DAC. The distortion and noise from the line outputs is similar to the Crystal DAC (February 2012), which also used the CS4398 IC but the new design is slightly better at the high-frequency end, due to the improved low-pass filter. By the way, to compare this graph to those published in the February 2012 Crystal DAC article, note that these graphs were produced with an Audio Precision System Two while we used an APx525 for the Crystal DAC, which measures distor- tion without including noise, ie, THD only, not THD+N. This type of filter gives a reasonably flat frequency response with a narrow range of load impedances. Since we don’t know exactly what impedance headphones will be used, we’ve designed the filter for a middle-of-the road value (around 16Ω). In practice, this gives a flat response with a wide range of headphone impedances (see Fig.8). For minimal distortion, the inductor in the output filter is an air-core type. To save space on the PCB and reduce cost, we have simply wound coils of enamelled copper wire around the two 10Ω resistors. These resistors don’t dissipate much but we have used 1W types so that they are large enough to wind the coils on. Without this, there could be a loud thump or crack if the unit is powered up or down with the headphones connected. This is mostly due to the various capacitors taking time to charge up to their normal operating voltages but also depends on which of the supply rails comes up first. By shorting the outputs to ground before switching on the ±15V rails and for a short time afterwards, this signal is shunted to ground and so very little of it passes through the headphones. But to minimise noise, we need the headphone amplifier output to be very close to ground when there is no input (ie, a very low offset voltage). Otherwise there will be a click when Q15/Q16 switch on and off. The offset is normally only a few millivolts but that can still be audible with a sensitive pair of headphones. So that is why we are using low-value input bias resistors for IC6. Note that while transistors Q15 & Q16 are on and various capacitors are charging, the amplifier will be trying De-thumping As with the line outputs, there is a pair of dual Mosfets connected so as to short the output to ground when there is no audio signal. In fact, these Mosfets gates are simply hooked up in parallel with those of Q1 and Q2 and operate simultaneously. siliconchip.com.au Headphone output Since the new DAC also has a headphone output, we have shown a plot of THD+N versus frequency for 10mW into a 32Ω load as well (red trace in Fig.6). This would be a loud listening level. Compared to the blue trace, the distortion is not much higher than that from the line outputs. On typical program material, the level won’t be fixed and most of the time the power level will be well below 10mW. And while most hifi headphones have an impedance of 32Ω or higher, some models have a lower impedance. Fig.7 shows how distortion varies with power at three common headphone impedances. In each case, THD+N rises as the power level drops below about 5mW as the residual noise begins to dominate the result. In fact though, the distortion continues to drop with reducing power and will actually be below .001% at 0.2mW rather than the .002% figure with noise included, as shown in Fig.7. At impedances below 32Ω, distortion is higher and power delivery is lower due to the increased current required to drive the load. Still, the results are quite reasonable at moderate power levels with a THD+N below 0.005% for impedances of 8Ω and above up to 15mW. The signal-to-noise ratio is better than 100dB for the headphone outputs driving a 32Ω load (relative to 50mW) and 110dB for the line outputs. And as you can see from Fig.8, the frequency response is very flat, down by just 0.1dB at 20kHz. If you want even lower distortion and more power, you could build the Hifi Stereo Headphone Amplifier (September-October 2011) and plug it into the line outputs of the DAC. very hard to pull the output away from ground but it won’t be able to. In this case, the short-circuit protection will be active until the circuit settles down. There will also likely be a fair bit of ripple on the ±15V rails during this time due to the relatively low current capability of the power supply (which we’ll explain later). Proper regulation has resumed by the time Q15 & Q16 turn off. Control circuit The micro has to set up the CS8416 digital audio receiver (IC1) and the CS4398 DAC (IC3) before they will operate correctly. It also communicates with them during operation, to determine the status (such as sampling rate) and change settings (eg, input switching). This is all done by microcontroller IC5, as shown in Fig.9. The SPI bus for IC1 & IC3 connects to its pins 3, 4, 5, 6 & 49 and thence to IC5’s internal SPI transceiver. Pins 48 & 50 control the reset lines for the two aforementioned March 2013  25 10 +5V +3.3V +3.3V 100 1 100nF IRD1 SPDIFCLK SPDIFO 3 1  CSDO 2 CSDI 2.2 Q11 BC327 CSCK PWRCTL 1k B 62 64 63 8 IRD E 6 5 4 36 37 19 AVdd 10 Vdd 26 Vdd 38 57 Vdd Vdd RG15 MCLR RG14 RG13 RB0 RG12 RB1 RG9 RB2 RG8 RB3 RG7 RB4 RG6 RB5 RG3 RB6 RG2 RB7 C RB8 1 F RB10 RB9 10k 220 F RB11 9 1 2 3 4 5 6 7 8 DATA IN 33 CLK 35 VDD 34 DATA OUT IC5 dsPIC33FJ128GP306 RF4 RF5 GND CON10 1 2 58 3 4 59 5 6 60 7 8 61 1 RB13 RB14 RB15 RD8 RF6 RD11 RF2 RC12 RC15 RF0 RD9 RF1 RD10 RG1 RC1 RG0 RC2 +5V 10k RB12 RC13 1k RC14 2 3 RD5 55 POWSW 4 RD4 RD7 RD3 1M RD2 1M RD1 ACIN SSPND 100k 54 RD0 RD6 Vcore/Vcap AVss 20 SC 2013 Vss 9 Vss 25 10k 1 2 3 4 5 7 ICSP CONN. CON11 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 RF3 S2 WP CON13 32 CS CD POWER SWITCH 31 CARD DETECT SD CARD SKT 4x 100nF 100nF 470 42 180 45 CON12 1 39 2 40 3 43 4 44 5 2 LEDS 4x GREEN (FRONT PANEL) DARGP0 3 DARCS 47 DARGP2 48 DACRST 53 DARGP1 52 AMUTEC 51 PHONES DET 50 DARRS 49 DACCS 46 CLKGENCS 56 Vss 41 10 F CLASSIC DAC CONTROL, FRONT PANEL & CLOCK GENERATOR SECTIONS Fig.9: the control circuit uses microcontroller IC5 to run the show. It is a 16-bit digital signal controller and can read WAV files up to 96kHz 24-bit from an SD card in socket CON10 and output an S/PDIF audio stream from pin 64 to IC1. LEDs1-8 show the state of the eight inputs (including the SD card) while LEDs9-12 indicate the sampling rate. Clock generator IC7 is used to provide the sampling clock when playing back WAV files. ICs while pins 2, 47 & 53 connect to the GPO pins on the digital audio receiver (IC1, Fig.4) for the functions explained previously. The micro also monitors the AmuteC output of the DAC at pin 52 so that it can determine when the output is silent. IC7 is a clock generator which pro26  Silicon Chip duces the sampling rate clock when playing back WAV files from the SD card. It shares the same SPI bus for control, with a third chip select line (CLKGENCS) driven from pin 46 of IC5. IC5 uses this bus to turn the clock output on and off and set its frequency. IC7 uses a 27MHz crystal and internal PLLs to generate the OMCK output for IC1. This clock is also fed to the pin 11 input of flipflop IC8b which acts as a clock divider. Each time CP2 goes high, the output at Q2 (pin 9) inverts because the inverting output Q2-bar (pin 8) is connected to the data input D2 (pin 12). The result is that the SPDIFCLK output from pin 9 is at half the rate of siliconchip.com.au  A LED5  K A LED6  K A LED7  K A LED8 +5V A LED9   K K A LED10  1 K A LED11 A LED12  K 2 FRONT PANEL LEDS  K  K K 3 4 5 CON14 POWER SWITCH WITH INTEGRAL LED A 10k 3.0k 22k 22k 100k 22k 100k 100k K A LED4 22k 100k  K 22k 100k  A LED3 470 100k A LED2 22k 1.5k A LED1  1 POWER SWITCH (FRONT PANEL) K 2 3 4 CON15 +3.3V 100 F 100nF 100nF 8 VCC 12 CSCK CSDO CLKGENCS 6 5 7 10 X2 27MHz 11 33pF 33pF 100nF 100nF 13 20 VDD2 VDD3 1 VDD1 MCKO1 CSEL MCKO2 MC MD SCKO3 IC7 PLL1708 MS SCKO2 SCKO1 XT1 SCKO0 100 F 100nF IC8: 74LV74 14 15 3 2 19 18 10 OMCK SD2 12 D2 4 14 Vdd 9 Q2 SD1 2 D1 SPDIFCLK CP2 RD2 Q2 3 8 CP1 RD1 1 13 Q1 Vss 7 6 XT2 AGND 9 DGND1 4 DGND2 16 DGND3 17 LEDS A OMCK and this goes to pin 62 of IC5 which is the Data Converter Interface (DCI) clock input. This controls the timing of the DCI serial output from pin 64 of IC5, which goes to input RXP7 on IC1 via a 10nF AC-coupling capacitor. When the micro wants to transmit audio to the DAC, it sets up IC7 to provide an appropriate clock and switches IC1 to input channel 7. It can then use a software routine to generate an S/PDIF stream which is output via the DCI peripheral to the receiver, to be decoded and sent on to the DAC. To do this, it must read the WAV data off the SD card and this is done with a second SPI interface. Pins 32 (card IRD1 BC327 B K siliconchip.com.au 5 IC8a IC8b 11 Q1 E C 1 2 3 select), 33 (data in), 34 (data out) & 35 (clock) simply connect directly to the SD card socket while pin 31 is used to sense whether a card is inserted, using a switch internal to the socket and a weak pull-up current internal to IC5. Power to the SD card socket is switched using PNP transistor Q11 which is controlled by pin 37. We March 2013  27 L5 47 H 0.5A REG4 AP5002 4 22 F 100k 2 25V X7R 100nF 50V X7R 3 100nF Vcc OUTPUT EN OUTPUT Comp 1k 100nF A 330pF 50V X7R K 1 FB Vss Vss 7 8 +3.9V 5 6 REG5 MIC39100-3.3 D6 1N5819 L6 470 H 0.5A LK2 +3.3VF OUT IN GND 4.7k +3.3V 470 F 10V 22 F 100 F 100 F 25V X7R 100nF 1.2k 220 F 25V K D7 1N4004 A D5 1N4004 A REG3 7805 K 220 F 25V D3 1N4004 470 F 16V A K D1 220 F 1N4004 35V S2 OUT IN GND 100nF 9VAC 16V CON9 A +15V K 100 F 100k D8 1N4004 G2 25V A K Q13a Si4804 K 220 F D2 1N4004 35V K 100 F 100nF GND A IN D4 1N4004 Q12a IRF7309 25V S1 OUT REG2 7915 100 F D2 A 470 F GND 100nF 100k D1 A D9 1N4004 PWRCTL D1 G1 S1 –15V 100k 100k E G1 B 1N5819 A BC559 K A SC 2013 CLASSIC DAC K E IRF7309 D2 D1 D1 B 1N4004 C +5V Q12b IRF7309 REG1 7815 K LK1 OUT IN D2 C 7805, 7815 7915 MIC39100-3.3BS GND G2 S2 G1 S1 IN GND OUT IN GND IN OUT Q14 BC559 GND IN GND OUT POWER SUPPLY SECTION Fig.10: power comes from a 9VAC plugpack. A charge pump voltage doubler feeds regulators REG1 & REG2 to provide ±15V rails to run the op amps and headphone amplifiers. These supplies are switched off using Q12 & Q13 when the unit is in standby (ie, when PWRCTL is low). Some components (eg, the DAC) require +5V and this is provided by a half-wave rectifier D5 and regulator REG3. The digital chips run from 3.3V and this is provided by switchmode stepdown regulator REG4 and linear post-regulator REG5. wait until the card is fully inserted to power it up and a 10Ω series resistor limits the in-rush current while a pair of capacitors provide a low-impedance supply for the card. A parallel resistor prevents these from charging via Q11’s leakage current when it is off. User interface The DAC’s state is displayed using 13 front-panel LEDs. Eight show the input status and they are connected to pins RB0-RB15 of IC5, each with two different value current-limiting 28  Silicon Chip resistors so that they can be driven at four brightness levels without the need for PWM. In practice, three levels are used: off (both outputs high impedance), dim (one output low) and bright (both outputs low). LED1 shows the status of input 1, etc. LEDs9-12 indicate the current sampling rate. A cable connects CON14 on the front panel to CON12 on the main board. These LEDs share a pair of current-limiting resistors at the common anode connection point as normally only one is lit at any time. Their brightness is based on whether audio is present (as opposed to merely a digital signal). The final LED is integral to the power button and this too is connected via a header and short cable, from CON13 on the main PCB to CON15 on the rear of the front panel. Its LED glows dimly in standby mode and brightly when the unit is powered on. But only one resistor is driven by the micro; the other is switched by part of DIP switch S2. Thus the LED can be switched off in standby if desired, using S2. siliconchip.com.au The unit is controlled by the aforementioned front panel power switch (via CON13/CON15) and also by infra­red remote control, using infrared receiver IRD1. As well as on/off control, the front panel pushbutton can be used to cycle through the input channels. Thus if you simply want to change inputs, you don’t have to go looking for the remote control. All other functions are performed using the remote. The Philips RC5 protocol is used as this is easy to decode and supported by virtually all universal remote controls. The output of IRD1 is a square wave and when its level changes, this triggers an interrupt handler routine in the software which then decodes the pulses. IRD1 runs off the 5V rail and it has an RC filter to ensure there is no noise on this line, as infrared receivers can be quite sensitive to noise. Microcontroller IC5 runs off the 3.3V rail and has a number of ceramic bypass capacitors, plus an RC filter for its analog supply. CON11 is an optional 5-pin in-circuit programming socket which allows IC5 to be re-flashed (IC5 is an SMD, so you would otherwise need a special socket to program it). S2’s remaining three switch banks are used to configure some of the basic functions of IC5, such as whether it will automatically scan for an active input. IC5 has no internal pull-ups to enable on the connected pins so at start-up it drives pins RF0, RF1 & RG1 high for a very brief period (less than 1μs) and senses the voltage on each. If the associated switch is on, the connected pin voltage will remain close to ground despite being driven “high”, as the output transistor’s internal impedance limits the current it can deliver. Because these “shorts” are so brief, they don’t risk damage to the output transistors. Pin 36 of IC5 (RG5) is the power control line which switches the ±15V rails on and off, both to conserve power during standby mode and to avoid thumps and clicks from the headphone output at power up/down, as explained earlier. It is active-high. Power supply Fig.10 shows the DAC’s power supply. It derives four regulated rails from a 9VAC plugpack and is designed to be efficient enough to not require any heatsinks. The 5V supply is the simplest. Disiliconchip.com.au ode D5 rectifies the incoming AC and charges a 220µF capacitor to 12-15V, depending on the exact plugpack voltage. This is then linearly regulated to 5V by REG3. The current drawn from the 5V rail is modest, so REG3 dissipates relatively little power. Much more current is drawn from the 3.3V rail; up to about 200mA, including 100mA for microcontroller IC5. As such, we’re using a switchmode regulator with a linear postregulator to keep the output clean. The AC is rectified by diode D7 and filtered with another 220µF capacitor, then REG4 (AP5002) steps the 12-15V down to 3.9V. It is a “buck” regulator so it does this by rapidly switching its output on and off, at 500kHz, and then filtering the resulting PWM waveform with an LC filter consisting of L5 and a 22µF SMD ceramic capacitor. This part of the circuit is very similar to that shown in the AP5002 data sheet. The 3.9V is then regulated to 3.3V using low-dropout linear regulator REG5. Another LC filter consisting of L6 (470µH) and a 100µF capacitor removes even more of the switching noise for the supply to the DAC as this is the part which is most sensitive to noise on the 3.3V rail. LK1 & LK2 are pairs of closelyspaced pads on the PCB which exist to allow constructors to check that the power supply is working before connecting it up to the rest of the circuit (ie, by soldering the pads together). Higher voltage rails The ±15V rails for the op amps and headphone amplifier are generated from the low-voltage AC supply using a charge pump. Consider the positive half of this pump. When the inner conductor of CON9 has a negative voltage relative to its barrel, current flows through diode D1 from ground and into the connected 470µF capacitor, charging it up to around 12V DC (ie, 9VAC x √2). When the AC voltage then goes positive, the positive side of this capacitor Pt.3 Next Month Next month, we will describe how to build the CLASSiC DAC and also explain how to test and configure it. If we have room, we’ll also give a brief explanation of how some of the more interesting features in the software operate. goes to nearly 24V (the AC peak plus the capacitor voltage) and thus diode D3 becomes forward-biased, charging the 220µF 35V capacitor to a similar level. This voltage then powers REG1, a +15V linear regulator, to provide a steady +15V rail for the op amps. The -15V part of the circuit is symmetrical and works in the same manner. Since input current for each of the ±15V supplies is drawn on both the positive and negative phases of the input AC waveform, the current drawn from the plugpack is roughly twice that drawn from the ±15V rails. Due to the impedance of the capacitors in this charge pump (ie, they partially discharge over the course of each AC cycle), current available on these rails is limited but is quite sufficient for our purposes. The +15V rail is switched by Q12b, half of a dual P/N-channel Mosfet. This is the P-channel device so it turns on when its gate is pulled low by Q13a, an N-channel Mosfet. When PWRCTL goes high, Q13a switches on and this in turn pulls Q12b’s gate to ground, enabling the +15V rail. At the same time, with PWRCTL high, Q14 turns on. This pulls up the gate of N-channel Mosfet Q12a, switching it on and enabling the -15V rail. A pair of 100kΩ resistors keeps both switches off if PWRCTL is high-impedance, which will be the case when power is first applied and any time that the micro is being reprogrammed. Finally, D8 makes sure that the +15V rail can’t be pulled negative when Q12b is off, while D9 ensures that the -15V rail can’t go positive when SC Q12a is off. Issues Getting Dog-Eared? Keep your copies of SILICON CHIP safe, secure & always available with these handy binders REAL VALUE AT $14.95 * PLUS P &P Order now from www.siliconchip.com.au/Shop/4 or call (02) 9939 3295 and quote your credit card number or mail the order form in this issue. *See website for overseas prices. March 2013  29