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A world first! Pt.1: By JIM ROWE A 2.5GHz 12-digit frequency counter with add-on GPS accuracy We are very proud of this high-resolution frequency counter which covers a range from below 10Hz to over 2.5GHz. It has an internal timebase (naturally) but also features an external timebase input which can accept 1Hz pulses from a GPS receiver, to achieve measurement accuracy approaching that of an atomic clock! And it doesn’t cost a mint to build! W E HAVE PUBLISHED a few digital frequency counters over the years, the most recent being two versions of a compact 50MHz counter in the October 2003 and February 2007 issues. But they are just toys compared to this new design which allows direct measurement of frequencies up to somewhere between 2.5GHz & 3GHz. This means it can be used to measure most of the frequencies used by WiFi, 24  Silicon Chip mobile phones and microwave ovens. And while high-quality commercial frequency counters often employ a temperature-compensated or ovencontrolled crystal timebase, these are not in the race when compared the very high accuracy 1Hz (1pps) signals available from many GPS receivers. In order to make these more accurate measurements meaningful, you need a high-resolution display, which is why this new design has no less than 12 digits. Oh, by the way, because it will measure period, it can give high-resolution readout of low frequencies as well. Naturally, it uses a microcontroller and this is used in a clever way, to simplify the counting circuitry while still using high-speed logic for dealing with the UHF range up to 2.5GHz and over. In spite of the high accuracy and siliconchip.com.au INPUT B INPUT AMPLIFIER INPUT A 12-DIGIT LED DISPLAY DIVIDE BY 1000 (PRESCALER) MAIN GATE COUNTER INPUT SELECT 1MHz (PERIOD MEAS.) COUNTER FOR FIRST FOUR DECADES COUNTER FOR LAST EIGHT DECADES BUFFER WAVEFORM SHAPER GATE CONTROL (PERIOD MEAS.) EXT TB IN TIMEBASE SELECT 1Hz CONTROL SIGNAL LATCH GATE CONTROL SELECT 1Hz TIMEBASE DIVIDER INTERNAL TIMEBASE SELECT DIVISION RATIO ÷1 ÷1 ÷10 ÷100 ÷1000 MODE DISPLAY LEDS PIC16F877A MICROCONTROLLER 8MHz 1MHz FREQUENCY DIVIDER (8:1) CONTROL SWITCHES Fig.1: block diagram of the 2.5GHz 12-Digit Frequency Counter. It uses a divide-by-1000 prescaler (to measure the higher frequencies) and a PIC16F877A microcontroller to process various signals and drive the display. Left: this printed photo of the completed prototype really doesn’t do the blue 7-segment LED displays justice – they really are nice and bright. The unit measures frequencies to over 2.5GHz and is also very easy to use. the case and supports the rest of the components and circuitry. The complete counter operates from a 9-12V DC plugpack, with a current drain of less than 650mA. Now let’s dive into the technology used in the new design. Block diagram resolution, this is not a difficult instrument to use. Below the 12-digit display is a row of pushbuttons, each of which has an associated LED to show when it has been pushed. The buttons are used to select one of the inputs, the mode (frequency or period), the timebase (internal or external) and the gating period (from one second to 1000 seconds). Finally, to the right of the digital display, there are three LEDs to indicate the frequency readout in Hertz or Megahertz, or Period in microseconds. We will explain all these features and how to use them later on in these articles. Overall though, it’s a doddle to use. The unit is housed in a standard plastic instrument case measuring 256 x 189 x 83mm. All components fit on two PCBs, linked by a short ribbon cable. The smaller PCB mounts behind the case front panel and supports the 12-digit display plus all of its management circuitry and components. The larger PCB sits inside the bottom of siliconchip.com.au Fig.1 shows the block diagram. It’s based on a PIC16F877A microcontroller, chosen because of its reasonably large number of I/O ports – five in all, including three 8-bit ports, one 6-bit port and one 3-bit. The PIC micro performs three important functions. The first is to control the overall operation, in response to the settings of the pushbutton switches on the front panel. The second is to manage the counter’s 12-digit display and its associated mode and range display LEDs. Finally, it also performs some of the actual counting. Counting of the first four “fast” decades is done outside the PIC but counting of the eight slower decades is done inside the PIC itself. In Fig.1, the PIC is shown on the right with the 12-digit main LED display above it, the mode display LEDs to its right and the control switches below it. Although only single arrows are shown linking the PIC micro to the main LED display and the mode display LEDs, all of these are controlled via a shared multiplexing system. To the lower left of the PIC is an 8-bit latch which is used to convey the various range and mode control signals to the counter’s input and timebase circuitry. Then at upper left of the PIC you can see the counter circuit for the first four decades, fed from the main gate and with its output passing into the PIC as input for the internal 8-decade counter. Moving right over to the left you can see the circuit blocks for the two main counter inputs, with channel A’s input in the centre and channel B’s input above it. Note that the channel B input block includes a 1000:1 prescaler, because this is the input channel for higher frequencies (100MHz - 2.5GHz). At lower left you’ll find the internal timebase block, the timebase selection block (internal/external timebase) and the programmable timebase divider. Ahead of the counter’s main gate (at upper centre in Fig.1) is a block labelled Counter Input Select, which is used to select which signal is fed to the counter gate: the input signal from channel A, that from channel B, or a 1MHz signal for period measurements. The 1MHz period measurement signal is actually derived from the PIC’s 8MHz clock, via an 8:1 frequency divider (shown at lower centre, below the control signal latch). The counter’s main gate is enaDecember 2012  25 Specifications A digital frequency and period counter capable of making frequency measurements up to at least 2.5GHz and time period measurements to 12 digits of resolution. All circuitry is on two PCBs, linked by a short 20-way IDC ribbon cable. The counter is housed in an instrument case measuring 256 x 189 x 83mm. Two Frequency Ranges: 10Hz – 100MHz (Channel A input); 100MHz – 2.5GHz or more (Channel B input; typically goes to 2.8GHz) Period Measurement Range: 1μs - 999,999 seconds (Channel A input); resolution 1μs Input Sensitivity: <20mV 0-20MHz; <75mV 20-100MHz; <250mV 100MHz+ Input Channel/Mode selection: eight pushbutton switches. Four Gating Periods for Frequency Measurement: 1s, 10s, 100s, 1000s Corresponding Resolution: 1Hz, 0.1Hz, 0.01Hz, 0.001Hz (Channel A); 1kHz, 100Hz, 10Hz, 1Hz (Channel B) Main Display: 12 x 14mm-high blue 7-segment LED displays Mode/Range Indicators: 11 x 3mm LEDs Internal Timebase: Based on a 32.768kHz crystal. Accuracy approx. ±1 x 10-5 External Timebase: Input for 1Hz pulses from GPS receiver, etc. Accuracy using GPS 1Hz pulses approx. ±1 x 10-11 Input Impedance: Channel A, 1MΩ//25pF; Channel B, 50Ω//3pF; External timebase, 23kΩ//8pF Power Source: External 9–12V DC supply bled by the PIC but counting does not actually start until the arrival of the next rising edge of the timebase gating control signal selected by the block below it. This will either be the internal or external timebase signal, divided down by the selected ratio in the case of frequency measurements or the signal from the channel A input in the case of period measurements. In response to the arrival of the first leading edge of the selected gating signal, the gate control circuit will enable the main gate to begin counting but on the arrival of the next leading edge the gate control circuit will close the gate again, to stop counting. The PIC monitors the gate control signal and when counting stops, it then proceeds to process the count (from both the four external decades and the eight internal decades) and pass it to the display. Circuit details Now let’s have a look at the full circuit. Because it is quite large, it is split into four sections: the input channels, shown in Fig.2; the timebase section (Fig.3); the main control and counting section (Fig.4) and the display multiplexing section (Fig.5). The upper section of Fig.2 shows the channel A input circuitry which handles signals in the range from be26  Silicon Chip    Current Drain: <650mA low 10Hz to above 100MHz. This is very similar to that used in our earlier counters, with an input buffer using a 2N5485 high-frequency JFET (Q3), feeding a 3-stage waveform shaper (squarer) using an MC10116P triple ECL (emitter-coupled logic) line driver device (IC5). The square-wave output from IC5a is then passed to a logic level shifter using transistors Q4 and Q5, to convert it into CMOS/TTL logic levels to feed the counter itself. The lower section of Fig.2 shows the channel B input circuitry which handles signals from 100MHz to 2.5GHz. This is very similar to that in the UHF Prescaler described in the October 2006 issue of SILICON CHIP. IC1 is an ERA-2SM+ broadband amplifier device which provides a gain of around +15dB with wideband frequency choke RFC3 (an ADCH-80A) as its output load. The amplified signals from IC1 are then fed to IC2, an MC12095 very high speed divide-by-four ECL device which forms the first stage of the channel B prescaling divider. IC2 feeds IC3, a programmable high-speed 8-bit ECL counter configured as a 125:1 divider. It then feeds IC4, an MC10EL32 highspeed ECL flipflop which performs the final division-by-two, to bring the overall frequency division to 1000 times. The outputs from IC4 are fed to a logic level shifter using Q1 and Q2, to convert them into a CMOS/TTL signal to feed the counter. Timebase circuitry Fig.3 shows the timebase circuitry. At upper left is the internal timebase generator which uses a 4060B oscillator/divider (IC6), together with a 32.768kHz crystal (X2) in the oscillator. It is followed by a 14-stage binary divider which delivers a 2Hz output signal from its O13 output (pin 3). This feeds IC7a, half of a 4518B dual 4-bit decade counter, where the 1Hz signal from the output of the first flipflop (pin 3) becomes our 1Hz internal timebase signal – fed to pin 1 of IC8a, one section of a 4093B quad Schmitt NAND gate. The external timebase signal (from a GPS receiver) arrives via CON3 and feeds IC8c, another section of the 4093B. IC8a and IC8c perform the internal/external timebase selection, under the control of a TB INT-bar/ EXT control signal from the PIC micro which arrives at lower right in Fig.3. This signal is inverted by IC8d to enable gate IC8a when the control signal is low but is also applied directly to pin 9 of IC8c, to enable this gate when the control signal is high. So a low control signal selects the internal 1Hz timebase signal, while a high level selects the external timebase signal from CON3. The outputs of IC8a and IC8c are fed to IC8b, used here as a low-input OR gate. The remaining section of Fig.3 shows the programmable timebase divider, which uses IC7b, IC9a and IC9b as three cascaded decade dividers and the four gates in IC10 (another 4093B quad Schmitt NAND) to select either the 1Hz signal from IC8b or the output of one of the three decade dividers – all under the control of the gating select signals which come from the PIC via control signal latch IC23 (see Fig.4). Only one of these signals is high (logic 1) at any time, so if the “Gating 1s” signal is high, gate IC10d is enabled to allow the 1Hz signal from IC8b to pass through to IC11b and then to the counter’s gate control circuitry. On the other hand, if the “Gating 10s” signal is high, IC10a is enabled to allow the 0.1Hz signal from IC7b to pass through to IC11b. And the other two gating select signals work in the same way, enabling either IC10c or IC10b. siliconchip.com.au A K A K 470nF D2 2012 BEVELLED END 2 4 IC1 3 1 4 2 3 DOT IC1 INPUT AMPLIFIER 1 6 8 CLK 6 1 3 6 10 F 7 6 AMPLIFIER 470 11 IC5b 1 8 14 16 20 Vcco Vcco Vcc Vcco Vbb 10 9 10nF 100nF IC5c 100nF DIVIDE BY 125 10nF A K ZD1 3.3V 430 A A ZD1 K K D3: 1N5711 100nF 14 15 75 4.7 F 51 IC4 CLK R 1 Vee 5 MC10EL32 Vbb CLK 8 Vcc G D 2N5485 +3V (VL) S 5 4 470 8 IC5a 180 3 2 6 7 E B C B 51 BC558 100nF 51 Q Q B Q4 BC558 8 C E 1 IC2, IC4 C E C E 4 470 B 11 5 1 IC3 26 18 19 25 TO IC13 PIN 9 +5V FROM Q7 TO IC13 PINS 5,12 +5V FROM Q6 MC10E016FNG 4 12 470 TP6 B Q5 BC558 82 Q1 BC558 120 C E 470 470 470 Q2 BC558 SCHMITT TRIGGER 100nF DIVIDE BY TWO 3 4 2 100nF 470 1k IC5: MC10116P 470 16 AMPLIFIER RFC2 47 H 470 12 13 28 +4V (VH) CLK TCLD 1 IC3 Vee 19 TC 26 MC10E016 MR 25 24 PE CE P0 P1 P2 P3 P4 P5 P6 P7 3 4 5 6 7 21 22 23 27 2x 100nF 100nF 10nF 1k 10nF RFC1 47 H 10nF VR1 1k OFFSET ADJUST INPUT CHANNELS 10nF DIVIDE BY FOUR GND 5 SW 1k 10nF 2 Vcc 4 OUT IC2 MC12095 RFC3: ADCH-80A 1nF 1nF 7 SB 1 CLK 100nF RFC3 HIGH RESOLUTION COUNTER NC K 100 10nF 100 3 47 10nF 100 F 100nF 470 S D INPUT BUFFER D4 1N5711 G D3 1N5711 Q3 2N5485 +5V Fig.2: the input channel circuitry. Channel A handles signals up to 100MHz and is based on 2N5485 JFET (Q3) and an MC10116P triple ECL line driver (IC5aIC5c). IC5c’s output is then fed to Q4 and Q5, to convert it into CMOS/TTL logic. The channel B input circuitry handles signals from 100MHz to 2.5GHz. IC1 is an ERA-2SM+ broadband amplifier and this feeds IC2, an MC12095 divide-by-four ECL device. IC2 in turn feeds IC3, a programmable 8-bit ECL counter configured as a 125:1 divider. This drives IC4, an MC10EL32 ECL flipflop which performs the final division-by-two, to bring the overall frequency division to 1000 times. The outputs from IC4 are then fed to Q1 and Q2, to again convert them to a CMOS/TTL signals suitable for feeding the counter circuitry. SC  A A K A K IC1: ERA-2SM+ 910k 100k 22pF D1 D1, D2: 1PS70SB82 CON2 CHANNEL B INPUT CON1 CHANNEL A INPUT 88t siliconchip.com.au December 2012  27 Accuracy and Resolution Accuracy and resolution are equally important when you are making any kind of physical measurement. There’s no point in having a measuring tool that’s extremely accurate if it doesn’t provide the resolution to allow reading its measurements with the same accuracy. That’s why vernier callipers and micrometers were developed, to provide much greater length reading resolution than precision-etched steel rules. Digital frequency counters are no exception. Since they operate by counting pulses at the input over a given period of time (the “gating” period), this means that their reading resolution is inversely proportional to the gating period. With the usual gating period of one second, the resolution is clearly 1Hz. The simplest way to achieve a higher resolution is to increase the gating period. For example a gating period of 10 seconds gives a resolution of 0.1Hz, while a gating period of 100 seconds gives a resolution of 0.01Hz and a gating period of 1000 seconds a resolution of 0.001Hz (1mHz). So extending the gating period improves the frequency resolution. But there’s no point in doing this unless the accuracy of the counter’s timebase is high enough to make the improved resolution meaningful. That’s why a typical frequency counter using a temperaturecompensated crystal oscillator as its internal timebase reference doesn’t attempt to provide a gating period of longer than 10 seconds, giving a resolution of 0.1Hz. Nowadays, there’s a relatively easy way to provide a counter with a timebase signal that’s much more accurate than a local crystal oscillator. Many GPS receivers provide a 1pps or 1Hz signal output that is accurate to within about 1 part in 1011, because each GPS satellite contains two atomic clocks which together provide a time accuracy of better than 1 part in 1012. If a counter uses the 1Hz pulses from a GPS receiver as its external timebase, it can therefore make meaningful frequency measurements with a gating period as long as 1000 seconds and a corresponding frequency resolution of 0.001Hz. That’s why our new counter provides a selection of four different gating periods (1s, 10s, 100s and 1000s) and an external timebase input intended to accept the 1Hz signals from a GPS receiver. It’s also why the counter is provided with a 12-digit display, to take advantage of the higher resolution and accuracy. The net result is that the circuitry in Fig.3 allows the PIC to select either the internal or external timebase signals and also whether the selected signal is divided by 1, 10, 100 or 1000. The selected timebase signal emerges from pin 13 of IC11b, to feed the counter gate control circuitry. Control & counting Fig.4 covers the main control and counting sections. The PIC micro is at upper right, shown as IC22. Don’t worry too much about the righthand side of IC22 at this stage, except to note that the outputs from port B of the PIC (RB0-RB7) are brought down to connect to control switches S2-S9 and the inputs of control signal latch IC23 (a 74HC373). The PIC scans the control switches to change the input channel, timebase mode and so on for the counter and stores the corresponding control signals in IC23. As you can see, the outputs of IC23 are labelled to indicate the various control signal functions. Just above the control switches is the PIC’s master clock circuit, based on an 8.0MHz crystal. This is entirely 28  Silicon Chip standard except for the addition of a 6-30pF trimcap (VC1) to allow the oscillator’s frequency to be adjusted as closely as possible to 8.00MHz. This is not for the PIC’s benefit but because we take the 8MHz clock signal from pin 14 of the PIC and feed it down to IC24, a 74HC161 binary counter which divides it by eight to derive the 1MHz clock signal used to make the counter’s period measurements. Note that pins 9 and 10 of IC22 (RE1 and RE2) are used to control Pchannel MOSFETs Q7 and Q6 over at far left. These transistors switch the +5V power to the input circuits for channels A and B (in Fig.2), allowing the PIC to turn off the power to the channel that is not currently in use. Below Q6 and Q7 in Fig.4 you’ll see the signals from the counter input channels (Fig.2) entering in the centre and feeding to selector gates IC13c, IC13b and IC13d. Then nearer the bottom, the timebase gating signal from IC11b (in Fig.3) enters and connects to input pins 3, 4 & 5 of IC11a. To put things into perspective, gates IC13b, IC13c and IC12a are used to select which signal is fed to the coun- ter’s main gate (via IC12b), while gates IC11a and IC13d below them are used to select which signal is fed to the main gate control flipflops IC17a and IC17b (via IC12c). In greater detail, in order to make frequency measurements, the PIC drops the FREQ-bar/PERIOD control signal line (from pin 12 of IC23) to logic 0, which disables gate IC12a but enables gate IC11a because of the logic 1 presented to pin 2 of IC11a from IC18d (used here as an inverter). So the timebase signal selected by the circuitry in Fig.3 is able to pass through IC12c and trigger the main gate control circuit around IC17. At the same time, the PIC raises either the SEL I/P CHAN A control signal from pin 9 of IC23 or the SEL I/P CHAN B control from pin 15 of IC23, to enable either gate IC13b or IC13c. This allows one of the two input channel signals to pass through IC12b to the counter’s main gate. But where exactly is the counter’s main gate? It’s actually inside IC14, a very fast 74AC163 programmable synchronous 4-bit counter which we’re using here as a decade counter – the very first decade of our 12-decade counter. The counter input signal is fed into the CP input of IC14 (pin 2), while the main gate control signal from pin 5 of IC17 is fed to the CEP and CET inputs (pins 7 and 10). So IC14 can only begin counting the input signal when IC17 “opens the gate” by raising the CEP/CET inputs to a logic high. IC14 is made to act as a decade counter by feedback applied via gate IC15a. The inputs of IC15a are connected to the ‘1’ and ‘8’ outputs of IC14, so that as soon as the count of IC14 reaches ‘9’, the output of IC15a drops and pulls the synchronous reset pin (SR-bar, pin 1) of IC14 to logic 0. As a result, the very next pulse edge reaching the CP input of IC14 causes it to reset to ‘0’ instead of incrementing to ‘10’. Just before we continue to follow the signal path through the counter, let’s explain how the gate control circuitry around IC17 works. Two very fast flipflops inside IC17 are interconnected in a kind of master/slave arrangement called a “synchroniser”. The simplest way to understand it is to follow through one operating cycle, as follows: Before counting begins, the PIC resets both IC17a and IC17b at the same siliconchip.com.au siliconchip.com.au December 2012  29 2012 22k A K D5 D6 MR RS Rtc Ctc 13 15 1 2 3 13 12 9 8 8 Vss 6 7 IC8d IC8c 11 10 7 5 4 100nF O3 O4 O5 O6 O8 IC6 4060B O7 14 O9 O11 O12 O13 2 1 IC8a 14 1 2 7 3 HIGH RESOLUTION COUNTER 1k A K 12 11 10 9 16 Vdd O3 5 6 3 4 1Hz INT O0 TPG TP5 IC8b 8 Vss O2 IC7a 4518B O1 4 16 VDD 9 10 15 13 12 CP0 O2 O3 7 IC10d 11 O0 11 13 14 4518B O1 12 CP1 IC7b MR TIMEBASE CIRCUITRY 6 5 CP0 CP1 MR 100nF 1 2 7 1 2 O3 5 6 3 O0 3 IC9a O2 4518B O1 4 16 VDD IC10a CP0 CP1 MR 100nF 9 8 10 CP0 O2 O3 Vss 8 O0 11 13 14 4518B O1 12 CP1 IC9b MR IC10c 9 10 15 IC10b 14 11 9 4 12 10 100nF A K D5, D6: 1N4148 5 6 IC8, IC10: 4093B IC11: 4012B 13 TO IC11a PINS 3,4,5 TB INT/EXT GATING 1s GATING 10s GATING 100s TIMEBASE GATING SELECT (FROM IC23) GATING 1000s IC11b 14 100nF Fig.3: the timebase generator uses a 4060B (IC6) and a 32.768kHz crystal (X2) in the oscillator. IC6’s internal 14-stage binary divider delivers a 2Hz output signal from its O13 output and this feeds IC7a, half of a 4518B dual 4-bit decade counter, The resulting 1Hz signal from pin 3 is then fed to pin 1 of Schmitt NAND gate IC8a. IC7b, IC9a & IC9b operate as cascaded decade dividers, while NAND gates IC10a-IC10d are used to select either the 1Hz signal from IC8b or the output of one of the three decade dividers. The gating select signals come from the PIC via control signal latch IC23 (see Fig.4). SC  CON3 1Hz INPUT FROM GPS 39pF VC2 6-30pF X2 10M 32.768kHz 220k TP1 100nF +5V 9–12V DC INPUT + – POWER D7 1N5819 REG1 7805 K A S1 CON4 2200 F 25V +5V OUT IN GND +5V 47 F 100nF 100k 100k 27 27 +5V S Q6 NX2301P S G D +5V FOR INPUT CHANNEL A 100nF G Q7 NX2301P +5V D TPG TP3 IC15c 14 9 TP4 10 TPG 1 8 IC13a 3 2 7 +5V FOR INPUT CHANNEL B IC12: 74AC10 IC13, IC15: 74AC00 IC18: 74HC00 SEL I/P CHAN A 18 16 14 12 3 5 7 9 100nF O0 O1 O2 O3 O4 O5 O6 O7 20 Vcc 19 OE2 IC19 1 74HC244 OE1 10 GND D0 D1 D2 D3 D4 D5 D6 D7 2 4 6 8 17 15 13 11 SEL I/P CHAN B +5V 100nF CH A INPUT FROM Q5 4 9 14 8 100nF IC13c IC13b 9 6 7 5 1MHz 13 IC12a 12 2 10 14 4 5 3 2 6 PE CEP CET CP IC12b 1 IC14 74AC163 TC Vss 8 P0 P1 P2 P3 3 4 5 6 1 2 16 14 13 12 11 Q0 Q1 Q2 Q3 Vdd SR 15 4 5 IC15b 10 IC15a CH B INPUT FROM Q1 100nF 9 7 6 3 10 2 1 16 14 13 12 11 Q0 Q1 Q2 Q3 Vdd PE CEP IC16 74HC160 CET CP 1 MR TC Vss 8 P0 P1 P2 P3 3 4 5 6 100nF FREQ/PERIOD 6 12 13 12 IC13d 13 11 14 100nF IC18c 4 2 TIMEBASE GATING SIGNAL FROM IC11b 2 3 4 5 IC11a 1 9 10 11 IC12c 8 7 3 7 SD1 D1 10 Q1 IC17a 74AC74 CP1 RD1 1 Q1 Vss 7 5 6 12 11 SD2 D2 CP2 RD2 13 +5V 1MHz 11 12 13 14 Q3 Q2 Q1 Q0 8 15 1 2 TP2 SENSE MAIN GATE STATUS 10 Vdd 9 Q2 Q2 RESET DECADES 1&2 SET MAIN GATE CONTROL FF 14 IC17b 74AC74 4 5 9 8 11 7 IC18b +5V IC18d 15 TC IC24 74HC161 IC18a 3 7 P3 P2 P1 P0 6 5 4 3 16 Vdd PE MR CEP CET Vss 8 CP 9 1 7 10 2 100nF 1MHz SC 2012 HIGH RESOLUTION COUNTER CONTROL & COUNTING CIRCUIT Fig.4: the PIC micro (IC22) forms the heart of the main control and counting circuit. As shown, its port B outputs (RB0-RB7) connect to control switches S2-S9 and to the inputs of control signal latch IC23 (74HC373). In operation, the PIC scans the control switches to change the input channel, timebase mode and so on for the counter and stores the corresponding control signals in IC23. In addition, the PIC processes the Channel A & Channel B input signals and the timebase signals (after processing via various logic gates, flipflops and counters) and drives the display board via CON5. 30  Silicon Chip siliconchip.com.au +5V CON5 +5V 100nF 4 16 100nF 2.2k 18 +5V 6 100nF 9 30 29 28 27 22 21 20 19 READ DECADES 1&2 18 16 14 12 3 5 7 9 O0 O1 O2 O3 O4 O5 O6 O7 20 Vcc 19 OE2 IC21 1 74HC244 OE1 10 GND D0 D1 D2 D3 D4 D5 D6 D7 2 4 6 8 17 15 13 11 100nF RESET DECADES 1&2 24 RESET DECADES 3&4 8 READ DECADES 1&2 17 READ DECADES 3&4 16 SET MAIN GATE CONTROL FF 23 ENABLE CONTROL SIGNAL LATCH 26 SENSE MAIN GATE STATUS 18 SENSE SWITCHES 25 3 4 5 6 7 O0 O1 O2 O3 MR 2 CP1 IC20a 4518B 1 CP0 11 12 13 14 15 O0 O1 O2 O3 16 MR Vdd 10 IC20b CP1 4518B 8 9 Vss CP0 12 13 100nF IC15d 11 14 13 18pF 22pF +5V TB INT/EXT GATING 100s GATING 1s GATING 10s SEL I/P CHAN B GATING 1000s 8MHz SEL I/P CHAN A FREQ/PERIOD 19 2 5 16 O7 20 Vcc O0 D7 D0 O1 D1 O6 D6 S2 S3 S4 MCLR S5 3 RD7 RD6 RB7 RD5 RB6 40 4 39 5 6 RD4 LK2 RD3 RD2 RD1 RD0 RA5 LK1 9 7 17 6 7 RA4 IC22 5 PIC16F877A RA3 RC5 RA2 RE0 RA1 RC2 RA0 5 4 3 3 1 2 2 RC1 15 RC4 13 RC7 RC3 RB5 RC6 RB4 RB3 TMR1/RC0 RB2 RB1 RB0 OSC2 OSC1 VC1 6-30pF S6 1 2 RE1 TMR1 COUNTER IN X1 8.0MHz 100nF 15 RE2 1 TO DISPLAY BOARD +5V K Vdd ICSP CONNECTOR 10 8 D8 32 11 Vdd A S7 Vss 12 38 10 37 12 36 14 35 20 34 19 33 11 Vss 31 S9 S8 10k 18 3 4 17 14 O5 IC23 D5 74HC373 6 7 15 9 12 11 O2 D2 O3 D3 D4 O4 LE GND 10 OE 8 13 1 NOTE: LK1 AND LK2 ARE REMOVED FOR PIC PROGRAMMING, BUT MUST BE FITTED FOR CORRECT COUNTER OPERATION 7805 NX2301P D8: 1N5711 A siliconchip.com.au K D7: 1N5819 A K D G S GND IN GND OUT December 2012  31 21 3 2 3 1 2 FROM MAIN BOARD K  G K  A S D K  A Q27 G A 15 15x27 16 1 13 14 19 20 17 O9 18 O8 IC26 O7 4 4514B 5 O6 6 O5 7 O4 8 O3 10 O2 9 O1 11 O0 GND 12 24 Vcc O15 O14 O13 O12 O11 O10 OE1 (Q26) (Q25) (Q23) (Q24) (Q28) (Q30) Q29 D S K  A K  A G K A S D K 12 Q21  Q19 DRAIN d g a dp c e b f 9 K   K A dp c e b f A Q18 DRAIN d g a 8 G K c e b f S D dp  A Q17 DRAIN d g a DISP3 7FB5641AB (Q16–Q19 OMITTED FOR CLARITY)  A 5 SEGf 10 SEGe 1 SEGd 2 f SEGc 4 SEGb 7 e SEGa 11 SEGdp 3 GATES OF Q23–Q30 8x47 SEGg 6 Q20 K  A Q16 DRAIN d g a DISPLAY BOARD SCHEMATIC NOTE: Q26 IS DRIVER FOR SEGMENT g, Q25 IS DRIVER FOR SEGMENT e, Q23 IS DRIVER FOR SEGMENT a, Q24 IS DRIVER FOR SEGMENT c, Q28 IS DRIVER FOR SEGMENT f, Q30 IS DRIVER FOR SEGMENT b Q19 GATE Q18 GATE Q17 GATE Q16 GATE Q22 (Q26) D 8x10k dp c b G e f S D G d S D 9 g a G d 8 S D g a G Q13 dp c e b f d S D 6 g a G S G Q12 dp c b Q8–Q22: 2N7002 Q23–Q30: NX2301P D Q14 dp c e b f DISP2 7FB5641AB Q15 dp c e b f LEDS 12 K A d g a 100 F 16V e f S D 12 G 6 Q11 dp c e b f 7 d S D 9 g a 1 12 G Q10 dp c e b f (BOTTOM OF DISPLAY) d g a d 8 S D g a G Q9 dp c e b f DISP1 7FB5641AB d S D 6 g a Fig.5: the displays are all driven in multiplexed fashion. As shown, the common cathodes of the three 4-digit blue LED displays, DISP1-DISP3, are switched by 2N7002 N-channel Mosfets (Q8-Q19). These Mosfets are controlled by the PIC’s RA port pins via CON5 and CON6 and then via IC26, a 4514B 4-bit to 16-bit decoder. The matching display segments are connected in parallel and are controlled from the PIC’s RB port pins via IC25 (a 74HC240 octal buffer and line driver) and eight NX2301P P-channel MOSFETs (Q23-Q30). The mode and range indicator LEDs are multiplexed in similar fashion. 2012 SC  CON6 D0 D1 D2 D3 E LE +5V GND 10 19 18 8x27 S HIGH RESOLUTION COUNTER 22 5 8 23 1 7 100nF 4 17 9 6 O0 D0 OE2 O1 D1 16 O2 D2 2 O4 D4 3 5 4 8 14 O5 D5 11 17 12 7 LED3 9 19 15 10 O6 O7 D6 20 Vcc 20 13 13 D7 IC25 O3 12 D3 74HC240 6 14 11 SEGc 220 15 SEGa G SEGg 100nF SEGf +5V SEGb 220 SEGe 220 LED1 LED4 SEGdp 220 16 LED7 LED8 18 LED11 32  Silicon Chip siliconchip.com.au Q8 dp c b The display PCB carries the three 4-digit 7-segment LED readouts plus the various mode and indicator LEDs. The full assembly details are in Pt.2 next month. time as it resets the first two decades of the main counter (IC14 and IC16). So to begin with, both IC17a and IC17b are in the reset state with pins 6 and 8 both at logic 1 (high). As a result, pins 5 and 9 are both low, with pin 5 holding the main gate inside IC14 closed and pin 9 holding the D input of IC17a at logic 0 so that IC17a cannot switch to its set state in response to the leading edge of any timebase pulse arriving at the CP1 input (pin 3) from IC12c. To initiate a counting sequence, the PIC provides a positive-going pulse at its RC4 output (pin 23) – which is labelled SET MAIN GATE CONTROL FF. This logic high is applied to both inputs of IC18c, which is used as an inverter. As a result, a negative-going pulse is applied to the SD2-bar input of IC17b (pin 10), immediately switching IC17b into its set state with pin 9 high and pin 8 low. And since the D1 input of IC17a (pin 2) is tied to pin 9, this effectively “primes” the main gate control flipflop IC17a. The leading edge of the next timebase pulse to arrive at the CP1 input (pin 3) of IC17a will immediately trigger this flipflop into its set state. This in turn drives pin 5 high and opens the main counter gate in IC14 to begin counting. At the same time, when the Q1 output of IC17a switches high, it also applies a clock edge to the CP2 input of IC17b (pin 11) and since the D2 input of IC17b is tied to logic 0 (ground), this causes IC17b to switch back to its reset state with pin 9 low and pin 8 high. This causes the D1 input of IC17a (pin 2) to be pulled low as well, preparing IC17a for the final part of the cycle. Counting then continues, but only until the next timebase pulse leading edge arrives at pin 3 of IC17a. As soon siliconchip.com.au as this happens IC17a switches back to its reset state, with Q1 (pin 5) falling back to logic 0 and closing the main gate inside IC14. So the result of this timing control cycle is that the counter’s main gate is opened for exactly one timebase period and then closed again. And although the PIC kicks off the cycle by sending out the SET MAIN GATE CONTROL FF pulse, the actual gate timing is determined by the timebase signal applied to pin 3 of IC17a. By the way, the PIC is able to determine when counting stops by monitoring the output of gate IC18a, which has its inputs connected to the Q-bar outputs of IC17a and IC17b (pins 6 & 8). The output of IC18a only switches low when both Q-bar outputs are high, which only happens at the end of a control cycle when counting stops. The output of IC18a is connected to the PIC’s RC3 input (pin 18, with the label SENSE MAIN GATE STATUS). This allows the PIC to sense when counting stops. As already noted, IC14 contains not only the counter’s main gate but also the first decade of the counter itself. And the next decade of counting is performed by IC16, a 74HC160 synchronous decade counter. The CP input of IC16 (pin 2) is connected to the output of IC15b (pin 6), while both inputs of IC15b (used here as a fast inverter) are connected to the ‘8’ output (pin 11) of IC14. As a result, a positive-going clock edge is fed to the CP input of IC16 when IC14’s count falls to zero, causing IC16 to increment every time IC14 has counted 10 input pulses. The third and fourth counting decades are based around IC20a and IC20b, two halves of another 4518B dual-decade counter. As you can see, the Q3 or ‘8’ output of IC16 (pin 11) is connected directly to the CP1-bar input of IC20a (pin 2), so that IC20a increments each time the count of IC16 returns to zero. Similarly, the Q3 output of IC20a is connected directly to the CP1-bar input of IC20b (pin 10), so IC20b increments each time the count of IC20a returns to zero. To recap, only the first four “high speed” decades of the counter are implemented in hardware external to the PIC, ie, IC14, IC16 and the two halves of IC20. The rest of the counting is done inside the PIC itself, mainly by its internal timer/counter module TMR1. This is a 16-bit timer/counter, with its input brought out to the PIC’s TMR1/RCO pin (pin 15). Since TMR1 increments on the positive-going edge of the signal fed to pin 15, we need to invert the “carry over” from pin 14 of IC20b to achieve correct counting. This is done by gate IC15d which is connected as an inverter. But how can we can use the PIC’s TMR1 counter module to count the remaining eight decades, when as a 16-bit counter it can clearly only count to 65536 – fewer than five decades? Well, we can do so because inside the PIC we can arrange for the overflow of TMR1 (when it rolls over from 65535 to zero) to trigger an interrupt and then use a small interrupt servicing routine to increment a further 8-bit counter register every time this happens. Doing this effectively converts the counter inside the PIC into a 24-bit counter, able to count up to 16,777,215. Power supply & ICSP Just before we leave Fig.4, two sections not yet mentioned are the power supply circuitry and the ICSP (in circuit serial programming) interface. The power supply is simple, with December 2012  33 This is the view inside the completed frequency counter, from the rear. All the parts fit on two PCBs which are linked together by a short ribbon cable. Power comes from a 9-12V DC plugpack supply. reverse polarity protection diode D7 in series with the front-panel power switch S1 and then a standard 7805 regulator (REG1) to provide a stabilised and filtered 5V supply for all of the counter circuitry. The ICSP circuitry (upper right) enables the PIC to be programmed or reprogrammed with the counter firmware at any time. All the connections needed for programming are brought out to the usual 6-pin ICSP connector, while the PIC’s RB7 and RB6 pins are isolated from the rest of the counter circuit during programming by removing links LK1 and LK2. After programming is completed, these two links are then refitted so that the counter can use RB7 and RB6 in the normal way. Finally, note that all the connections from the PIC’s RA and RB I/O ports are brought out to 20-way DIL connector CON5, shown at far right in Fig.4. This allows the display PCB, shown in Fig.5, to be connected via a ribbon cable fitted with IDC headers. Multiplexed display All the displays are driven in 34  Silicon Chip multiplexed fashion – not just the 12 numeric digit displays but the 11 indicator LEDs as well. The numeric displays consists of three 4-digit 7-segment blue LED displays, DISP1-DISP3, which have their common cathodes controlled by 2N7002 N-channel Mosfets Q8-Q19. Note that only Q8-Q15 are shown while Q16-Q19 are “implied”, with dotted lines. This is to save space on the diagram. These Mosfets are controlled by the PIC’s RA port pins via CON5 and CON6 (linked by the ribbon cable) and then through IC26 – a 4514B 4-bit to 16-bit decoder. This circuitry thus forms the “digit drive” section of the display multiplexing system. All matching segments of the display digits are connected in parallel and driven by NX2301P P-channel MOSFETs, Q23-Q30. Again, most of these connects are shown dotted, to save space on the diagram. These P-channel Mosfets are controlled by the eight outputs from IC25, a 74HC240 octal buffer and line driver. This is controlled in turn by the PIC’s RB port pins, again via CON5 and CON6. So the circuitry at upper left in Fig.5 forms the “segment drive” part of the display multiplexing. As you can see, the 11 indicator LEDs (LED1-LED11) are part of the same multiplexing system, split into three groups forming three “pseudo display digits”. The three groups are controlled by Mosfets Q20-Q22, controlled in turn by outputs O12, O13 and O14 of IC26. The anodes of the LEDs are connected to the display segment driver lines from Q23-Q30, so they can be controlled by the PIC as part of the multiplexing. For example, LED1 is addressed as segment b of “digit” 15, while LED7 and LED11 are addressed as the DP (decimal point) segments of “digits” 14 and 13 respectively. As far as the PIC’s firmware is concerned, the indicator LEDs are simply specific segments of the three additional pseudo display digits. That’s all we have space for in this first article on our new high-resolution counter. Next month, we will present the construction details for both the main PCB and the display PCB and give the set-up procedure, which is SC simple and straightforward. siliconchip.com.au