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SPORT S ync Audio Delay Module By NICHOLAS VINEN Many sports fans feel that radio commentary is better than that on TV, particularly commercial TV. To eliminate the annoyance of the TV commentary (and the adverts) they want to turn down the sound on the TV and listen to the radio instead. But the delay in the live TV broadcast causes a major problem. This simple project lets you delay the commentary on the radio to match the action on your TV – and it’s remote controlled. L OTS OF READERS have asked us for this project. They hate the commentary on TV sports broadcasts and the same comment goes for the adverts. But if they listen to radio commentary instead, they hear the score change before they see it on the screen. Our Sports Sync project fixes that. It lets you to delay the radio from 0.2 seconds up to 30 seconds or more, in small increments. So it’s perfect for matching up the sound and the picture. A universal remote control is used to operate the device and the controls the Delay, Volume & Mute functions. The rear panel of the device also carries an Output Volume control, along 26  Silicon Chip with an Input Gain Control and RCA input and output sockets. Three LEDs on the front panel indicate the device status: Power, Activity and Clipping. Design The obvious way to provide an audio delay is to convert the sound from the radio to a digital stream, store it in a memory buffer and then convert it back to analog audio later, ie, build a digital audio delay. By controlling how much of the memory buffer is used, we control the length of the delay. The required memory buffer is quite large – larger than the amount of internal RAM (random access memory) available in any microcontroller. Even the new PIC32 series micros have an upper limit of 128KB of RAM which at a measly sampling rate of 16kHz and a low 8-bit voltage resolution is only enough to buffer about eight seconds worth of audio. We want a longer maximum delay and better audio quality. So we need an external RAM chip for the microcontroller. We considered the idea of adapting the SD Card Music & Speech Recorder/ Player (SILICON CHIP, August 2009) for this purpose but it uses flash memory for storage and that is not suitable for this task. For this application, the memory is constantly being written but flash wears out after a fixed numsiliconchip.com.au Audio delay lets you synchronise radio sports commentary with broadcast TV for the best of both worlds ber of write cycles. In some cases the number of write cycles can be quite low so it is really only suitable for data storage. RAM, on the other hand, can be written as much as necessary without any risk of failure. The basic design is shown in the block diagram of Fig.1. The radio is connected to CON2 and its audio output is amplified and biased to suit the requirements of the analog-to-digital converter (ADC) in microcontroller IC1. The sound is then digitised and stored in a 512KB static RAM (SRAM) chip (IC2). It is later retrieved and played back, then passed through some filtering and a volume control before being sent to output connector CON3. The incoming audio is also applied to a clip detector circuit consisting of a window comparator, pulse stretcher and clip LED. This indicates whether the audio gain is too high for the ADC so that the gain can be set to the optimal level. The circuit also incorporates an siliconchip.com.au Features & Specifications Channels ....................................................................................................1 (mono) Delay ....................................................... 0.2-34s with increments starting at 50ms Sample Rate ......................................................................... 10-40kHz (see Table 1) Voltage Resolution .........................................................................................12 bits Input Sensitivity ................................................................................... 200mV RMS Signal-to-Noise Ratio ..........................................................................around -70dB Controls ......................................... delay and volume adjustment (infrared remote) Power Supply ..................................................................................... 9V DC 150mA infrared receiver (IRD1) which is connected to the microcontroller, so it can pick up remote control signals, providing delay and volume adjustment. An 8MHz crystal oscillator ensures that the delay and sampling rate are accurate and stable. Two additional LEDs (LED2 and LED3) provide feedback on the audio buffering state and infrared activity. The two serial-to-parallel latch ICs (IC3 and IC4) assist the microcontroller in addressing its external RAM. Their role will be explained in more detail later. Software The software which runs on the microcontroller has two main tasks: (1) record, buffer and play back the audio and (2) receive, decode and act on infrared control signals. The majority of the code is for the audio buffering scheme and Fig.2 shows how this works. The audio signal applied to input May 2011  27 16-BIT SERIAL-TOPARALLEL ADDRESS LATCH (IC3, IC4) INFRARED REMOTE CONTROL INPUT (IRD1) DC BIAS (4.5V) AUDIO INPUT (CON2) CLIP LED (LED1)  ADDRESS DATA 512K x 8-BIT STATIC RAM (IC2) ADC INPUT PULSE STRETCHER (Q1,D2) WINDOW COMPARATOR (0.14V–3.16V, IC7a & b) MICROCONTROLLER (IC1) ACTIVITY LED (LED2)  POWER LED (LED3) LED DRIVERS (IC7c, IC7d) AUDIO DATA DC BIAS (1.65V) GAIN (0–6) & LOW PASS FILTERING (IC6b, IC6a)  DAC DIFFERENTIAL AMP & LP FILTER (IC6c) OUTPUTS VOLUME CONTROL & BUFFER (IC6d) AUDIO OUTPUT (CON3) 8MHz CRYSTAL OSCILLATOR (IC5) Fig.1: block diagram for the SportSync audio delay project. The incoming audio signal is amplified and filtered, then digitised in microcontroller IC1 and stored in SRAM (IC2). It is subsequently retrieved from the SRAM by IC1, converted back to analog audio and filtered and buffered before being sent to the output. A clip detector aids in setting the gain while two additional LEDs provide feedback. A universal remote control is used to operate the unit. AN0 is continuously digitised and fed alternately into two 240 sample (480 byte) direct memory access (DMA) buffers. As each buffer becomes full, an interrupt is triggered and the handler subroutine moves its contents into the local circular recording buffer, which has space for twelve sets of 240 samples (12 x 480 bytes). The local buffer blocks are 480 bytes each despite the 12 bit sample resolution. This is because the ADC stores each sample as 16 bits since that is the register size of this processor. It is called a circular buffer because after data is stored in the final block, the next storage location is the first block again. This allows up to twelve buffers worth of data to be kept in the order that they are recorded without the need to move any of the blocks around in memory. Instead, we simply keep track of the first and last block to contain valid audio data. As shown in the diagram, the local recording buffer typically contains only a couple of blocks worth of data. In reality though, it is larger than that to allow for any delays in being emptied (eg, due to infrared command handling), so that it won’t overflow and lose data. It is emptied as quickly as possible into the main circular buffer, in the external SRAM chip. This can hold up to 1456 blocks of 240 samples. When the data is moved to the external SRAM chip, it is re-arranged so that each pair of 12-bit samples is stored in three bytes rather than four 28  Silicon Chip (2 x 12 bits = 3 x 8 bits). Thus each 240 sample buffer takes up 360 bytes of SRAM. 1456 x 360 bytes = 511.875KB, so this just fits in the 512KB chip. Once a block of recorded data has been stored to SRAM, another block is read back from a different location and fed into the local playback buffer. Like the local recording buffer, it also has space for twelve blocks of 240 samples but it is kept as full as possible. This is so that during a brief delay (eg, processing an infrared command), it will not empty. The samples are converted back into the 16-bit format as they are transferred from SRAM into the local playback buffer. During this process, the digital volume control also takes effect. If the volume setting is below maximum, the sample values are re-scaled to a lower value, reducing the resulting audio amplitude. data does not spend long in the buffer before it is read back and so the delay is short. As the gap between the two locations widens, the delay increases. Digital-to-analog converter The length of the delay also depends upon the sampling rate used (this is analogous to tape speed). The lower the sampling rate, the slower blocks are recorded and played back. So with a fixed number of blocks, at lower sampling rates the delays are longer. However, lowering the sampling rate also reduces the audio quality (just as lower tape speed reduces the high frequency response and audio quality). So for short delays we want to keep the sampling rate as high as possible. Ideally, the sampling rate is reduced only when a longer delay is required As with the ADC, the digital-toanalog converter (DAC) also has two 240-sample DMA buffers which it plays from alternately. As each buffer becomes empty, the DMA interrupt handler re-fills it from the local playback buffer. The delay period is adjusted by controlling the difference between the location where data is fed into the circular storage buffer in external SRAM and the location where data is read back. If the playback location is not far behind the record location, the Tape loop analogy Just to make the workings of the circular buffer a little clearer, the circular buffer can be regarded as being similar to the analog delay systems which used an endless loop of tape with a recording head and replay head. In that case, the audio delay was set by the length of the tape loop, the tape speed and the space between the recording (input) and replay (output) heads. In the digital system, we feed the signal into the circular buffer (which does not “move”) and the microcontroller sets the delay by altering the space between the moving input address and the moving output address. Sampling rate siliconchip.com.au #1448 #1449 #1447 #1445 #1446 #1443 #1444 #1441 #1442 CIRCULAR STORAGE BUFFER (1456 x 240 samples) #1440 #4 #3 #1 #2 #1455 # 1456 #1453 #1454 #1451 #1452 #1450 External SRAM sample blocks are 240 x 12 bits = 360 bytes each, 524,160 bytes total. Delay Adjustment IC2 (SRAM) 8-BIT DATA BUS, 19-BIT ADDRESS BUS CIRCULAR RECORDING BUFFER (240 x 12-bit samples) AN0 IN ADC OUT 2 x DMA BUFFERS – – – – – #2 #1 – – – – – #7 #8 CIRCULAR PLAYBACK BUFFER (240 x 12-bit samples) #9 #10 #11 #12 #1 #2 2 x DMA BUFFERS #3 #4 #5 #6 IN DAC OUT DAC1LP/ DAC1LN Local RAM sample blocks are 240 x 16 bits = 480 bytes each, 11,520 bytes total. IC1 (dsPIC MICRO) Fig.2: the audio buffering scheme. Digitised data is stored in a 12-entry local recording buffer and then transferred to the 1456-entry circular storage buffer within IC2. Later, data is copied back into the local playback buffer before being sent to the DAC. than would otherwise be possible. Initially, the sampling rate is set to 39.06kHz (40MHz ÷ 1024). This has a Nyquist frequency of 19.53kHz which is adequate for reproducing all audible frequencies of interest. In this condition, 240-sample blocks are consumed at the rate of 163 per second and so the maximum delay is around 1456 ÷ 163 + 0.1 = 9.03 seconds. To keep the interface simple, we automatically lower the sampling rate if the delay is increased beyond eight seconds. When this transition occurs, the recording and playback rates are no longer equal so the gap between the recording and playback locations slowly grows and at the same time, the maximum possible delay increases. During this process, the green LED flashes. The sampling rate is initially reduced to 26.04kHz (40MHz ÷ 1536), which allows for a maximum delay of 1456 ÷ 109 + 0.1 = 13.4 seconds. If the delay is set to more than 12 seconds siliconchip.com.au then the sampling rate is reduced again. This process continues down to a minimum sampling rate of 9.77kHz (40MHz ÷ 4096) – see Table 1. To aid in this process, the software keeps track of the sampling rate used to record each block stored (1480 total), allowing it to play back each block at the same rate as it was recorded. This is necessary because the playback rate only changes some time after the recording rate changes, ie, when the first block recorded after the rate change makes its way through all three buffers. This means that at some point after the sampling rate changes, there may be a small glitch in the audio due to the sudden change in sampling rates. This only occurs once, until the sampling rate stabilises and it is usually innocuous. If the delay is reduced far enough to allow a higher sampling rate to take effect, the rate will automatically be increased using the reverse of the process described above. Circuit details Refer now to the complete circuit diagram, shown in Fig.3. The audio signal from the radio is applied to RCA connector CON2, with a 100kΩ Table 1: Sampling Rate vs. Maximum Delay & Frequency Sampling Rate Maximum Delay Switching Point Maximum Audio Frequency 39.06kHz 9.0 seconds 8 seconds 19.53kHz 26.04kHz 13.4 seconds 12 seconds 13.02kHz 19.53kHz 17.9 seconds 16 seconds 9.77kHz 9.77kHz 35.7 seconds – 4.88kHz May 2011  29 +5V +3.3V 100nF 10 16 Vdd MR 32 Q0 1 Q1 2 Q2 3 Q3 14 IC3 Q4 4 SD 74HC595 5 Q5 6 12 LCK Q6 7 Q7 13 9 OE Q'7 Vss 11 100 9 31 30 28 27 26 25 23 1 2 SRCK 3 4 5 6 7 8 8 16 10 100nF MR Vdd Q0 15 3 IRD1  IC2 AS6C4008 22 CE 24 OE 29 WE 12 A0 11 A1 A2 10 10 1k 13 14 15 17 18 19 20 21 1 16 15 11 14 7 17 RB0' 8 1 18 RB1' 21 2 3 +4.5V 4 5 100k CON2 AUDIO INPUT 100 470nF 6 5 6 100k IC6: TL074 IC6b VR1 10k LOG 2.2k 7 3 2 IC6a 470nF 2.2k 2 13 MCLR Vdd AVdd RB7 RB6 RB4 RB13 RB5 RB12 RB3 RB11 RB8 RB9 RA4 RB10 RA3 11k RB2 AN0 DAC1LP 10k IC7: LM339 D2 A 1k K 1 IC7b 10k 6 100k 22k 300 4 2 CLIPPING  LED1 IC7a K SC 2011 26 7 C A 25 +3.3V 10 F B 10 +4.5V +5V Q1 BC557 12 RB1 DAC1LN E 23 22 RB0 11k +4.5V 24 RA1 2.2nF 2.2nF 10 F 100nF 28 IC1 dsPIC33FJ64GP802 22k 11k 1nF 1 100nF 16 D0 D1 D2 D3 D4 D5 D6 D7 1 Q1 2 Q2 SRCK 3 Q3 14 IC4 Q4 4 SD 74HC595 5 Q5 6 12 LCK Q6 7 Q7 13 9 OE Q'7 Vss A3 A15 A17 A13 A8 A9 A11 A10 A18 A16 A14 A12 A7 A6 A5 A4 11 100nF 100nF 15 CLKI +1.65V 20 5 1k 10k 10 F TANT 9 Vcap Vss 8 AVss 27 Vss 19 SPORTSYNC AUDIO DELAY MODULE Fig.3: this is the complete circuit. The audio is delayed using microcontroller IC1 and static RAM chip IC2. Op amps IC6a-IC6d condition the audio input and output signals, while comparators IC7a-IC7d perform audio signal clip detection and drive the two status indicator LEDs. IC5c and IC5d form the crystal oscillator circuit which drives pin 9 of IC1. 30  Silicon Chip siliconchip.com.au REG2 LM3940IT–3.3 +3.3V OUT 100nF IC5: 74HC00 14 3 IC5a 1 6 2 IC5b IN GND 100 F +3.3V REG1 7805 +5V OUT D1 1N4004 10 IN +9V GND 100 F K + A 9V DC INPUT – 47 F CON1 5 4 A LED2 A  LED3  K K IC7: LM339 300 11 100k 10 RB0' IC7d 13 +9V 100pF 9 100k RB1' 300 8 3 IC7c 100nF 14 12 100pF 1k +1.65V +4.5V 100 F 1k +9V 13k 10k 10 F 10 9 10k 10 F 8 IC6c 8 IC5c 7 9 12 VR2 10k LOG 13 4 IC6d 10 F 14 CON3 100 AUDIO OUTPUT 11 10k 2.2nF 15nF 10 F 1M 11 10 2.2k 2.2k 150pF 13k IC5: 74HC00 100nF IC6: TL074 IC5d 12 13 33pF 33pF B K A E C D1: 1N4004 A A IRD1 K D2: 1N4148 siliconchip.com.au BC557 LEDS X1 8.0MHz K 1 2 7805, LM3940IT-3.3 GND IN 3 GND OUT May 2011  31 Parts List 1 PC board, code 01105111, 118 x 104mm 1 ABS instrument case, 140 x 110 x 35mm (Jaycar HB5970, Altronics H0472) 4 No.4 x 9mm self-tapping screws 1 9V 150mA+ plugpack (Jaycar MP3146, Altronics M8922) 1 universal infrared remote control (eg, Altronics A1012, Jaycar AR1726) 1 8MHz HC49 crystal (X1) 1 PC-mount DC socket (CON1) 2 PC-mount switched RCA sockets (CON2, CON3) 2 10kΩ logarithmic 16mm potentiometers (VR1, VR2) 2 small knobs to suit VR1 & VR2 3 5mm LED right-angle mounts 1 32-pin or 40-pin DIL socket 1 28-pin DIL socket 2 16-pin DIL sockets (optional) 3 14-pin DIL sockets (optional) 1 400mm length 0.71mm diameter tinned copper wire Front & rear panel labels Semiconductors 1 dsPIC33FJ64GP802 microcontroller programmed with 0110511A.hex (IC1) 1 AS6C4008-55PCN 512k x 8bit 3.3V SRAM (IC2) 2 74HC595 octal serial-toparallel latches (IC3, IC4) 1 74HC00 quad NAND gate (IC5) pull-down resistor for DC biasing. Following this is a resistor/capacitor (RC) low-pass filter of 100Ω and 1nF, which eliminates any radio frequency (RF) signals picked up by the signal lead. The audio signal is then AC-coupled with a 470nF capacitor and biased to half supply with a 100kΩ resistor. This nominally 4.5V half supply voltage is generated with a simple 1kΩ:1kΩ resistive divider and filtered with a 100µF capacitor, to remove any supply ripple. Biasing the signal to this level allows the op amps which process it later to have a symmetrical swing within the supply rails. The signal is buffered and amplified by IC6b, one quarter of a TL074 quad low noise JFET-input op amp. The amplification factor is two, set by the two 11kΩ feedback resistors. This allows for an input signal of up to around 1V 32  Silicon Chip 1 TL074 quad JFET-input op amp (IC6) 1 LM339 quad comparator (IC7) 1 infrared receiver (IRD1) 1 7805 3-terminal regulator (REG1) 1 LM3940IT-3.3 low dropout regulator (REG2) 1 BC557 PNP transistor (Q1) 1 1N4004 1A diode (D1) 1 1N4148 switching diode (D2) 1 red 5mm LED (LED1) 1 yellow 5mm LED (LED2) 1 green 5mm LED (LED3) Capacitors 3 100µF 16V electrolytic 1 47µF 25V electrolytic 6 10µF 16V electrolytic 1 10µF 16V tantalum 2 470nF MKT 9 100nF MKT 1 15nF MKT 3 2.2nF MKT 1 1nF MKT 1 150pF ceramic 2 100pF ceramic 2 33pF ceramic Resistors (1%, 0.25W) 1 1MΩ 4 2.2kΩ 5 100kΩ 5 1kΩ 2 22kΩ 3 300Ω 2 13kΩ 3 100Ω 3 11kΩ 2 10Ω 6 10kΩ RMS before clipping occurs. The signal then passes through another RC low-pass filter (2.2kΩ/2.2nF) with a -3dB point of 33kHz, to filter out any supersonic components of the signal. This reduces aliasing artefacts in the later analog-to-digital converter (ADC) stage which can result from signal frequencies above the Nyquist frequency (ie, half the sampling rate). Following the second RC filter is potentiometer VR1 which allows the overall recording gain adjustment. This is important since we want the signal swing to be just below the clipping point for the ADC, to maximise dynamic range. The 10µF capacitor prevents DC current flow through the potentiometer due to the signal DC bias. It charges up to half supply via the potentiometer. The resulting audio signal then passes through IC6a which is also configured as a buffer and gain stage. This time the gain is three ((22kΩ + 11kΩ) ÷ 11kΩ). It is followed by another 33kHz low-pass filter to further reduce aliasing. The -3dB point of the combined filters is around 21kHz. The signal is AC-coupled and DCbiased again with another 470nF capacitor, this time to half the 3.3V supply, ie, nominally 1.65V. This halfsupply rail is generated with another resistive divider, this time comprising two 10kΩ resistors. There is no filtering since this rail is regulated. The signal is applied to the AN0 analog input of IC1. IC1 samples the voltage at AN0 at one of the above-mentioned sampling rates, depending on the delay setting. The audio is then later converted back into an analog signal by the internal DAC and appears at pins 25 and 26 of IC1 (DAC1LP and DAC1LN). The signal at pin 26 is inverted compared to pin 25 and we obtain the final audio signal by subtracting these two voltages, to reject any common distortion or noise. This subtraction is performed by IC6c, which is configured as a differential amplifier. The 150pF feedback capacitor reduces amplifier gain at high frequencies for stability as well as providing some low-pass filtering to remove DAC switching noise. The two 10µF AC-coupling capacitors allow the DAC output signal to be re-biased to the 4.5V half supply rail, so IC6c can operate correctly. The audio signal then enters another low-pass filter identical to those used earlier, to further attenuate DAC switching noise and then passes to the 10kΩ volume adjustment potentiometer. As with VR1, this also has a 10µF capacitor to prevent DC current flow through it. The audio signal is buffered by IC6d (a voltage follower) and AC-coupled so that it is symmetrical about ground. It then passes through a third low-pass RC filter consisting of a 100Ω resistor and 15nF capacitor, with a corner frequency of 106kHz. This is deliberately high so that additional cable capacitance will not attenuate the high audio frequencies and the 100Ω resistor also provides output short-circuit protection. Clip detection The signal input to the ADC should be just below 3.3V peak-to-peak since siliconchip.com.au the ADC’s resolution is limited. If the signal voltage is significantly less than the ADC’s range, the resulting resolution will be less than the full 12 bits. If the input to AN0 exceeds either of IC1’s supply rails, the result contains unpleasant high-frequency clipping artefacts. The clip detection circuit helps the user maximise ADC resolution without clipping the signal. IC7 is a quad comparator with opencollector outputs. Two of its stages are used to detect clipping. The audio signal is applied to the non-inverting input of IC7a and the inverting input of IC7b. Their outputs are connected together to form a window comparator. The “window” is defined by three resistors, two 1kΩ and one 22kΩ, connected between the +3.3V rail and ground. The voltages on either side of the 22kΩ resistor are about 3.16V and 0.14V. If the signal voltage is outside this range, the output of one comparator goes low, pulling current through diode D2, charging the 10µF capacitor. When this capacitor has charged, current flows through the 10kΩ resistor from Q1’s base, supplying current to the clip LED (LED1), which is limited to 10mA by the 300Ω series resistor. The capacitor charges quickly but discharges slowly, ensuring the LED lights for long enough to be visible. Memory interface As explained earlier, we are using an SRAM chip to buffer the audio data. This is essentially a large array of 8-bit registers packed in a chip (524,288 registers to be exact). This makes it very fast and gives practically infinite rewrite cycles but it is significantly more expensive than dynamic RAM (DRAM). However DRAM is harder to interface with; see the adjacent panel for more details. Interfacing with the SRAM chip presents some challenges. The AS6C­ 4008 has 19 address inputs, three control lines (write enable, output enable and chip enable) and an 8-bit data bus. That’s a total of 30 inputs or outputs (I/Os). With the type of microcontroller we are using, we would have to use a surface-mount package to get enough pins to interface directly with such an IC. To avoid this, we drive 16 of the 19 address lines (A3-A18) with two high-speed 74HC595 serial-to-parallel latch ICs (IC3 and IC4). The remaining three address lines (A0-A2) are driven siliconchip.com.au SRAM & DRAM: What’s The Difference? Processors use two types of random access memory (RAM): static RAM (SRAM) and dynamic RAM (DRAM). SRAM is used where speed is critical, eg, for processor instruction and data caches, hard drive caches and so on. DRAM is used for bulk storage such as main memory. SRAM is essentially just a series of registers, where each is formed from a number of CMOS transistors (ie, Mosfets); typically six are required per bit. This forms a bistable element and as long as power is applied, the memory state is retained. Because Mosfets consume most of their power when switching, idle SRAM power can be very low. When an SRAM is inactive its power consumption is almost entirely due to the gate leakage currents. Since it is built from transistors, SRAM is also fast. Speed is limited primarily by propagation delays and transistor switching speeds. On the other hand, data is stored in DRAM using small capacitors which are fabricated on a silicon die. In modern DRAM, these capacitors are typically built in “trenches” to increase density. The charge in each capacitor represents one data bit and each capacitor is normally accompanied by a single transistor which connects the capacitor to the data bus when that bit is to be read or written. Because each DRAM cell contains just one transistor and one capacitor, DRAM density can be very high, so a single DRAM chip can store a lot more data than a similarly sized SRAM chip. There are three drawbacks to DRAM though: speed, power consumption and interface complexity. Speed is limited because the capacitors take time to charge and discharge and because when reading DRAM, to avoid discharging the capacitor, the current drain must be kept low. The DRAM interface is more complicated because the capacitors won’t hold a charge forever. They eventually discharge via leakage. This means that DRAM must be constantly “refreshed” every 64ms or so. To refresh the RAM, essentially it is read and then re-written, topping up the charge on the capacitors. Refreshing is an extra task which must be managed by the DRAM controller and it can’t interfere with the normal operation of the memory, ie, it must be hidden from the processor (or else the processor has to be aware of it and work around it). This is also the reason that power consumption is typically higher than for SRAM. The refresh circuitry must be constantly active, even when memory is not being accessed, and this means extra power consumption regardless of how active the memory bus is. So when speed is critical, SRAM is used and when capacity is the dominant requirement, DRAM is the best choice. directly from the micro. This means that we can read or write a block of eight bytes of data quickly and then to change blocks, we shift one of 65,536 possible block addresses into the serial latches. Since the serial transfer can occur at the same time as we are reading or writing our 8-byte block, this doesn’t slow down memory access. The new address is shifted into the latches by one of IC1’s internal serial peripheral interface (SPI) units and when it is time to change the address, the LCK line shared by IC3 and IC4 is brought high, instantly switching to the new address. Data transferred to and from the SRAM goes over an 8-bit bus (DQ0DQ7) that is connected directly to eight consecutive pins in the micro (RB4-RB10). To save another pin, we can control the three memory control lines using two microcontroller outputs. To write to the SRAM, we bring output RA4 low. This directly pulls input WE-bar (write enable) of IC2 low but it also brings CE-bar (chip enable) low via the AND-gate formed by IC5a and IC5b. Both of these inputs to IC2 must be brought low to perform a write operation. Similarly, to read from the SRAM, output RA3 brings IC2’s OE-bar (output enable) input low as well as the CE-bar (chip enable) input, via the same AND-gate. All in all, we use three of IC1’s pins to drive the serial address bus (RB0 for May 2011  33 SportSync 9V DC 33pF D1 4004 CON1 100nF TIP+ IC4 74HC595 100nF OUTPUT 47 µF 25V + REG1 7805 REG2 LM3940-3.3 + 100k 22k 10 µF 10k 150pF IC6 TL074 Q1 BC557 100nF 13k 13k 2.2k 2.2nF IRD1 100nF 1k 10k 100nF 11k SC D2 100nF K 100Ω 300Ω IC7 LM339 100 µF + 4148 2.2k 1k 1k 11k 470nF 1nF 11k + 01105111 © 2011 10 µF 10 µF 22k 100k 2.2nF IC1 dsPIC33FJ64GP802 10k 10k 10k 1k 1k + 100k 2.2k 100Ω VR1 10k LOG 10Ω 470nF + + 100nF 10Ω 100nF 10 µF 100k 100k 100 µF + 10 µF INPUT IC2 AS6C4008 + 2.2nF 100Ω VR2 10k LOG 10 µF CON3 CON2 Value µF Value IEC Code EIA Code 470nF 0.47µF   470n   474 100nF 0.1µF   100n   104 15nF 0.015µF   15n  153 2.2nF .0022µF   2n2  222 1nF .001µF    1n  102 150pF   NA   150p   151 100pF   NA   100p   101 33pF  NA   33p   33 IC5 74HC00 IC3 74HC595 15nF + 2.2k 1M 33pF 100nF Table 2: Capacitor Codes X1 8.0MHz 300Ω 300Ω 10k + 2 x 100pF 10 µF CLIP LED1 A ACTIVITY LED2 K A POWER LED3 K A Fig.4: follow this parts layout diagram to build the PCB. All components mount on this board which fits neatly into a small plastic instrument case. Ensure that the electrolytic and tantalum capacitors, diodes and ICs are installed with the correct orientation. serial data, RB1 for the serial clock and RA1 for the latch control), three pins for the remaining address lines, eight pins for the data bus and two to initiate reads and writes, for a total of sixteen control lines. This leaves just enough free pins for the other functions we require, with some pin multiplexing. Status LEDs We use multiplexing to drive two status LEDs without the need for additional micro pins or external latches. Outputs RB0 and RB1 primarily drive the serial bus but when it is idle (which is much of the time), their state determines whether LED2 and LED3 are lit. The serial peripheral which drives RB0 and RB1 is switched off when it is not being used and each pin is held either low or high. Because the serial bus is only being used a fraction of the time, the average voltage at the RB0 and RB1 pins is mostly controlled by their 34  Silicon Chip The view at right shows the fully built PC board. Take care not to get the two 3-terminal regulators (REG1 & REG2) mixed up and note that they face in opposite directions. Note also that there are a few minor differences between this prototype and the final version shown in Fig.4. state between serial bursts. The voltage is averaged by two low-pass RC filters consisting of 100kΩ resistors and 100pF capacitors, with a -3dB frequency of 16kHz. The voltage across these capacitors is compared to the 3.3V half supply voltage (ie, around 1.65V) by IC7d and IC7c. These drive LED2 and LED3 respectively, via 300Ω current-limiting resistors, setting the LED current at around 10mA. The LEDs are on if the filter capacitor voltage is above 1.65V, which is true only when the corresponding I/O pin is being idled in the high (+3.3V) state. Power supply The power supply is simple. Diode D1 provides reverse polarity protection and the following 47µF capacitor provides a small amount of filtering. This unregulated supply voltage powers the quad op amp (IC6) and the quad comparator (IC7). Regulator REG1 provides a 5V supply for the infrared receiver (IRD1), the LEDs and the pulse stretching circuit of the clip detector. The 100µF capacitor at REG1’s output reduces noise on the 5V line and the 10Ω series resistor reduces regulator dissipation by about 100mW. The load on the 5V regulator draws around 100mA and depending on the supply voltage it drops between 2.3V and 5.3V, giving a dissipation of 230530mW. It does not need a heatsink although if the supply voltage is at the upper end of the range it will run hot to the touch. The 5V supply for IRD1 is further filtered with a 100Ω resistor and 100nF capacitor to keep switching noise from the other components away from IRD1, as infrared receivers can be quite sensitive to power supply noise. The majority of current drawn from REG1 is actually for the +3.3V rail which is regulated by REG2 for the microcontroller (IC1), SRAM (IC2) and the digital logic ICs (IC3-IC5). The 100µF capacitor at its output is not just for filtering; it is required for stability since REG2 is a low-dropout type. Construction Before assembling the PCB, check the copper side for any defects such as broken tracks or under-etched areas siliconchip.com.au and repair if necessary. Also check that the board fits inside the case when the plastic end-panels are in place and that the mounting holes line up with the plastic posts. It’s a good idea to then test-fit the larger components, such as the RCA sockets, to ensure that the holes have been drilled large enough. Refer now to Fig.4 for the assembly details. Start by installing the 14 wire links using tinned copper wire. Alternatively, 0Ω resistors can be used in some locations if desired. Make sure that the links are straight, so that they can’t contact adjacent pins later. You can straighten the link wire by up as shown on the overlay diagram. If you don’t have a 32-pin socket for IC2, you can cut four pin rows off the end of a 40 pin socket using side-cutters, or you can use pin header strips. Now install the three 5mm LEDs, using plastic right-angle LED mounting blocks. In each case, start by inserting the LED’s leads through the holes in its mounting block, with the anode (longer lead) aligned so it will go through the pad nearest the anode (A) marking on the overlay. That done, bend the leads down to a right-angle, using the mounting block as a bending jig. The assembly can then be soldered in place. If you don’t have plastic LED mounting blocks, you can instead bend the LED leads 5mm from the body and install them with the horizontal portion of the leads 3.5mm above the top of the PCB. Now fit the ceramic and MKT capacitors. Don’t get the different values mixed up. Transistor Q1 (BC557) can then be soldered in place. If necessary, crank its leads out using small pliers before fitting it to the board. Next, bend the leads of the infrared receiver back away from the lens at right angles, as close to the body as possible. That done, bend them back down again, leaving a 4mm horizontal lead section. The IR receiver can then be pushed all the way down onto the board and soldered it in place – see photos. Follow with the tantalum capacitor. This device is polarised, so make sure it goes in the right way around. Its positive lead is indicated by a “+” symbol on the body and is usually on the right with the label side facing you. The electrolytic capacitors can then clamping one end in a vice and pulling on the other end using a pair of pliers, to stretch it slightly. Follow with all the fixed value resistors, using a DMM to check the value of each one before soldering it in place. The two diodes can then go in, taking care with their orientation (they face in opposite directions). The larger 1N4004 resistor goes at the top of the board, near the power socket mounting location. The IC sockets and any ICs that are being soldered directly to the board can go in next. In both cases, ensure that the notch or pin 1 marker is lined Table 3: Resistor Colour Codes o o o o o o o o o o o o siliconchip.com.au No.   1   5   2   2   3   6   4   5   3   3   2 Value 1MΩ 100kΩ 22kΩ 13kΩ 11kΩ 10kΩ 2.2kΩ 1kΩ 300Ω 100Ω 10Ω 4-Band Code (1%) brown black green brown brown black yellow brown red red orange brown brown orange orange brown brown brown orange brown brown black orange brown red red red brown brown black red brown orange black brown brown brown black brown brown brown black black brown 5-Band Code (1%) brown black black yellow brown brown black black orange brown red red black red brown brown orange black red brown brown brown black red brown brown black black red brown red red black brown brown brown black black brown brown orange black black black brown brown black black black brown brown black black gold brown May 2011  35 14 C 8 16.5 12 C 18 B B A 11 21 22.75 21.5 21.25 23 134 19.5 21.5 D D 18.75 10 30 E D 10 10.25 HOLE A: 8 x 11mm RECTANGULAR HOLES B: 8mm DIAM. HOLES C: 6.5mm DIAM. HOLES D: 5.0mm DIAM. HOLE E: 3.5mm DIAM. ALL DIMENSIONS IN MILLIMETRES LI P V C E C TI A P O W R IT Y P IN G Fig.5: use this drilling template as a guide for making the holes and cut-outs in the two plastic end-panels for the case. It’s best to use a small pilot drill (eg, 2mm) to start the holes (so that they are correctly centred), then carefully enlarge them to size using large drill bits or a tapered reamer. Fig.6: the front and rear panel labels can be copied and attached to the endpanels. Alternatively, a PDF of these labels can be downloaded from the SILICON CHIP website and printed out. all go in, again taking care to ensure they are orientated correctly. Don’t get the different values or voltage ratings mixed up. Next, fit the RCA sockets and DC connector. In each case, the connector must be pushed down right onto the PCB and adjusted so that it is at right angles to the board edge before being soldered in place. The crystal (X1) can then go in, followed by regulators REG1 & REG2. Note that the metal tabs of the regulators face away from each other. Ensure that the 3.3V regulator is installed nearest to the PCB edge. Now for the two potentiometers (VR1 & VR2). Before mounting them, 36  Silicon Chip SILICON CHIP SPORT SYNC 9V DC -+ AUDIO INPUT AUDIO OUTPUT OUTPUT VOLUME cut the shaft of each pot to a length of 17mm using a hacksaw and file off any burrs. The two pots can then be soldered to the board, making sure they are pressed down fully and that their shafts are parallel with the PCB surface. Finally, complete the PCB assembly by inserting the ICs into their sockets. Check that they are all correctly orientated; if not, they could be damaged when power is applied. Testing It’s a good idea to carry out a few tests before installing the board in a case. To do this, first place the completed PCB on a non-conducting INPUT GAIN SPORT SYNC surface and turn both potentiometers fully anti-clockwise. That done, connect a power supply with a DMM (set to measure amps) in series with one of the supply leads. Now apply power and watch the LEDs. Initially, all three LEDs should come on but the red LED should turn off after a second or so. Check that the current is around 100-120mA. The green and yellow LEDs should remain on during the initial memory test, which takes 2-3 seconds. At the end of this period, the state of these LEDs indicates whether or not the board is functioning normally: • Green LED only: memory test successful, operation is normal. siliconchip.com.au The board fits neatly inside a standard plastic instrument case from Jaycar or Altronics. • Yellow LED only: memory test failed – check that IC2 is properly installed and that there are no solder bridges, short circuits or broken tracks. • Both LEDs off or remain lit for more than a few seconds – microcontroller or power supply failure. • Red LED remains lit for more than a few seconds – error in analog input circuitry – check that IC6 & IC7 and their associated components are installed correctly. If, after a few seconds, the green LED is the only LED lit and the current drain is around 100mA, you can proceed with an audio test. You will need to connect a signal source (eg, an AM radio) to the input connector and headphones or an audio amplifier to the output connector. Having done that, turn up the gain knob until the red clip LED lights, then turn it down slightly so that it is no longer does. Now turn up the volume control – you should hear the signal source being repeated at the output with a slight delay (around 0.2s). If you can hear it clearly, then the unit siliconchip.com.au is operating normally. Now check that the remote control works. Set it to the appropriate Philips VCR code (eg, 115 for the Altronics A1012 remote and 916 for the Jaycar AR1726), point it at the receiver and press the 1, 2 & 3 number buttons. The yellow LED should flash in response and the audio delay should change to be 1, 2 or 3 seconds depending on which button is pressed. Check also that the volume down/up buttons work. Finishing construction Fig.5 shows the drilling details for the end-panels of the plastic case. Start with 2mm pilot holes on the rear panel, then enlarge them using a tapered reamer or larger drill bits. Check the hole sizes regularly by test fitting the panel to the pot shafts and the RCA connectors. When the hole sizes are correct, de-burr them using a larger drill bit. For the DC socket, start with a 5mm hole in the centre and then enlarge the hole to a rectangle using a needle file. Continue until the DC connector fits neatly through the hole. The front panel requires three 5mm holes to accept the LEDs plus a 3.5mm hole for the IR receiver. Again, it’s best to start these holes using a small pilot drill (eg, 2mm), to ensure accuracy. The bottom of the case has eight moulded plastic posts. The four inner posts must be removed (or reduced in height), otherwise they will interfere with the solder joints on the bottom of the PCB. Use sidecutters to make vertical cuts in the side of each post and then small pliers to break sections off. They can then be filed to a neat finish. Once the drilling is complete, attach the rear panel to the PCB using the potentiometer washers and nuts. That done, push the front panel into place and then slide the whole assembly into the case. Check that the PCB sits correctly on its mounting posts and that the lid can be fitted with everything in place. It’s then just a matter of laminating the front and rear panel labels before attaching them using spray adhesive. These panels can be downloaded from the SILICON CHIP website (in PDF format) and printed out, or you can use a copy of Fig.6. You will have to temporarily remove the assembly from the case and detach the panel in order to fit the labels. Alternatively, if you purchase a kit, the labels will either be supplied or the panels will come pre-drilled with screened lettering. Once the labels are on, cut out the holes using a sharp hobby knife, then refit them to the PCB. The assembly can then be lowered into the case and secured using four self-tapping screws. Complete the assembly by fitting the lid and pushing the two knobs onto the potentiometer shafts. Using it Using the device is easy. First, connect the output of your radio to CON2 (Audio Input). Most small radios have a 3.5mm stereo jack headphone output so you will need to use a 3.5mm stereo jack to twin RCA plug cable. Plug the jack into the radio and connect one of the RCA plugs to CON2. Sport commentary is typically on AM radio which is usually monaural so it may seem redundant to use a stereo cable. However, since most May 2011  37 The front panel carries the three indicator LEDs plus an adjacent hole for the infrared receiver. The two pots (Input Gain and Output Volume) are mounted on the rear panel and once set for a particular installation, should not need touching again. Also on the rear panel are the input and output RCA connectors and a DC power socket. Virtually any universal IR remote control can be used to operate the SportSync Audio Delay, including this Digitech unit from Jaycar (Cat. AR1726). The Altronics A1012 is also suitable (see text for codes). radios can also receive stereo FM, we don’t want to insert a mono plug and risk shorting the two output channels together. It probably won’t cause any damage but it’s best not to find out. Some radios have RCA output sockets and in this case a cable with an RCA plug on each end is all that’s required. The unit’s output can be connected to headphones, earphones, a power amplifier or a TV’s audio input. Headphones or earphones may be connected directly, using an RCA to phono jack cable, or via a headphone amplifier. Most power amplifier and TV audio inputs will be RCA sockets so a simple RCA plug to RCA plug cable should do the trick. With the connections made, follow this step-by-step procedure to adjust the unit and set the levels: (1) Set the Input Gain control to about two-thirds clockwise, then turn the 38  Silicon Chip radio’s volume control up until the Clipping LED just lights. If necessary, advance the Input Gain control further to achieve this. When the Clipping LED comes on, turn the radio’s volume down until it goes out again. (2) Turn the Output Volume down and apply power. Wait until the green LED lights, then advance the Output Volume until you hear the radio. (3) Set the volume to the loudest level that you would ever use, then use the remote control to turn the it down to a comfortable level. This will give you an appropriate volume control adjustment range. (4) Set the delay to synchronise the audio to the TV image. You will probably need to wait for a sport event in order to set it. Initially, use the number buttons on the remote control (0-9) to set the delay, in seconds. If eight seconds is not enough then press the number nine and the sampling rate will automatically drop. This is indicated by the flashing green LED. With a sampling rate below 39kHz, the 0-9 buttons no longer correspond exactly to a number of seconds but instead set the delay somewhere between minimum (0 button) and maximum (9 button). (5) To increase the delay beyond 9 seconds or to make fine delay adjustments, use the channel up/channel down buttons. You will need to use these buttons to get the delay just right. Once the delay is correct, it will be remembered next time the unit is switched on, along with the volume setting. You can also use the Mute button on the remote to temporarily switch the sound off. When the unit is muted, the yellow LED will flash SC periodically. siliconchip.com.au