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A Digital VFO with Graphics Display This DDS VFO uses a widely available recycled Nokia cellular phone LCD to display analog and digital frequency readouts, text, and VFO status messages F or several years, I’ve wanted to build my own DDS (Direct Digital Synthesis) VFO (Variable Frequency Oscillator). Analog Devices makes one of the most popular ranges of DDS chips which digitally generate precise sine waves covering frequencies from practically “DC to daylight”; well, up to many hundreds of MHz. Some time ago I managed to obtain several samples but, for some time afterwards, that was as far as things went. I was just too busy with work and family to devote any time to the project. In addition, I couldn’t locate a suitable design to build. Practically all existing designs use one of the PIC microprocessor family. Others use several PIC microprocessors; yet others use a further large bunch of ICs to interface displays and keypad functions. With my microprocessor development tools all focused on the 8051 family – and being fundamentally of a contrary nature – I was determined to use an 8051 chip in my DDS VFO rather than mess about gearing up for another microprocessor, and keep the chip count minimal. Underlying this was a feeling that if I wrote my own software, I could customise it to suit my precise requirements and be better placed to develop one or two other DDS-based projects I have in mind. Of course, that naively assumes I’ll find the time to complete those new designs. Fig.1: the promise of things to come? The DDS VFO with its cellular phone “readout” mounted inside an HF transceiver the author is currently working on . . . 58  Silicon Chip siliconchip.com.au h LCD CLOCK fc by Andrew Woodfield ZL2PD ADDRESS COUNTER n bits SINEWAVE LOOKUP REGISTER DIGITAL TO ANALOG CONVERTER fOUT DIGITAL TO ANALOG CONVERTER fOUT Fig.3: basic Direct Digital Synthesis system. FIG 3: BASIC DIRECT DIGITAL SYNTHESIS SYSTEM PHASE ACCUMULATOR TUNING WORD M 24–48 bits n bit carry  n bits PHASE REGISTER 14–16 bits PHASE TO AMPLITUDE CONVERTER SYSTEM CLOCK fc Operator interface Let’s not forget the operator interface. Practically all existing designs use a standard 2 line x 20 character alphanumeric display. An earlier popular design used high current seven segment LED displays. The size of both of these displays and the limited information presented to the operator didn’t seem ideal to me. They certainly weren’t well suited for the small HF transceiver I’ve also been building. This led to another delay while I looked for alternative displays and a series of experiments with some small cheap, graphical LCD modules. These monochrome LCDs were used in many older cellular phones, as well as in some current low cost entry-level models. I built several small projects using one of the most commonly used Fig.2: the readout, from a Nokia cellular phone, is capable of displaying simple graphics . . . siliconchip.com.au Fig.4: a typical Direct Digital Synthesis system. FIG 4: TYPICAL DIRECT DIGITAL SYNTHESIS SYSTEM graphical LCDs, the Nokia 3310 LCD module. This LCD turned out to be very useful – It offers a 84 x 48 pixel display with a visible area of about 35mm x 25 mm. DDS Oscillators Direct digital synthesis (DDS) is a digital method to generate waveforms, usually sine waves. In contrast to the more common phase locked loop (PLL) approach which uses a voltage controlled oscillator, digital dividers and a phase detector to generate frequencies in defined steps, data stored in an internal DDS chip table is passed to a digital to analog (D/A) converter at a specific clock rate. If the table contains values equivalent to the amplitude of a sine wave, then a sinewave at a frequency related to the clock rate will be produced. One such basic DDS is illustrated in Fig.3. By changing the clock speed, a wide range of sinewave frequencies can be generated. If the clock is fast enough, frequencies can readily be generated across wide ranges, and at sub-Hz increments. The completely digital nature of the DDS oscillator and its ability to generate very fine frequency increments are the main advantages over PLLs. In practice, a DDS device uses the arrangement shown in Fig.4. The tuning word, which is usually 32 or 48 bits wide, is used to modify a phase accumulator. This outputs a 14-16 bit word for onward signal generation. With this approach and with a 32-bit tuning word, it is possible to generate more than 4 billion specific frequencies. For more information on DDS chips, the introductory documents on the Fig.5: and here it’s shown mounted on the back of the PC board, along with the six control switches. There are minor differences to the correct layout shown in Fig.8. March 2008  59 bands. The LCD modules the current operating frequency and mode of the VFO. A key feature of this design is an analog-style graphics-driven dial displayed on the LCD which sweeps up and down just like a conventional mechanical dial while tuning the VFO. The VFO also features two independent VFOs, a programmable receiver IF offset capability, full RIT, and VFO locking. All of this software is handled within a single 20-pin low cost Atmel 89C4051 microprocessor. The DDS drivers within the microprocessor are quite compact, but much of the space within the 4K bytes of flash program memory is actually required for lookup tables to handle the Nokia 3310 LCD. Unlike standard 2 line x 20 character alphanumeric displays, all of the information displayed has to be generated, dot by dot, by the 89C4051 microprocessor. Each and every character, every graphical feature, all resides within the 4K of program memory. The VFO code itself amounts to less than 1.5Kbytes, the balance taken up by the graphics tables. There is also some room in the program memory to permit other builders to add features to suit individual Fig.6: there are two ways to construct the DDS VFO – cut the board and “sandwich” the two sections as shown here, or leave the board intact (the tracks for the two sections are provided). As you can see from this photo, the component side of the PC board(s) is a groundplane, formed by using double-sided PC board blank. Analog Devices website at www.analog. com are highly recommended. The most significant problems with DDS oscillators are noise and spurious emissions. These can be minimised by using D/A converters with relatively long digital words. Many DDS devices are limited to 10-bit words but newer devices more often use 12-bit or 14bit words. This DDS VFO uses an Analog Devices AD9850 chip which uses a 10-bit D/A. This delivers a spurious emission level of -50dB. Frequencies are selected using 32 bits of a 40 bit tuning word, allowing better than 0.03Hz frequency steps 60  Silicon Chip At right is the optical encoder, made from a surplus mechanical mouse with the 80MHz DDS clock used in this design. The balance of the 40 bit word is used for phase and control functions. Since this level of resolution exceeds most requirements, many DDS VFO designs use a larger step size. In this VFO design, the user can select 10Hz, 100Hz or 1kHz steps to give three tuning rates – slow, medium and fast. Functionality The DDS VFO covers all amateur radio bands between 160m and 10m in 10Hz, 100Hz or 1kHz increments, and will happily tune outside of these requirements. The code uses no special features of the AT89C4051 and so it may be used with almost any 8051-type processor possessing adequate memory. One option might be the addition of country-specific frequencies, for example, not currently supported by the present VFO software. To that end, the fully commented source code is available from my website, as well as the Intel hex file for direct programming of blank microprocessors. The Design In contrast to other designs, this DDS VFO design is almost minimalsiliconchip.com.au siliconchip.com.au March 2008  61 LOCK VFO A/B PTT RIT 4 IC1b 22pF 22pF 10k +5V 7 IC1: LM393 1 X1 8.866MHz 22k 5 6 8 IC1a 10k RST 5 4 12 16 15 14 13 X2 X1 P1.0 P1.4 P1.3 P1.2 P1.1 7 P3.3 INT1 6 P3.2 INT0 1 GND 10 IC2 AT89C4051 Vdd 20 P3.0 P3.1 P3.4 P1.5 P1.6 P1.7 P3.7 A A A Vo CS 5 8 7 9 7 2 IC3 80MHz OSC 8 3 14 100nF 7 +5V 8 Rset D2 Vddd 2 5,24 Dgnd CLKin 22 10,19 Agnd RST IoutB 20 12 3,4, 6,23 100nF 56 100 10 F IN 150pF 33pF L2 330nH* IN 100pF 100nF 1 2,4 3 A A K OUT 100nF RFC3 100 H 120 K 12V DC RF OUT 2 3 ERA-4 LEDS ADJ BEVELLED 4 END 1 IN – + LM317LZ RFC4 100 H 1N4148 47 F IC5 ERA-4 LCD MODULE PINOUTS (REAR VIEW) 1 8 OUT GND IN 7805 GND OUT REG1 7805 * L1: 13 turns on T25-10 L2: 12 turns on T25-10 100pF 10pF L1 390nH* 100nF ADJ OUT REG2 LM317LZ RFC2 100 H 470 10 F 330  LED1 330 3.9k 4.7 F 10k +3.3V K A IC4 Iout 21 AD9850 DDS+DAC Wclk Fu/d SDin 11,18 Vdda RFC1 100 H GND 6 RST NOKIA 3310 LCD MODULE V+ 1 25 100nF 3x 10k NOT USED 1 F SDA SCL 4 D/C 3 2  LED2 1k 8 9 K A 3x 10k D1– D3 1N4148 17 K 18 K 19 K 11 100nF DDS DRIVEN VARIABLE FREQUENCY OSCILLATOR BAND 2x 10k STEP  2 3 10k 10 F Fig.7: the complete DDO VFO circuit diagram. Using the cellphone display certainly simplifies things! 2008 SC  TUNING OPTICAL ENCODER   560 100nF +5V 12V DC IN 14 IN TO IC1 PIN 3 2x 22pF NOT USED 10k 100nF IC1 LM393 10k 560 IC3 80MHz OSC 18030340 OFV SDD A K ENCODER LED 5V 22k 10k 4148 D1 4148 D2 4148 D3 + 100nF REG1 100nF REG2 10 F 10k 10k 10k S3 S2 S4 S5 1 2 3 4 5 6 7 8 330 470 + 1 F + 10 F + 4.7 F S1 NOKIA 3310 LCD MODULE S6 1k 28030340 LED1 OFV SDD LED2 = BOTTOM LAYER COPPER (TRACKS) = TOP LAYER COPPER (GROUNDPLANE) Fig.8: component overlay for the top (ground plane) side. Here the two parts of the PC board are shown still connected; the links (shown in green) are only required if you split the board and “sandwich” it. ist, using just four chips (excluding the regulators): the microprocessor, the optical encoder interface chip, the DDS, and the RF amplifier chip. This avoids the approach used in a number of other designs which requires a microprocessor dedicated to the encoder and display and a second processor dedicated to the DDS. The microprocessor is also operated at a very leisurely 8MHz. I actually used a PAL TV colour-burst crystal of 8.866MHz but any crystal from 8 to 12MHz will likely work fine. The top speed for this micro is 24MHz, so clearly nothing much is being pushed hard in this design. This might suggest that the 8051 is significantly more efficient than other 8-bit microprocessors used in similar designs. My software is all written in handcoded assembler, often far more effi- A NOTE TO SILICON CHIP SUBSCRIBERS Your magazine address sheet shows when your current subscription expires. Check it out to see how many you still have. If your magazine has not turned up by the first week of the month, contact us at silchip<at>siliconchip.com.au 62  Silicon Chip + 47 F 330 IN TO IC1 PIN 5 TO/FROM OPTICAL ENCODER – RFC4 10k 8 100nF + 10k 1 + RFC1 RFC2 100nF 100pF 56 100 100pF 7 10 F 10k 10k X1 8.866MHz 33pF 10k 10k 3.9k 150pF IC2 AT89C4051 120 L1 L2 100nF 100nF RFC3 10pF RF OUT cient than higher level languages and the code possibly also makes a little better use of interrupts. This approach allows the optical encoder (the main tuning control) to be very rapidly read without causing any measurable delays in the main DDS and display routines despite the fairly intensive data transfers required by the Nokia 3310 LCD whenever it is being updated. Interrupt-driven routines tend to be a little more complex to write but are necessary here to handle rapid updating of the digital display and the analog dial graphics, while also reading the dial and checking for any pressed buttons. These functions can add up to quite a lot of work for this modest 8051 microprocessor to manage but it is made possible by minimal mainline software functions and a relatively fast background interrupt cycle. This interrupt cycle is focused on reading the encoder, the most time-critical function. When power is applied to the VFO, the microprocessor begins by initializing the LCD module. These feature a brief animated set of graphics which illustrate some of the flexibility of the display and makes use of some spare ROM space. The 89C4051 then initialises the DDS VFO to the bottom of the 80m band in receive mode, with an offset assuming an IF of 8.467MHz, and with RIT (receiver incremental tuning) turned off. These parameters are all set by the software, and are very easy to change to suit other applications and user preferences. These settings are all very clearly highlighted in the source code. The DDS requires a 40-bit serial word transfer from the microprocessor. As the encoder is rotated, the DDS frequency is updated, the new frequency displayed and the dial graphics dynamically changed according to the direction of tuning knob rotation. The 40-bit word sent to the DDS is calculated from a series of predetermined lookup values, one for each digit in the 7-digit frequency of the VFO, the values depending on the DDS clock used. In this case, they assume an 80MHz clock, the highest frequency crystal Fig.9: soldering that SMD-mount chip requires a steady hand and a fine iron (see the SMD article in this issue!) siliconchip.com.au oscillator I could buy locally. The DDS output is filtered using a 5th order elliptical low pass filter with a cutoff frequency of about 35MHz. The output from the filter is then amplified with a ERA-4 surface mount MMIC. This gives a output level of about 1V peak-to-peak or +13dBm into 50W from the VFO, ideal for diode mixers. Since the DDS output level follows a sinx/x envelope, the output reduces to 0.8V peak-to-peak by 30MHz. This 2dB rolloff is of little concern in transceiver applications but should be borne in mind if this software is used for signal generator applications. The 80MHz DDS oscillator is the reference for the VFO’s output frequency. By contrast, the microprocessor crystal is a nominal 8MHz crystal and, as noted earlier, its exact frequency is not critical. Since output frequency accuracy and stability depends on the 80MHz DDS oscillator (and few of these have any external frequency adjustments available), any users requiring absolute output frequency accuracy can make the simple frequency alignment adjustments within the software. I found my VFO was accurate to a few hundred Hertz and quite adequate for my uses. The Nokia 3310 LCD module requires a 3.3V supply. While some 8051 chips will operate on the same 3V supply, the 80MHz oscillator demands a 5V supply. The decision was therefore made to run both a 5V (for micro and oscillator) and a 3.3V rail for the LCD. It’s a slight additional complexity but makes the design easier to convert to other types of 8051 chips should this prove desirable. The interface between the AT89C4051 and the display, necessary due to the different supply rails on these parts, is handled with three cheap isolating diodes. If you are able to purchase some 3.3V clock oscillators (a standard part but one I couldn’t buy locally), you can easily modify the entire VFO for single supply rail operation. The microprocessor interface for the LCD module uses fewer control lines than suggested in many references. Most suggest the need for five lines, including a reset line from the microprocessor. Careful reading of the datasheet revealed that the chip select (CS) line can be permanently tied to ground at the cost of a little more current. The VFO’s MMIC amplifier is fairly siliconchip.com.au Figs.10 & 11: here’s the full size artwork for both sides of the PC board with the top (ground plane) at right. We imagine most constructors will not bother etching a second layer (if they can!) but will simply remove the top-side copper around the holes with a small twist drill (eg, 5mm). It’s tedious but easy enough to do holding the drill in your fingers, putting the tip in the hole and twisting. The smaller holes in the ground plane are for the components which solder to both sides of the board – these should not be opened out. greedy, drawing around 65mA, so the modest constant 5mA consumed by the always-on LCD turned out to be of little concern. The datasheet also suggested the possibility of using a resistorcapacitor reset arrangement (10kW and 4.7mF), and that saved a further I/O pin. As a result, there is an additional delay of a hundred milliseconds or so at power-up, just to be sure the display has reset but this is of little importance in overall operation. The main dial knob uses connects to an optical encoder. This is interfaced to the microprocessor with an LM393 comparator to ensure clean rising and falling quadrature signals. The use of an optical encoder delivers improved long term reliability and allows users to set up the mechanics of the dial knob to suit individual taste. Construction The VFO can be built either as a single PC board measuring about 150 x 50 x 15mm (wxhxd) or in a sandwiched two-PC board configuration measuring 100 x 50 x 25mm (wxhxd). Those wanting a smaller version can convert the current layout to use SMD March 2008  63 Parts List – DDS VFO 1 double-sided PC board, 150 x 50mm, coded 06103081 (see text) 1 digital display ex Nokia 3310 cellular phone (see text) 1 surplus mechanical (ball-type) mouse for optical encoder parts (containing 1 LED and 2 phototransistors – see text) 1 8.866MHz crystal (X1) 6 PC mounting SPST pushbutton switches Semiconductors 1 LM393 (IC1) 1 AT89C4051 microcontroller (IC2) 1 80MHz oscillator (IC3) 1 AD9850 (IC4) 1 ERA4 (IC5) 1 7805 5V positive voltage regulator (REG1) 1 LM317LZ voltage regulator (REG2) 3 1N4148 silicon signal diodes (D1-3) 1 yellow LED 1 green LED Capacitors 1 10mF 16V PC electrolytic 3 10mF 10V PC electrolytic 1 4.7mF 10V PC electrolytic 1 1mF 10V PC electrolytic 7 100nF polyester 1 150pF polyester 2 100pF polyester or ceramic 1 33pF ceramic 2 22pF ceramic 1 10pF ceramic Inductors 1 390nH (L1) 1 330nH (L2) 4 100mH (RFC1-4) (code 0.1, 100n or 104) (code 150p or 151) (code 100p or 101) (code 33p or 33) (code 22p or 22) (code 10p or 10) (13T 33SWG ENCU on T25-10 toroidal former) (12T 33SWG ENCU on T25-10 toroidal former) Resistors (all 0.25W, 1%) 1 22kW 12 10kW 1 470W 2 330W 1 3.9kW 1 120W parts and reduce the dimensions by about 40%. While the present design uses a double sided PC board, the top side of the board is left unetched, forming a continuous copper ground. This allows the PC board to be etched in typical home workshops with ease as if it was a single sided PC board. That’s the method I used for the version pictured. While I’ve used standard components as far as possible, construction is not for the faint-hearted. The DDS chip, for example, is a 28 pin SMD device with very close pin spacing. The display connections are also challenging. Time and care allows both to be soldered into place but it does require a good soldering iron with a fine tip, steady hands, patience and good eyesight. I’d suggest building the keyboard/ 64  Silicon Chip 1 1kW 1 100W 1 560W 1 56W display PC board first. Install the jumpers first, the resistors, then the buttons, and finally mount the display. The Nokia 3310 display is supplied mounted on a plastic keypad frame assembly complete with speaker. Prise out the speaker – it’s just pressed into a rubber ring – and trim the surplus plastic away with a sharp knife, being careful not to disturb the plastic around the display itself. This is essential to maintain slight compression on the metallic springs which press onto the conductive tracks on the LCD glass. The display is then wired to the pads on the PC board. I was tempted to lay the PC board out to permit the display to be directly mounted on it but the current method offers a little more flexibility. However, it does require some delicate soldering of wire jumpers between the spring metal connections on the rear of the display and the PC board. I kept everything in place with a few dabs of hot glue and the display assembly was mounted a few millimetres off the PC board with three further strategic dabs of hot glue. This sounds crude – but it’s unseen and the glue forms a very rigid arrangement which can be easily adjusted with a little heat from a soldering iron. The display is extremely light, and the resulting mounting is very robust. There is also space beneath the LCD for the addition of backlighting, perhaps using some diffused LEDs, if desired, although the current PC board layout does not allow for component wiring. By the way, don’t be tempted to remove the white plastic material from the rear of the LCD. This improves display contrast and aids backlighting. I tried some green LEDs for backlighting and they worked very well, so I may add these to the final transceiver. An extra pullup resistor (10kW) can be seen in Fig.5 mounted next to the inter-PC board wiring on the top side of the keyboard/display PC board. This was caused by a minor change in pin connections when going from my Veroboard and wirewrap prototype to the final PC board version. This resistor IC1 PIN 1 IC1 PIN 7 ENCODER OUTPUTS WITH POSITIVE (CLOCKWISE) ROTATION IC1 PIN 1 IC1 PIN 7 ENCODER OUTPUTS WITH NEGATIVE (ANTICLOCKWISE) ROTATION Fig.12 : quadrature outputs from an optical encoder are used to tune the DDS. siliconchip.com.au siliconchip.com.au 54 95 28 59 8 44 Notes: 38 40 1. Red lines and dimensions in red text indicate details specific to the DDS VFO. All other dimensions may be varied to suit specific applications. 2. Panel material should be removed from the shaded area. 3. Dotted lines show outlines of LCD display and other panel-mounted components Fig.13 : same-sized diagram of the front panel of the transceiver on P58 showing where the VFO mounts. 4. All dimensions are in mm 40 21 54 28 has now been added to the PC board layout shown in Figure 8 and 9. Constructing the DDS/microprocessor PC board can start with the installation of the resistors and capacitors. Then proceed to add the jumpers and the various through-PC board connections if your board does not have plated-through holes. Mount the microprocessor socket (I strongly recommend using a “machine screw” IC socket for non-plated through PC boards), the LM393, crystal oscillator and crystal. The LM393 does not need a socket. Complete the board by soldering in the DDS chip and the ERA-4 MMIC. The optical encoder should be added next. Although you can use a commercial model, I made my optical encoder from parts salvaged from an old PC mechanical-type mouse. It’s not a difficult task – there are enough bits inside an old mouse for two such encoders. It is possible to monitor the two output pins of the LM393 interface to confirm correct quadrature waveforms using an oscilloscope (See Fig.12) while rotating the encoder. If you test without the microprocessor installed, which is best, you will need to add temporary pullup resistors on each open-collector comparator output. Any value from 4.7kW to 100kW works fine for testing. Remove these once encoder testing is complete. Fig.12 shows the ideal waveforms. Actual outputs have less perfect shapes, with variable width and timing but still do the job. The LCD module and pushbuttons are mounted on the solder side of the PC board. This allows the board to be mounted at the ideal distance from the front panel for display visibility and for the buttons to be depressed through a Lexan or similar flexible keypad/panel. Since my workshop facilities doesn’t run to Lexan production facilities, I made a workable flexible front panel from transparent plastic stick-on film from the local stationery shop and a laser-printed paper panel overlay. Unfortunately, my panel layout is too long to be printed here but it can be downloaded from my website (see references) or from www.siliconchip. com.au The film is layered over the paper on both sides and provides protection for the display while allowing the March 2008  65 buttons to be easily pressed under the appropriate keypad label. This panel will obviously wear out much faster than Lexan but it’s cheap and easy to make and replace. There are two indicator LEDs on the PC board. The green LED shows when DC is applied to the board and can be used as a power indicator (Top left hand corner of the front panel in Fig.10). The yellow LED was used during the software development to measure the time taken by the main software loop. It still does, changing state each time through the loop, flickering in varying degrees of brightness as buttons are pressed, the VFO is tuned, and the LCD updated. I located this LED at top dead centre over the main tuning knob. Yes, I confess, it’s purely for there for show, so just omit it if you don’t like it. The two PC boards are connected together using a total of 12 short wire links. There is a further short wire jumper which is run between the two boards for the +12V supply. This goes to the 120W resistor to power the MMIC. Operation With an 80MHz DDS clock, the VFO will operate with minimal spurious outputs up to about 30MHz. In transmit mode, the DDS VFO outputs the frequency displayed on the LCD. In receive mode, the receiver IF offset is added to the displayed output frequency until the actual DDS output frequency exceeds about 30MHz. At that point, the IF offset is subtracted from the nominal output frequency to keep spurious products to an acceptable minimum. The VFO keys have the following functions: LINE FUNCTION 1 Reserved for a 14 character string of text including the user’s callsign 2 Digital display of VFO frequency 3 Used by the VFO cursor which indicates the step size currently in use 4 Analog dial display 5 RIT frequency (Only shown in RIT mode) 6 Status messages including VFO lock, VFO A/B selection, and Tx mode Line 1 is the top-most LCD line. Incidentally, lines in the software are actually numbered from 0 to 5 to match the LCD controller’s addressing scheme. addresses the display using this linebased mode as shown above. Also mentioned earlier, the VFO has three tuning speeds, selected by the Step key. Some consideration was given to adding variable rate tuning to this VFO. This method is used on some commercial transceivers. As the dial is rotated more quickly, for example, the tuning rate will initially directly match the increased rotation speed. Then, if the tuning rate is sustained, the VFO frequency increment will be automatically increased, resulting in accelerated tuning, with the frequency being incremented at a much faster rate. When the dial is slowed, this is detected and the tuning rate switches to a slower rate. Having used it in one of the commercial transceivers I own, I’ve not found it particularly pleasant to use. Call me old-fashioned but I prefer the standard fast/slow tuning speed selection used in one of my older commercial transceivers. I did try a variety of variable rate methods during the development of this design but none really proved to offer any benefits over the scheme finally adopted. So, variable rate tuning VFO KEY FUNCTIONS: Step Selects VFO frequency increment (10Hz, 100Hz or 1kHz steps) Band Selects desired band (160m, 80m, 60m, 40m, 30m, 20m, 15m, 12m, 10m) RIT Changes dial to RIT control allowing the receiver frequency to be offset by ±5kHz in 10Hz steps VFO A/B Selects one of two independent VFO frequency banks Lock Locks the VFO frequency to the currently selected DDS output frequency Tx Removes the receiver IF and RIT offsets from the VFO output frequency As mentioned earlier, the LCD is addressed as a 6-line display, each 8 pixels high and 84 pixels wide. This is determined by the LCD controller chip bonded inside the Nokia 3310 display, a Philips PCD8544 or equivalent. The DDS VFO software therefore 66  Silicon Chip is not a standard feature in this VFO. Construction Options The split PC board layouts used in this design readily permit the use of other keypads and displays. In such cases, only the DDS/microprocessor board need be built. The relevant port lines are all available on the edge of this PC board. With minor changes in software, those standard two-line x 16 character alphanumeric LCD modules may be used, as may many different keypad arrangements and keypads. In most such cases, the software will readily fit in the smaller AT89C2051 (2K flash ROM) microprocessor which is 100% pin-compatible with the DDS/microprocessor board layout shown here. If there is sufficient interest, I will make schematics, connection details and software available on my website for this alternate version. Future Development Now that this design is complete, I want to find some time to build an RF signal generator using the more powerful AD9854 or AD9912 DDS chips. These DDS devices have higher quality quadrature outputs and are ideal for use with software-based receivers. Interestingly, a simple signal generator actually requires much less code than a ham-band transceiver VFO. But to compensate for this, I’d like to use one of the more complex full-colour cellular phone LCD modules. All I have to do is persuade my wife to let me borrow her new cellphone for a few minutes… SC References 1. The ZL2PD website can be found at www.zl2pd.com This contains all of the source code, assembled hex files, full size schematics and PCB artwork for free downloading 2. Analog Devices, ‘A Technical Tutorial on Digital Signal Synthesis’, 1999 (See www. analog.com) 3. Two websites offering Nokia 3310 LCD displays at time of writing include www.jelu. se and gsmserver.com, although I have no experience with either source. siliconchip.com.au