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• Realistic stereo performance • Low noise and distortion • Adjustable stereo effects • Runs from a 12V plugpack A high-performance stereo simulator This high performance stereo simulator uses a digital delay chip to convert any mono signal source into stereo. You can use it to enhance the sound from mono VCRs, AM tuners or electronic musical instruments. By JOHN CLARKE If you compare the sound from a mono source to that of stereo the difference is easily perceived. Instead of appearing to come from a single point, the sound is dispersed over a wide field between the stereo speakers. Very few recordings these days are made 14  Silicon Chip with ping pong ball effects whereby the sounds bounce from one channel to another and back again. Because of this, attempting to simulate stereo sound is a reasonably straightfor­ward design exercise. In the past, the usual approach to producing a simulated stereo effect was to divide the mono signal into separate fre­ quency bands and distribute these into the left and right chan­nels. This frequency division was done by an array of filters which rejected certain bands in the audio spectrum for one chan­ nel but allowed them through for the other channel. The real drawback to this approach is that you need a fair few filters for a good result. Another method was to use bucket brigade delay chips but these are quite expensive, have high noise and distortion and the overall result is mediocre. So how have we gone about it? Our task has been made easier by Dolby surround decoders which require high-performance digital delay chips. We have used one of these devices and the results are very good. How it works In essence, we use the delay chip to provide a “comb filt­er” effect. This chops the incoming audio signal into lots of very narrow frequency bands. The narrow frequency bands are subtracted from the mono signal and the result becomes the left simulated channel. The difference between the simulated left channel and the incoming mono signal then becomes the right simulated channel. Fig.1 shows the general arrangement of our stereo simula­tor. It has an input buffer IC1a and this feeds the delay chip IC2. It also drives one input of mixer IC1d while the delay chip drives the other input. The output of mixer IC1d becomes the right channel. For the left channel, the delay chip drives inverter IC1c and its output is mixed with the input mono signal before mixing with the buffered output mono signal in IC1b. This process of mixing a signal with an identical delayed version results in some frequencies being “in phase” and these pass through without attenuation. Other frequencies are cancelled out because they are “out of phase”. If the delay chip is set at 1.5 milliseconds, for example, the input signal will be in phase with the delayed output at 666Hz (1/1.5ms), 1.333kHz, 1.999kHz and so on. Thus, these fre­ quencies will pass through to the right channel. For the left channel, the inverted signals are out of phase at 666Hz, 1.333kHz and so on and these frequencies will coincide with a dip in the response. Conversely, signals at 333Hz, 999Hz, 1.666kHz, etc will pass through to the left channel but will have dips in the right channel. Fig.2 shows the frequency response for the left and right chan­nels. The solid curve is the right channel while the dotted curve is the left channel. Note that the notches at the lower frequencies (333Hz, 666Hz, 999Hz, etc) are very deep while at higher frequencies the notch depth becomes progressively less. Looking at the responses of Fig.2, it is easy to see where the term “comb Fig.1: the stereo simulator has an input buffer (IC1a) and this feeds the delay chip (IC2). The delayed signal is then mixed with the buffered input signal to produce the right channel. The left channel is produced by mixing an inverted delay signal with the buffered input signal. filter” came from – all those notches look like the teeth of a comb. Mind you, Fig.2 shows just one possible set of frequency responses. It corresponds to a delay setting of 1.5ms. You can also select delays anywhere between 0.5ms and 4ms, in steps of 0.5ms, and each of these settings will have its own characteristic “comb filter” effect. Circuit description We have used the M65830P digital delay IC from Mitsubishi as the heart of the circuit. This is the same delay chip as used in the Dolby Pro Logic Surround Sound Decoder, as published in the November & December 1995 issue of SILICON CHIP. The delay chip works by first converting the incoming analog signal to a digital format which is then clocked into memory. This digital signal is then clocked out at the end of the delay period and converted back to an analog form. The chip is timed by a 2MHz crystal oscillator to provide a 500kHz sampling rate. In the Dolby Surround Sound Decoder, we used a microproces­sor to control the delay AUDIO PRECISION STEREO AMPL(dBr) & AMPL(dBr) vs FREQ(Hz) 0.0 21 MAR 96 12:18:53 0.0 -5.000 -5.00 -10.00 -10.0 -15.00 -15.0 -20.00 -20.0 -25.00 -25.0 -30.00 -30.0 -35.00 -35.0 -40.00 -40.0 20 100 1k 10k 20k Fig.2: these “comb filter” effects are the frequency response curves for the left and right channels. The solid curve is the right channel while the dotted curve is the left channel. June 1996  15 16  Silicon Chip chip but in this circuit we use three low cost CMOS ICs. These are required because the M65830P gets its delay setting instructions each time it is powered up. The full circuit of the Stereo Simulator is shown in Fig.3. The mono input signal is AC-coupled into unity gain buffer IC1a via a 2.2µF capacitor. IC1a then drives mixers IC1b & IC1d and the delay chip, IC2. The signal to IC2 is AC-coupled to its pin 23 via a low-pass filter comprising the 39kΩ and 18kΩ resistors and the 560pF and 150pF capacitors. This filter rolls off signals above about 15kHz to prevent higher frequencies affecting the digital conversion and causing spurious effects in the output. The capacitors at pins 17, 18 and 20 control the rate of delta modulation which is the type of analog to digital conversion used in IC2. Similarly, the .068µF capacitor at pin 16 controls the digital to analog conversion output signal appearing at pin 15. This output is applied to another 15kHz filter comprising two 39kΩ resistors, an 18kΩ resistor and 560pF and 150pF capacitors. The output of IC2 is then AC-coupled to inverter IC1c and mixer IC1d via a 4.7µF capacitor. IC1b & IC1d mix the signals applied to their inverting inputs via 10kΩ resistors. Their outputs at pins 1 & 7 become the left and right simulated stereo channels. All four op amps in IC1 are biased to +6V by a voltage divider consisting of two 10kΩ resistors across the 12V supply rail. Delay selection IC2’s delay is controlled by CMOS chips IC3-IC6. Each time IC2 is powered up it automatically resets itself to provide a 20ms delay. This is much too long for this application so we need to set it by feeding a serial data stream to the Data input at pin 6. This data is Fig.4: taken from a Tektronix TDS360 200MHz digital scope, this printout shows the timing of the SCK (top), Data, (serial clock) and REQ (request) lines to IC2. This data is sent once to the delay chip each time it is powered up. clocked in at each negative transi­tion of the SCK input and accepted on the rising edge of the REQ input. The serial data stream must include various mute, sleep and address codes as well as the delay information before IC2 will respond. Fig.4 shows the timing of the Data, SCK (serial clock) and REQ (request) lines to IC2. What happens is that when the REQ line goes low (lower trace), the serial data block (centre trace) can be clocked in. In the time that the REQ line is low, there are 12 clock pulses and these clock in the respec­tive data levels. Our data line shows two positive pulses in the data line but this is not the case as the data stream actually contains 12 separate codes which can be high or low. On the first clock pulse, the sleep data is fed in and this must be a low. The following six codes are for delay selection while the next three are the low mute, ID1 and ID2 (identification codes). The last two codes are high for the ID3 and ID4 identifi­cation signals. For the ID4 code to be valid, pin 7 of IC2 must be also high. With all this data complexity, it is easy to see why a microprocessor is the most elegant solution in Dolby Prologic decoders, particularly when it can provide a lot of other functions as well. IC5, a 74HC165 serial shift register with parallel load inputs, is used to supply the first eight bits of data. This has the advantage that the data can be initially set by parallel load inputs (inputs A-H). The E, F and G inputs are con­nected to a DIP switch to allow Performance Frequency Response................. (see graphs) Fig.3 (left): the heart of this circuit is the Mitsubishi M65830P digital delay chip. Each time it is powered up it needs a stream of serial data to set its delay time. It can be set for between 0.5ms and 4.0ms using a DIP switch (see Table 1). Once data has been sent to IC2, CMOS chips IC3, IC4 and IC5 are effectively out of circuit. Signal-to-Noise Ratio................. 96dB unweighted (22Hz to 22kHz); -100dB ................................................... A-weighted, with respect to 1V RMS. Harmonic Distortion................... <0.5% at 1kHz and 1V RMS Maximum Input Signal................ 1.2V RMS Output Level............................... 0-1V RMS Delay Options............................. 0.5-4ms in 0.5ms steps June 1996  17 Above: bird’s eye view of the Stereo Simulator – there is not much wiring to be done. Note that shielded cable is used for the connections between the board and the RCA sockets. Another view of the assembled PC board, prior to installation in the case. Take care to ensure that all ICs are correctly oriented. 18  Silicon Chip the delay to be selected. IC3 and IC4 are used to control IC5. IC3 is a 4060 binary counter which has its own oscillator, set by the components connected between pins 9, 10 & 11. IC3 supplies the clock signal for IC2 at its Q4 output. Its Q5 output at pin 5 is inverted by IC6a to drive IC4, a 4022 divide-by-8 counter which has eight outputs, O0 to O7. We use the O1 output to drive the serial input of IC5. Finally, we use the QH output of IC5 to drive the data input of IC2. When the “6” output of IC4 goes high after 12 counts of SCK, IC3 is reset, the REQ line goes high and IC5 is set into the load position with a low pin 1. At power up, the 47µF capacitor at the input of Schmitt NAND gate IC6b is high and its output is low. When the capacitor charges, the pin 3 output goes high to apply a short positive pulse to the reset input of IC4 via the .001µF capacitor. This resets IC4 and the code is fed to IC2. The resultant waveforms are shown PARTS LIST 1 PC board, code 01406961, 100 x 100mm 1 plastic case, 111 x 45 x 140mm, Arista UB14 1 front panel label, 95 x 33mm 1 rear panel label, 95 x 33mm 1 12VAC 300mA plugpack 1 SPDT toggle switch (S1) 1 4-way DIP switch (DIP1-DIP3) 1 2MHz crystal (X1) 3 panel mount RCA sockets 1 insulated panel mount DC socket 1 5mm ID rubber grommet 1 400mm length of hook-up wire 1 150mm length of shielded cable 1 250mm length of tinned copper wire 7 PC stakes Semiconductors 1 TL074, LF347 quad op amp (IC1) 1 M65830P digital delay (IC2) 1 4060 binary counter (IC3) 1 4022 divide by-8 counter (IC4) 1 74HC165 8-bit shift register (IC5) 1 4093 quad 2-input Schmitt NAND gate (IC6) 1 7805 5V regulator (REG1) 1 7812 12V regulator (REG2) 1 1B04 bridge rectifier (BR1) 1 1N914, 1N4148 signal diode (D1) 1 3mm red LED (LED1) Fig.5: the parts layout and wiring diagram for the Stereo Simula­tor. Note that the input and output leads are wired in shielded cable. in Fig.4, as previously discussed. Note that once the “6” output of IC4 goes high, it also pulls the reset line of IC3 high and this stops any further data being sent. Thus, IC3, IC4 and IC5 serve no further purpose until the circuit is powered up the next time. That completes the circuit description except for the power supply. This uses an AC plugpack fed to a bridge rectifier (BR1) and a 470µF filter capacitor. A 12V regulator supplies power for the op amps in IC1 while a 5V regulator supplies the rest of the circuit. Construction Capacitors 1 470µF 16VW PC electrolytic 3 100µF 16VW PC electrolytic 2 47µF 16VW PC electrolytic 5 10µF 16VW PC electrolytic 2 4.7µF 16VW PC electrolytic 1 2.2µF 16VW PC electrolytic 3 0.1µF MKT polyester 2 .068µF MKT polyester 1 .012µF MKT polyester 1 .001µF MKT polyester 3 560pF MKT polyester or ceramic 2 150pF ceramic 2 100pF ceramic Resistors (0.25W 1%) 1 1MΩ 11 10kΩ 1 100kΩ 3 4.7kΩ 4 47kΩ 1 2.2kΩ 4 39kΩ 3 100Ω 1 22kΩ 1 33Ω 2 18kΩ 1 10Ω The Stereo Simulator is assembled June 1996  19 A view of the Stereo Simulator with the top removed and showing the inside of the rear panel. onto a PC measuring 100 x 100mm and coded 01406961. Our prototype was housed in an Arista UB14 plastic case measuring 111 x 45 x 140mm. Self-adhesive labels, were fitted to the front and rear panels. The full wiring details and component overlay for the PC board are shown in Fig.5. You can start construction by checking the PC board against the published pattern of Fig.6. Fix any broken tracks or shorts that may be evident. Now insert the ICs, diode, resistors and links in the locations shown. Take care with the orientation of the ICs, noting that IC1 is oriented differently to the others. DIP Switch Settings DIP1 DIP2 DIP3 Delay Freq. on on on 0.5ms 2kHz on on off 1ms 1kHz on off on 1.5ms 666Hz on off off 2ms 500Hz off on on 2.5ms 400Hz off on off 3ms 333Hz off off on 3.5ms 285Hz off off off 4ms 250Hz The accompanying resistor colour code chart should be used when selecting each resistor value. Alternatively, This DIP switch can be used to change the delay chip’s setting and thus the stereo effect. Use Table 1 at left to set the DIP switches. use a digital multi­meter to measure each resistor before it is fitted into the board. RESISTOR COLOUR CODES ❏ No. ❏  1 ❏  1 ❏  4 ❏  4 ❏  1 ❏  2 ❏ 11 ❏  3   ❏  1 ❏  3 ❏  1 ❏  1 20  Silicon Chip Value 1MΩ 100kΩ 47kΩ 39kΩ 22kΩ 18kΩ 10kΩ 4.7kΩ 2.2kΩ 100Ω 33Ω 10Ω 4-Band Code (1%) brown black green brown brown black yellow brown yellow violet orange brown orange white orange brown red red orange brown brown grey orange brown brown black orange brown yellow violet red brown red red red brown brown black brown brown orange orange black brown brown black black brown 5-Band Code (1%) brown black black yellow brown brown black black orange brown yellow violet black red brown orange white black red brown red red black red brown brown grey black red brown brown black black red brown yellow violet black brown brown red red black brown brown brown black black black brown orange orange black gold brown brown black black gold brown CAPACITOR CODES ❏ ❏ ❏ ❏ ❏ ❏ ❏ ❏ Value IEC Code EIA Code 0.1µF   100n   104 .068µF   68n   683 .012µF   12n   123 .001µF   1n   102 560pF   560p   561 150pF   150p   151 100pF   100p   101 Seven PC stakes will need to be fitted to the board. This done, insert and solder in the capacitors taking care to orient the electrolytics with correct polarity. Next, fit the 3-terminal regulators and make sure you insert the 7812 (REG2) into the location nearest LED1. Insert the DIP switch, crystal and bridge rectifier. The LED is mounted without shortening its leads and is bent over at right angles to insert into the front panel hole. The PC board is fitted into the case and secured with four self-tapping screws into integral standoffs in the base. Affix the adhesive labels to the front and rear panels and drill out the holes for the power switch and LED on the front panel and for the RCA sockets and DC socket on the rear panel. A 3mm hole is required for the LED. Note that the DC socket must be insulated from the metal rear panel to prevent shorting the AC plugpack to ground. On our prototype, we fitted the DC socket inside a 5mm ID grommet and then secured it with a nut after shaving the grommet thinner with a sharp utility knife. After fitting the front and rear panels, the final wiring can be done. Use short lengths of shielded cable for the input and output connections. The connections from the DC socket to the switch and PC board are made with hook-up wire. Apply power and use a multimeter to check that pin 4 of IC1 is at +12V. Pin 16 of IC3, IC4 & IC5, pin 14 of IC6 and pin 24 of IC2 should all be at +5V. If the LED does not light, it is probably connected the wrong way around. Testing To test the Stereo Simulator, connect the mono input to the mono output of your VCR and the stereo outputs Fig.6: actual size artwork for the PC board. + STEREO SIMULATOR POWER + + + + + 12VAC INPUT MONO INPUT LEFT OUT RIGHT OUT Fig.7: these full-size artworks can be used as drilling templates for the front and rear panels. to the left and right inputs on your amplifier. This done, set DIP1, DIP2 and DIP3 on, apply power and listen to the stereo effect. Now set DIP 1 off and switch off the power. Reapply power after about 10 seconds and check that the stereo effect has changed. If that is the case, the circuit is working correct­ly and you can experiment with the delay settings. Table 1 table shows the delay versus frequency bands for various settings of DIP1-DIP3. We found that the most satisfying stereo effect was obtained with the delay set to either 2ms or 2.5ms. SC June 1996  21