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A Look At The 68000 Microprocessor RO UN DE DG E 0 HB By ELMO JANSZ The 68000 microprocessor is manufactured by Motorola & made its debut in about 1979. It is a 16-bit device & was designed to supersede the earlier 8-bit 6800. It is widely used in Apple Macintosh & Atari machines. Over the years, the amount of hardware and software acces­sories available for this device has grown rapidly. From the 68000, a family of devices has now come into existence such as the 68010, 68020, 68030 and the 68040. In this article we shall confine discussion to the 68000. From this point onwards we shall refer to the microproces­ sor as the MPU. The 68000 comes in a 64-pin package which elimi­ nates the need for multi-function pins and simplifies interfacing with external hardware. It has a 32-bit internal architecture, which includes 16 internal general purpose registers, each 32 bits wide. Eight of these are data registers and the rest are address registers. The data and address registers do not have dedicated func­tions such as an accumulator, which was so with the 6800. In­structions can be written 58  Silicon Chip so that operands reside in any of the data registers or storage locations in external memory. The MPU can handle a bit, a byte, a word or a long word of data. A bit is one binary digit, a byte is eight binary digits, a word is 16 binary digits, and a long word is 32 binary digits. The MPU has 23 address lines, giving it access to a very large range of addresses in external memory. It also has access to a user/supervisor environment which provides for multi­pro­ cess­­ing and multitasking activities; ie, the ability to handle more than one task at a given time. Interface buses Fig.1 is a block diagram of the MPU showing its interface buses. Buses are groups of pins or lines and these come under the following headings: Address, Data, Asynchronous Control, Proces­sor Status, System Control Bus/ Function Codes, Interrupt Control, Arbitration Control and Synchronous Control. Let’s examine each of these in turn. The address bus: the MPU has a 23bit address bus. Lines A1 to A23 are used to address memory and input/ output devices. A0 is not shown as it is internal to the device and is used to deter­mine whether the upper or lower byte of a word is to be used when processing byte size data. The data bus: labelled D0-D15, this bus is bidirectional and can be used to read/write data. Byte size data can be transferred on either half of the bus, while word transfers use both halves. The asynchronous control bus: the MPU uses asynchronous bus control. This means that once a bus cycle (ie, a procedure) is initiated, it is not completed until a signal is returned from external memory. Five signals are available to control address and data transfers. These are: (1) Address strobe (AS-bar) (2) Read/write (R/W-bar) (3) Upper data strobe (UDS-bar) (4) Lower data strobe (LDS-bar) (5) Data transfer acknowledge (DTACK-bar) The MPU has to indicate to external devices when an address is available and whether a read or write operation is to take place. The AS-bar and R/W-bar signals perform this activity. When a valid address is placed on the address bus, the AS-bar line is pulsed low. The R/W-bar indicates whether a read or a write is to com­mence. When the MPU reads data from the data bus, R/W-bar is pulsed high. When data is written to memory or to an output device, R/W-bar is pulsed low. The asynchronous bus cycle re­quires external memory to signal the MPU when the cycle is com­pleted. The DTACKbar input provides this. During a read cycle a low on DTACK-bar indicates to the MPU that valid data is on the bus. The MPU reads, latches the data, and completes the cycle. During a write operation, DTACKbar informs the MPU that data has been written to memory or an output device. The UDS-bar and the LDS-bar are called the upper and lower data strobes respectively, and indicate whether a byte or word of data is on the data bus. A low on UDS-bar indicates a data transfer on the upper eight lines of the data bus. A low on LDS-bar indicates a transfer on the eight lower data lines. Table 1 shows the logic levels possible for each type of data transfer. Bus function codes: during a bus cycle, the MPU outputs a 3-bit status code on FCO, FC1 and FC2. These are called the bus func­tion codes and these inform external devices what type of bus cycle is in progress. They indicate whether data or program is being accessed and whether the MPU is in the user or supervisor state. The codes are output at the beginning of each read or write cycle and continue to be valid until the next read or write cycle commences. System control bus: this bus is comprised of the three lines BERR-bar, HALT-bar and RESET-bar. BERR-bar is an input to the MPU to inform it that there is a problem with the current bus cycle, while the HALT-bar signal is used to stop the MPU. An external signal applied to this line stops it at the completion of the current cycle. HALT is bidirectional and when an instruction execution is terminated, external devices are informed of the fact using this line. RESET-bar is used for initialisation with a signal from ADDRESS BUS VCC(2) A1-A23 ADDRESS/ DATA GND(2) CLK DATA BUS D0-D15 FC0 PROCESSOR STATUS MC68000 PERIPHERAL CONTROL (SYNCHRONOUS CONTROL) FC1 FC2 MC68000 MICROPROCESSOR R/W UDS E LDS VMA ASYNCHRONOUS BUS CONTROL DTACK VPA BR BG BERR SYSTEM CONTROL AS BGACK RESET HALT BUS ARBITRATION CONTROL IPL0 IPL1 IPL2 INTERRUPT CONTROL Fig.1: this block diagram of the 68000 MPU shows all the various interface buses. These fall into various groups & the function of each group is explained in the text. external hardware, generally at power up. It is bidirectional but its output is software controlled. Interrupt control bus: this bus is comprised of three lines, IPLO-bar, IPL1-bar and IPL2-bar, and is used to service inter­rupts from external devices. In an interrupt routine, the MPU discontinues its current activities and services an external device. The external device provides a 3-bit code on these lines and this is compared with a mask value in the status register. Arbitration control bus: this bus is comprised of the three lines BR-bar, BG-bar and BGACK-bar. These signals are used for hand­ shaking activities that control transfer of the MPU’s system bus between devices. Hand­ shaking is the correct communication between devices so that information can be smoothly transferred between them. The device that possesses control of the bus at any time is called the Bus Master. Synchronous operation: the MPU has facilities for transferring data over the system bus in a synchronous manner. In a synchro­nous transfer, no acknowledgment is required from the receiving device before the next piece of information is transmitted. Three control signals are available for this function: Enable (E), Valid Peripheral Address (VPA-bar) and Valid Memory Address (VMA-bar). They are used to interface the MPU to much slower devices. Enable (E) provides a free-running clock 1/10th of the MPU clock frequency. For example, it could be used to interface the 10MHz MPU Table 1: Logic Levels For Each Type of Data Transfer UDS-bar LDS-bar R/W-bar 0 0 0 Word transferred to memory or I/O 0 1 0 High byte transferred to memory or I/O 1 0 0 Low byte transferred to memory or I/O 1 1 0 Invalid data 0 0 1 Word transferred to MPU 0 1 1 High byte transferred to MPU 1 0 1 Low byte transferred to MPU 1 1 1 Invalid data Comments 31 16 15 87 16 15 31 0 0 15 87 SYSTEM BYTE USER BYTE to a 1MHz external device. VPA-bar indicates to the MPU that it is to perform a synchronous data transfer over its asyn­ chronous system bus. Valid Memory Address (VMA-bar) is a signal produced by the MPU when VPA-bar goes active. It tells external equipment that a valid address is present on the address bus and that the next data transfer will be synchronised to the enable (E) line. Clock input: the block diagram shows a single clock input la­belled CLK. This signal is externally generated and fed to the MPU at frequencies between 4MHz and 12.5MHz. Internal registers The MPU contains 18 32-bit internal registers as depicted in Fig.2. Observe that there are eight data registers, seven address registers, two stack pointers, a program counter and a status register. The status register, unlike the others, is only 16 bits wide. The eight data registers are labelled D0 - D7 and are each 32 bits wide. The least significant bit is labelled B0 and the most significant bit B31. Each can work with a byte, a word or a long word of information. This information is generally referred to as the operand. Byte data always resides in the eight least significant bits, words in the least significant 16 bits and long words occupy all 32 bits. The size of the operand is specified in the instruction. Data registers can also be used as index registers. The value in the register represents an offset, which 60  Silicon Chip EIGHT DATA REGISTERS A0 A1 A2 A3 A4 A5 A6 SEVEN ADDRESS REGISTERS A7 TWO STACK POINTERS 0 USER STACK POINTER SUPERVISOR STACK POINTER 31 D0 D1 D2 D3 D4 D5 D6 D7 0 Fig.2: the MPU contains 18 32-bit internal registers as depicted here There are eight data registers, seven address registers, two stack pointers, a program counter & a status register. PROGRAM COUNTER STATUS REGISTER can be combined with the contents of another register to point to a data location. This facility is very useful in reading blocks of information. Address registers The address registers are labelled A0 to A7 and are also 32 bits wide. They do not store data but rather address information such as base and pointer addresses. There are two stack pointers called the user stack pointer (USP) and the supervisor stack pointer (SSP). Only one of these is active at any time and for this reason they are shown as a single register, A7. USP identifies the top of the stack in the user part of system memory. This is the section in memory where return addresses, (ie, when called upon to temporarily suspend its normal activities and attend to some other demand) are stored. Register data and other parameters are also saved in the stack. When in the supervisor state the user stack pointer becomes inactive and the supervisor stack becomes active. The address contained in the supervisor stack points to the top of a second stack called the supervisor stack. The supervisor stack is used for the same purpose as the user stack but it is also used by supervisor calls such as soft­ware exceptions, interrupts and internal exceptions. Exceptions are similar to interrupts. The procedure permits the MPU to respond to certain events, external or internal, by suspending its current activities and switching to a new program sequence. At the completion of the routine, the program is switched back to the point at which it left off in the main program. (The return address is stored in the stack before commencement of the new program sequence). The program counter The program counter points to the next instruction to be executed. It is automatically incremented by two when an instruc­tion is fetched. Although the PC is shown as composed of 32 bits, only the lower 24 are used. These can access 16M bytes or 8M words; ie, the address space can be considered to hold 16M bytes or 8M words. Word addresses are even and can have values from 00000016 through to FFFFFE16. Note that 1K = 1024 bytes and 1M = 1,048,576 bytes. The status register The status register is shown in Fig.3. Two bytes called the User byte and the System byte are shown. Each byte consists of a number of flags or condition codes. The carry flag, bit 0, is set when an add operation generates a carry out or a subtract (or compare) operation requires a borrow. During shift or rotate operations (ie, the movement of the bits of a piece of informa­tion), it holds the bit that is rotated or shifted out of a reg­ister or memory location. The overflow flag is bit 1. If an arithmetic operation on signed numbers (numbers that are represented as positive or negative quantities) produces an incorrect result, then the overflow flag is set; otherwise it is cleared. The zero flag, bit 2, is set when the result of an opera­tion is zero. A non-zero result clears the z flag. The negative flag, bit 3, depends on the sign bit; ie, the most significant bit of the result of an arithmetic logic, shift or rotate opera­tion. If this bit is 1 then the flag is set; otherwise it is cleared. The extend flag, bit 4, takes the same status as the C Flag, resulting from a shift or rotate operation. Let us now examine the system byte of the status register. It contains the bits that control the operational options of the MPU and the interrupt mask which was mentioned above. Bit 13 is used to distinguish between the user and super­visor states of operation. A logic 1 in this bit indicates that the MPU is operating in the supervisor state while a 0 indicates the user state. Trace Mode (T) The T bit (Trace mode) is used to enable or disable trace (Single Step) operation. It is active or not by setting or clear­ing bit 15. The entire contents of the Status Register can be read using software. Un-implemented bits are read as logic 0. The system byte can be modified only when the MPU is in the super­visor state. Addressing modes Addressing modes give information to the programmer on how to generate an address that identifies the location of the oper­and. The operand is the information being worked upon. We observed earlier that the MPU includes eight data registers and eight address registers. Data registers are used for storing usable data. Address registers, on the other hand, are used to access source or desti­nation operands residing in memory. The MPU can address a very large memory space, 16 megabytes in fact. The addressing modes available to the MPU can be classified under the following headings: (1) Immediate (2) Direct (3) Absolute (4) Address Register Indirect (5) Address Register Indirect with 16-Bit Displacement (6) Address Register Indirect with Index and 8-Bit Offset (7) Address Register Indirect with Post-Increment (8) Address Register Indirect with Pre-Decrement (9) Program Counter Relative with 16-Bit Displacement (10) Program Counter Relative with Index and 8-Bit Offset Let us examine each of these using only the MOVE instruc­tion which is available with all addressing modes. Immediate: in immediate addressing, the operand is included in the instruction. For example the operation “MOVE.W #$AABB,DO” moves the word $AABB into Data Register D0. The symbol # indi­cates that immediate addressing is to be used. The $ sign indi­cates hex-data. $AABB is the source operand. SYSTEM BYTE 15 T 13 S USER BYTE 8 10 I2 I1 I0 4 X N Z V 0 C TRACE MODE SUPERVISOR STATE INTERRUPT MASK EXTEND NEGATIVE CONDITION CODES ZERO OVERFLOW CARRY Fig.3: the status register. Two bytes called the user byte & the system byte are shown. Each byte consists of a number of flags or condition codes. For dealing only with bytes of data, a special form of immediate addressing called Quick Immediate addressing is avail­able. The instruction “MOVEQ #AA,D0” uses this form of immediate addressing to move the byte $AA into D0. Direct: Direct addressing is used only when one of the data or address registers contain the operand. If the register specified by the instruction is the data register, the addressing mode used is called Data Register direct. On the other hand, if the address register is specified, it is called Address Register direct. Consider the instruction “MOVE.W AO,DO”. The Move.W portion indicates that the word in A0 is to be moved into D0. A0 contains the source operand and D0 has the destination operand. The source operand uses address register direct addressing, while the destination operand uses data register direct address­ing. Both operands do not reside in external memory. Absolute: in the absolute addressing mode, the effective address of the operand is included in the instruction. There are two forms of absolute addressing, called absolute short and absolute long. Both forms are used to access operands residing in external memory. If absolute short addressing is used, a 16-bit address must be included as the second word of the instruction. This is the storage location of the operand in memory. Consider the instruc­tion: “MOVE.L $2345,D0”. It indicates that the long word commenc­ ing at address location $2345 is to be moved into the data reg­ister D0. The MPU does a sign extension based on the most significant bit of the absolute short address to give a 32-bit address. (Remember only 24 bits are used as the address bus is 24 bits wide). $2345 = 0010 0011 0100 0101 The most significant bit is 0. Extending it gives: 0000 0000 0010 0011 0100 0101 ie, the required address is $002345. Absolute short addressing generates an address correspond­ing to the first and last 32K bytes of the MPU’s address space. Absolute long addressing permits the use of a 32-bit number as the data address. The instruction “MOVE.L $02345, D0” has the same effect as the previous one, with the exception that the absolute address is specified with more than four digits. The source operand is now encoded by the assembler as an absolute long address using 32 bits instead of 16. Again, only 24 bits are actually used. The operand can now reside anywhere within the address space associated with the MPU. Address register indirect: in this form of addressing one of the address registers contains the address of the source or destina­tion operand. As an example, in the instruction “MOVE.L (AO), D0”, A0 contains the address of the source operand and must be enclosed in brackets. D0 is the destination operand. Execution of the instruction causes the long word at the address location pointed to by the contents of A0 to be copied into D0. Address Register Indirect With 16-Bit Displacement: this address­ ing mode uses a sign extended 16-bit displacement, which is added onto the contents of the address register to March 1995  61 generate the address of the operand. Consider the instruction “MOVE.W 10 (AO), D0”. 1010 is the 16-bit displacement. Since the displacement is 16 bits wide, the operand must be within +32K bytes of the memory contents pointed to by the address register. In Address Register Indirect addressing, the address of the operand is determined by adding the contents of an internal register and the signed 8-bit offset to the contents of the address register. The internal register serves as the index. For example, in the instruction “MOVE.W 12(A0, D0), D1” 1210 is the offset, A0 the address register and D0 the index register. These quantities are added to determine the address of the operand. Address Register Indirect With Post-Increment: this addressing mode is similar to address register indirect addressing. However, with post-increment, after the address is used, the contents of the address register are incremented by one, two or four depend­ ing on whether a byte, a word or a long word was accessed. Con­sider the instruction “MOVE.W #AABB,(A0)+”. We observe that the operand is to be placed in the address location pointed to by the address register. After the operation, the address register is automatically incre­ment­ed by 2, since the operand is a word. Address Register Indirect with Pre-Decrement: is similar to address register indirect with Post-Increment, except that the address register is first decremented by one, two or four depend­ing on whether a byte, word or long word is involved. Consider the instruction “MOVE.W #AABB, -(A0)”. The address register is first dec­ remented by 2 since a word is involved and the word $AABB is moved into the address indicated by the address reg­ister. Program Counter Relative with 16-Bit Displacement: in this mode, a displacement is used to indicate to the program counter how many bytes the data to be accessed is located away from its current position. When the instruction is executed, the MPU sign extends the 16-bit displacement to 32 bits and then adds it to the updated value of the program counter. Consider the instruction “MOVE.L Loc (PC), D0” which moves the long word starting at memory location with label Loc into D0. To do this the assembler calculates the number of bytes the updated value of the program counter is away from the address with label Loc. This value is expressed as a signed 16-bit binary number and is added onto the current value of the program coun­ter. Since 16 bits are used the operand lies within +32K bytes of the updated value of the program counter. Program Counter Relative with Index and 8-Bit Offset: this is similar to the addressing mode examined above except that both an index and an offset are used. The contents of an index register – any of the data or address registers, together with a signed 8-bit offset – are added to the updated value of the program counter to determine the address of the operand. Now consider the instruction “MOVE.W 6(Pc, D0), D1”. 610 is the 8-bit offset and D0 represents the index. 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