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COMPUTER BITS BY MIKE ZENERE A look at the 68705 microcontroller By using the right technology, lighting controllers, music synthesisers, keypad entry modules and burglar alarms can be custom designed with relative ease. Next month, we will feature a home burglar alarm based on the 68705P3 microcontroller, so let's take a look at what's inside this very versatile chip. The 68705P3 is a complete microcomputer on a chip. It contains CPU, EPROM, RAM, 20 pins of bidirectional I/O, a 15-bit interval timer and a clock. This circuitry is all contained in a 28pin package, with no external address or data buses. To make full use of the 68705P3's features, we have to understand its capabilities in both hardware and software terms. Fig.1 shows a block diagram of the MCU (Micro Control Unit). At the heart of the chip is the CPU (Central Processing Unit), which is made up of both a controller and an XTAL TIMER Prescaler ALU (Arithmetic Logic Unit). All executable instructions are decoded by the ALU under the direction of the controller. The 68705P3 has several types of memory, the first being 112 bytes of RAM (Random Access Memory). This may not seem like a large amount at first glance, but remember that this area is used to hold stack data and to keep track of variables. The second type of memory is ROM (Read Only Memory). This is not usable by the programmer under normal conditions but is implemented EXTAL Timer / 8 RESET INT Vpp Counter T1mer Control Accumul ator A 8 CPU Inde x Pon A 1/0 L,nes PAO PA1 PA2 PA3 PA4 PA5 PA6 PA7 8 Register Control Da ta 01 r Pon B Reg Reg X 5 Reg Regist er cc CPU Stack 5 Pointer SP Data OH Reg Progr am Cou nte r 1804 X 8 EPROM 115 X 8 8001s trap ROM The 68705P3 has 20 I/O (input/output) lines, all of which are programmable as inputs or outputs. These I/O lines are grouped into three ports: A, B and C. Ports A and B are both eight bits wide, while port C is only four bits wide. All three ports are TTL compatible and differ in the following way: port A lines, when in the input mode, float high due to internal pull-up resistors, whereas port B lines are capable of sinking l0mA of current. This means that LEDs may be driven directly from port B. · Along with each port is an associated DDR (Data Direction Register). The DDR operates under program control and is used to tell the port whether its associated bits are inputs or outputs. The clocking source for the processor is quite versatile, and there are four options available. Fig.2(a) shows how the unit can be PB0 clocked by an external PB1 Pon P82 source, while Fig.2(b) 8 PB3 1/ 0 PB4 shows how · the clock frePB5 Lines Code Dat a Q ,r Input/output PB6 PB? Condition Port A Reg when the program needs to be burnt into the on-board EPROM (Erasable Programmable Read Only Memory). The 1804 bytes of EPROM are used to hold the program on a permanent basis so that even if power is removed, the program is not lost. 3 High PCH Port C Reg ALU Program Coun1er 8 Low PCL 112 X B RAM PC0 PC1 PC2 PC3 Port C 1/ 0 Lines Fig.I: block diagram of the 68705P3 microcontroller. It contains a CPU, 1804 bytes of EPROM, 112 bytes of RAM & 20 programmable I/O lines. SEPTEMBER1992 37 ,rno,17 •r___n . : . . CLOC; u , --l__J c[],. .fi] (c) 27Pf~ .,. (d) Fig.2: the unit can be clocked by an external source (a) or by an on-board oscillator. The on-board oscillator frequency can be set by an external resistor (b); by a link (c); or can be crystal controlled (d). qu en cy can be set by an external resistor. Fig 2(c) shows how the on-board oscillator is selected. Finally, Fig.2 (d) shows how a crystal is applied between pins 4 & 5 to obtain an accurate clock signal. Returning to Fig.1 again, we can see that the processor can be interrupted through the INT input. Normally, th e processor executes a desired program but, under certain circumstances, it may be required to halt normal operations and temporarily run a different program. This interrupt line is also quite flexible and is able to accept both analog and digital signals. This is accomplished by a Schmitt trigger which can detect the zero crossing points of an AC signal. PROGRiM COUNTER Other interrupts STACK POINTER There are two other ways of interrupting the processor: (1) by using a software interrupt instruction; and (2) by using an interrupt generated by the count out of the on-board interval timer. The interval timer and its optional prescaler are software selectable. Once the counter is loaded, it starts to decrement at the rate of the internal clock. When it reaches zero, an interrupt is generated which the processor may or may not acknowledge, depending upon the setting of internal flags. The prescaler is a 7-bit divider and is used to extend the count of the timer. Resetting of the processor can be accomplished in two ways. First, a lµF capacitor is connected from its RESET pin (pin 28) to ground. This provides sufficient time at power up for the oscillator to stabilise. The second way is to apply a digital (logic 1°1°1°1°1 1 1•1•1•1•1•1 1 1 CONDITION CODE REGISTER HALF-CARRY INTERRUPT MASK NEGATIVE-----' ZERO-----' CARRY------' Fig.3: this diagram shows the 68705 programming model, with the condition code register at .the bottom of the list. This register keeps track of certain operations and is acted upon during the course of the program. low) signal to the RESET line from an external circuit. Software overview The instruction set for the 68705 series of processors is well suited for bit manipulation and testing. Both the HITACHI COMPACT SERIES SCOPES C RT READOUT AND CURSOR SCOPES CRT READOUT SCOPES V-1065A DC to 100MHz V-665A DC to 60MHz V-1060 DC to 100MHz V-660 DC to 60MHz Dual c hannel, delayed sweep, CRT readout, cursor readout (not prov ided on t he V- 1060 and V- 660), frequency counter (not prov ided on the V- 1060 and V-660), sweep tim e autorang in g, trigger lock. Hi tachi Compact features CRT Readout, Sweep Ti me A uto rang in g and Trigge r Lock Functio ns. 'II ST LUCIA ELECTRONICS 'II 24 Campbell St. Bowen Hills V212 AT $719 + TAX (V212 NOT SHOWN) AND "FLUKE" SCOPE METER'S FROM $1459 + TAX. <at> HITACHI 38 S ILI CON CHIP Q 4006. Tel: (07) 252 7466 Fax (07) 252 2862 ECONOMIC ELECTRON/CS: 22 Campbell St. Bowen"Hills Q 4006. P.O. Box 481, Fortitude Valley 4006. Tel: /07) 252 3762. Fax /07) 252 5778. SOUTHPORT ELECTRONIC SHOP: Shop 1, 10 Welch St. Southport Q 4215. Tel: /075) 32 3632. Fax: /075) 51 0543. accumulator and the index registers are eight bits wide, while the program counter is 11 bits wide. This gives the MCU a total address range of 2048 locations. This number includes all ROM, RAM, EPROM, 1/0 ports and DDRs. The stack pointer is also 11 bits wide but is only capable of obtaining_ a depth of 32 bytes as the top 6 bits are fixed. This might seem like a small number but is sufficient for most applications. TABLE 1: 68705 MEMORY $000 Port A $001 Port B $002 Port C (low order nibble only) $003 Not used $004 Data direction register, Port A $005 Data direction register, Port B $006 Data direction register, Port C (low order nibble only) $007 Not used Programming model $008 Timer data register Fig.3 shows the 68705 programming model with the condition code register at the bottom of the list. This register keeps track of certain operations and is acted upon during the course of the program. The first bit informs us if a CARRY has resulted from adding two BCD (Binary Coded Decimal) numbers. The second bit lets us tell the CPU to ignore any interrupts. The third bit tells us if a negative number was stored in the accumulator, while the fourth bit tells us if the value of the accumulator was 0. Finally, the fifth bit informs us if a CARRY was required for the last operation. The entire memory map is shown in Table 1. Notice how all of the RAM, 1/0 ports, timer registers and DDRs reside in page 0, while the EPROM starts in page 1. At the end of memory, there are four vectors and each has its own individual use. These four vectors are: (1) RESET - when power is first applied. (2) INT - when there is a change of state on pin 2. (3) SWI-when the instruction SWI (software interrupt) is encountered in the program. (4) TIV ~ when the internal timer times out. When any of the above four conditions are met, the processor loads its program counter with the data contained in the two locations associated with that interrupt and continues execution from that point. $009 Timer control register $00A Not used $00B Program control register $DOC - $00F Not used $010- $07F RAM $080 -$783 EPROM $784 Mask options register $785- $7F7 Bootstrap ROM (EPROM burner program) $7F8-$7F9 Timer interrupt vector $7FA- $7FB External interrupt vector $7FC-$7FD SWI interrupt vector $?FE - $?FF Reset vector Address modes There is a total of 10 address modes that the 68705P3 can use. Because the range is rather extensive we will only look at a few of the more commonly used ones. Immediate: the first one we come across is the immediate addressing mode, which deals with constants. For example, LDA 30 loads the accumulator with the value 30. Direct: the direct addressing mode is used to load variables rather than constants. Therefore, LDA 30 instructs the processor to load the accumulator with the contents of location 30. In this mode, only page zero is accessible as the effective address is specified by a single byte. Extended: the extended addressing mode is similar to the direct addressing mode except that two bytes are used to form the effective address. Thus , LDA 700 instructs the processor to load the accumulator with the contents of location 700. The disadvantage with this is that execution time is slower and the instruction takes up an extra byte of memory. Inherent: in this addressing mode, there is no effective address. These instructions are used when all of the required information is already in the CPU. As an example, the instruction CLR X would load the index register with all zeros; ie, it would be cleared. Indexed: there are three types of indexed addressing modes accessible to the programmer. (1) Type a: indexed - no offset. The instruction LDA,X instructs the processor to load the accumulator with the contents of the address pointed to by the index register. (2) Type b: indexed - 8-bit offset. With this instruction, the contents of the index register are added to the 8bit offset to give a final address from which the data is manipulated; eg, LDA 40,X. (3) Type c: indexed - 16-bit offset. This 2-byte indexed form of addressing allows complete coverage of the entire address range. For example , the instruction LDA 700,X results in the number 700 being added to the contents of the index register, and then the accumulator is loaded from this final location. Bit manipulation & testing The instruction set for the 68705 series of chips has all of the usual commands as well as some very powerful and interesting bit instructions. The first two we are going to look at are Bit Set and Bit Clear. For example, BSET 3,DRA sets bit 3 . of data register A to logic 1, while BCLR 7,7F sets bit 7 of RAM location 7F to logic 0. The next two unique instructions are Branch If Bit Set and Branch If Bit Clear. Both of these instructions test the designated bit and branch accordingly. For example, BRSET 7,60,20 is decoded as "test bit 7 of location 60 and if set then branch forward 20 locations and continue program execution there". Programming Once the designer has decided on the type of application, the software can be written. Because most people have a PC, a fast and accurate way to produce the necessary code is to use a cross assembler. Basically, this is a language translator which runs on a computer and converts normal ASCII code into a language that the 68705 will understand. The next step is to download this information (hex code) into a 2716 EPROM. Once this has been done , the data is then transferred byte by byte into the EPROM aboard the microcontroller using a 68705 programmer board. SC SEPTEMBER 1992 39