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Al CAPAClTA Build this 4-digit capacitance meter This attractive 4-digit capacitance meter is designed for the workshop or laboratory. It can measure capacitance from 1pF up to 9999µF in seven ranges with an accuracy of better than ± 1% ± 1 digit. By JOHN CLARKE & GREG SWAIN Capacitance meters are always a very useful addition to any electronics workshop. While it is true that capacitors are marked with their value, it is often difficult to interpret the coding or worse still, the markings are illegible. On other occasions, a capacitance meter can be used to select matched capacitor values which may be necessary in critical filter and timing circuits. Many digital multimeters now feature capacitance measuring ranges as standard but these are not usually very accurate. They are also usually unable to measure 30 SILICON CHIP values below about 10pF and above 20µF. The SILICON CHIP Digital Capacitance Meter has no such problems. It is a 4-digit · mainspowered instrument which matches our 1GHz Frequency Meter in styling. It is housed in a grey plastic instrument case and features a red plastic front panel, through which four LED displays can be seen. To use the instrument, you simply connect the capacitor to the test leads and select the appropriate range. The value is then read directly from the big, bright LED display. Seven ranges are available and these allow the unit to measure capacitors anywhere from lpF to 9999µF. An over-range LED flashes whenever the capacitance value is too large for the range selected. Range switching is via two frontpanel switches. One switch sets the capacitance units to pF, nF or µF while the second switch sets the position of the decimal point. Thus, the readings available are 99.99, 999.9 and 9999 for the µF and nF ranges. The pF range operates on the 9999 setting only. The pF range also includes a nulling control. This allows the stray capacitance of the instrument and the test leads to be nulled before taking a reading. The null control is switched out on the nF and µF ranges because it's not needed there. The test capacitor is connected into circuit via two alligator clip leads attached to a BNC line plug. This plugs into a matching BNC socket on the front panel. You can use longer clip leads that those shown in the photos if you wish, provided their stray capacitance doesn't exceed the range of the null control. How it works Let's now see how the unit works. The operating principle is really very simple and relies on the time taken for the test capacitor to charge to a particular voltage. During this time, a 4-digit counter is clocked by a train of pulses derived from a reference oscillator. By suitably adjusting the reference oscillator, the cmmt can be made to equal the value of the capacitor. Fig.1 shows the basic scheme for the Digital Capacitance Meter. In addition to the reference oscillator and 4-digit counter already mentioned, it also uses a gating oscillator and a nulling oscillator. In operation, the gating oscillator generates a positive-going output pulse, the length of which depends on the value of the test capacitor Cx. The larger the value of Cx, the longer the output pulse. This pulse is applied to one input of NAND gate ICBb and gates the signal from the nulling oscillator. The nulling oscillator generates a short negative-going pulse as shown in Fig. l(b). VRl determines the width of this pulse and is the null Most of the parts (including the range switches) are mounted on two PC boards which are then soldered together at rightangles. Note that a small heatsink must be fitted to 3-terminal regulator REG2. control. Fig.l(c) shows the result of gating the two oscillator waveforms with IC8b and inverting the output with IC8c. In effect, the nulling circuit shortens the length of the gating signal by the width of the negativegoing pulse. The length of the pulse from ICBc thus depends on two factors: the value of the test capacitor (Cx) and the width of the pulse from the nulling oscillator as set by the null control. GATING OSCILLATOR IC2, ICBd , IC7b The output pulse from IC8c is applied to one input of IC8a and gates through a train of high frequency pulses from the reference oscillator. These pulses are as shown in Fig.l(e) and clock a 4-digit counter. This counter drives the LED display to indicate the capacitor value. There's nothing especially fancy about any of the parts. In all, there are 9 CMOS ICs, 9 transistors and two 5V 3-terminal regulators, plus associated bits and pieces. A kit of 4-DIGIT LED DISPLAY 4-DtGIT COUNTER CK IC3 HULLING OSCILLATOR IC1 REFERENCE OSCILLATOR IC4 .,. (a) PULSE FROM GATING OSCILLATOR (b) PULSE FROM NULLING OSCILLATOR _J 7_J (c) PULSE FROM ICBc _ ____, (d) PULSES FROM IC8a Fig.1: block diagram of the Digital Capacitance Meter. The time taken for test capacitor Cx to charge determines the width of the pulse from the gating oscillator (a). This pulse is then shortened by the length of the pulse from the nulling oscillator (b) using ICBb & ICBc. The resulting gating signal (c) is then applied to one input of IC8a and gates through high frequency pulses from a reference oscillator to clock a 4-digit counter. MAY1990 31 A IC1, PIN 3 I ~.~,~ I -----,(h IC2, ~N 3 ~..--,--) ·~:.JI_j__ E . ,1) I Cx IC2, PIN 6 I I NULLING PERIOD I---', ICBC, ~IN 10 _ _ I --uu------------------ !'-BEGIN COUNT CK IC3~ PIN 1 2 i l 1 U I I - '--END COUNT H LE IC3, PIN 5 _....:._._ _ _ _ _ _ _ ____, I R IC3, PIN 13 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __, J CE IC6, PIN 13 Fig.2: this diagram shows the waveforms at various parts of the circuit and should be followed in conjunction with the text. Note the latch enable (H) and reset (I) pulses which appear at the end of the count. parts will probably cost you somewhere around the $120 mark. Circuit details Refer now to Fig.3 which shows all the circuit details. The first thing to note is that all the circuit elements shown in Fig.1 can be directly related to Fig.2. IC1 is the nulling oscillator, IC2 the gating oscillator, IC4 the reference oscillator and IC3 the 4-digit counter. The nulling oscillator consists of a 7555 timer, IC1, wired in astable mode. When S1b selects either the pF or nF ranges, the 0. lµF timing capacitor on pins 6 & 2 charges via a 10MO resistor. VR1, the null control, provides the discharge path for the timing capacitor. These timing components give a charging time of about 0.7 seconds (pin 3 high) and a discharge time between O and 35µs, depending on the setting of VR1 (pin 3 low). Thus, IC1 generates a brief negativegoing pulse at its pin 3 output every 0.7 seconds. This output signal (waveform A in Fig.2) is applied to pin 5 of NAND gate ICBb via a 10k0 resistor (pF range only). When the µF range is selected, 32 SILICON CHIP the nulling oscillator works in a different way. On this range, Slb switches a 33µF capacitor and 1MO resistor in parallel with the existing timing components on IC1. This increases the output high time of IC1 to approximately 22 seconds. This is necessary to ensure that large value test capacitors in the µF range have sufficient time to charge. The update time on the µF range is not fixed at 22 seconds, however. That only applies to very large value test capacitors (ie, those approaching 10,000µF). For lower values, the update times are considerably shortened by employing some clever circuit techniques as we shall see later on. As well as feeding pin 5 of IC8b, the pin 3 output of IC1 is also differentiated using an 820pF capacitor and a 4.7k0 resistor. The resultant negative-going spike (waveform B, Fig,3) is applied to the pin 2 trigger input of 7555 timer IC2 and to pin 3 (CK) of D-type flipflop IC7b. This triggers IC2 on its negative-going (leading) edge and clocks IC7b on its positive-going (or trailing) edge. IC2 is wired for monostable operation (triggered by IC1) and the test capacitor (Cx) is charged (and discharged) via a timing resistor selected by Sla and either S2a, S2b or S2c. If the switches are in the positions shown on Fig.3, Cx will charge and discharge via a 1MO resistor [as selected by Sla & S2a). The 100k0 resistor in series with pin 6 of IC2 protects the 7555 if a test capacitor that has been charged to a high voltage is inadvertently connected to the circuit. Otherwise though, the 100k0 resistor plays no part in the circuit operation. IC2's pin 3 output drives six inverters from a 4049 IC package (IC9). These inverters are paralleled in two groups of three and drive complementary transistor pair Qt & Q2 via 6.8k!1 base current limiting resistors. Now let's consider what happens when we connect a test capacitor across the Cx test terminals. Initially, pin 3 of IC2 is low and so pins 2, 4 & 6 of IC9 are all high. Thus, Q2 is on and this effectively grounds the wipers of S2a-S2c. When a trigger pulse arrives from IC1, IC2 triggers on the negative-going edge and switches its pin 3 output high (waveform C). This turns Q2 off and Qt on and so Cx now charges from the + 5V rail via Q1 and the selected timing resistor. The high on pin 3 of IC2 also drives the output of NAND gate IC8d low and this pulls the Set input (pin 6) of dual-D flipflop IC7b low. IC7b then triggers on the trailing edge of the trigger pulse and switches its Qbar output (pin 2) high. This is shown as waveform D on Fig.3 and is the gating pulse which is applied to pin 6 of IC8b. Pin 3 of IC2 remains high until Cx has charged to 2/3Vcc (ie, to 2/3 the + 5V supply rail). At this point, pin 3 goes low and IC8d pulls the Set input of IC7b high. This switches pin Fig,3: all the parts depicted in Fig,l ► can be directly related to the main circuit, ICl is the nulling oscillator, IC2 the gating oscillator and IC4 the · reference oscillator. IC3 is the 4-digit counter and this drives four common cathode LED displays via switching transistors Q4-Q7. Over-range indication is provided by Q3, IC7a and LED 1. S2b S2c DP2 +5V DP2 0.1! 1M 1% 10k 1¾ +5V 100!:l D1 1N4002 D3 1N4002 1% pF S1a IC 2 7555 100k 0.1! 1M 4.7k ex 10M uF S1b 33 .J.:" 16VWl 3 A nFO pF 0.1 O.li i 820pF IC1 7555 STYRO .,. 1.,. +5V 10k +5V D nF F p uF '°'-__ S1d +5v__J' " 12,CK .,. pF 3.15 +5V 7x47!:l a c~17 0.1! RBLLJ' _!_§_ 13 950kHz ~ 11cK1 10 EN 1 EN2 CK2 IC5 4518 IC4 7555 .,. ~ ,-.. co co - ':" E--:i., N "-l "-l IC6 4017 2155 r IC3 74C926 1~ g•4 R 24 H 5LE Al .,. vcc 81 18 DISPLAY 3 BELOW 10 Cl)_M IDP2 3,8 COM IDP3 3,8 15 7 8 D,11 1 . r·· , vcc - - I DIGITAL CAPACITANCE METER DP2 ~ DP3 DISPLAY 4 I I I I cil! ELJc VIEWED FROM 1,cuu,_ .,. ,-, ,-, ,-, DISPLAY 2 I I /c It 131R 8 G:) 1 16VWI •/ d 1~ GND 05 .,. 0 9 .5kHz 14,CK J_! 5 v---;)l~:fsv1sv~\:!J~f,---. __ 1r-+1rr----------..!!lll 1000 .J.:" 22 .J.:" :::::mo-'-:[ 2x1N4002. 16VWI ---•wI ...~... 22 p!UT f + 5V 16VWr A---0 " S3 CE 041 ) ·-~~ 100pFI STYRO ~ JlJ R2 15 Al POWER •• 2 1§_ 04/14 1/-:)b d'l 0.1! 95kHz .,. 4xHDSP-5303 DISPLAY 1 bl16 1J3w.J.: LEDl DYER-RANGE 03 BC548 cotl4 vcc vcc c_gr,, 3,8 PARTS LIST 1 plastic instrument case, 203 x 67 x 158mm 1 PCB, code SC04106901, 173 x 82mm 1 PCB, code SC04106902, 174 x 62mm 1 Scotchcal front panel, 1 95 x 32mm 1 masking film, 195 x 64mm 1 red Perspex sheet, 1 95 x 64 1 aluminium plate, 178 x 45mm x 1.5mm 1 2155 1 A 15V centre-tapped transformer 1 mains cord and plug 1 cord grip grommet 1 plastic push on/push off mains switch (Jaycar Cat. SP-0716 or equivalent) . Note: don't substitute a metal-bodied type . 1 T0-220 heatsink, 27 x 25 x 34mm 2 4-pole 3-position rotary switches 1 5000 linear potentiometer 1 5k0 miniature vertical trimpot 2 20mm knobs 1 15mm knob 1 BNC panel socket 1 BNC line plug 1 red alligator clip 1 black alligator clip 40 Molex pins 1 1 -metre length of 1mm tinned copper wire 1 200mm-length of blue mains wire 2 of IC7b low again to end the gating pulse. Cx now discharges via Q2 and its selected timing resistor in the case of the pF and nF ranges, and via Q2 and either Dl, D2 or D3 on the µF range. These discharge diodes are necessary on the µF range to ensure that the test capacitor discharges completely before the next trigger pulse arrives from ICl. So why have we used the Q-bar output of IC7b as the gating signal instead of the pin 3 output of IC2? After all, the two waveforms are almost identical, the only difference being that Q-bar of IC7b goes high just after pin 3 of IC2 goes high. The reason is that if no test capacitor is connected to the circuit, pin 3 of IC2 generates a brief 34 SILICON CHIP 1 240mm-length of blue heavy duty hookup wire 1 1 20mm-length of brown heavy duty hookup wire 1 50mm-length of red heavy duty hookup wire 1 50mm-length of black heavy duty hookup wire 1 200mm-length of light duty hookup wire (for VR1) 1 80mm-length of 1 2mm heatshrink tubing 7 PC stakes Semiconductors 4 HDSP-5303 12.5mm common cathode red LED displays 1 rectangular red LED (LED 1) 3 7 555 CMOS timers (IC1 ,IC2,IC4) 1 7 4C926 4-digit decade counter (IC3) 1 451 8 dual BCD counter (IC5) 1 4017 decade divider (IC6) 1 4013 dual-D flipflop (IC?) 1 4011 quad NANO gate (IC8) 1 4049 hex inverting buffer (IC9) 3 BC328 PNP transistors (Q1,Q8,Q9) 5 BC338 NPN transistors (Q2,Q4-Q7) 1 BC548 NPN transistor (03) 5 1 N4002 1 A diodes (D1 ·D3,D5,D6) 1 1 N914 diode (D4) pulse each time it receives a trigger signal from ICl. Without IC7b, this pulse would gate through pulses from the reference oscillator to the counter and so the display would indicate a reading when it should be displaying 0000. Because of the way it is clocked, IC7b doesn't respond to these short pulses from IC2 and its Q-bar output remains low. Thus, no pulses can be gated through to the counter and so the display reads 0000 with no capacitor connected - which is just what we want. On the pF range, IC8b & IC8c gate the signals from ICl and IC7b as described previously for Fig.1. This produces waveform F on pin 2 of ICBa which then gates through the pulses from the precision 2 7805 5V 3-terminal regulators (REG1, REG2) Capacitors 1 1 OOOµF 16VW PC electrolytic 1 33µF 1 6VW PC electrolytic 1 22µF 16VW PC electrolytic 1 1OµF 16VW RBLL electrolytic 1 1OµF 1 6VW PC electrolytic 1 4. 7µF 16VW PC electrolytic 1 1µF 1 6VW PC electrolytic 8 0. 1µF monolithic 1 0.1 µF 1 % polyester (for calibration) 1 820pF polystyrene 1 1 OOpF polystyrene Resistors (0.25W, 1 10MO 2 1 MO 1 % 1 1MO 1 1 OOkO 1 % 2 1 OOkO 2 10k0 1 % 3 10k0 2 6.8k0 5%) 1 4. 7k0 1 2.2k0 1 1 kO 1 % 1 1 kO 1 6800 1 1000 1 % 1 1000 9 470 Miscellaneous Solder, machine screws and nuts, self-tapping screws. Note: this circuit will only operate correctly with CMOS 555 timer ICs. These can be marked ICM7555, TLC555CN or LMC555CN. The LM555CN in not suitable since it is only a standard 555. oscillator circuit to the 4~digit counter (IC3}. When the nF and µF ranges are selected, the nulling circuit (but not !Cl} is disabled by using Sld to switch pin 5 of IC8b to + 5V. This means that IC8b now gates through the entire waveform from IC7b (ie, IC7b's output is no longer shortened by the width of the pulse from the nulling oscillator). Reference oscillator Reference oscillator IC4 consists of yet another a 7555 timer. This is wired in astable mode and oscillates at 950kHz as set by a lkO resistor, calibration trimpot VR2 and a l00pF timing capacitor. The 950kHz signal appears at pin 3 and is applied to the pF range of Slc The four LED displays are mounted using Molex pins. Install each display with the decimal point at bottom right. Mount the over-range indicator LED so that its top surface is level with the displays. and also to the CKl [clock) input of IC5. IC5 is a dual BCD counter which divides the 950kHz output from IC4 by 10 and 100. The divide-by-10 signal (95kHz) appears at the Q4 1 output [pin 6) and is applied to the nF position of Slc. It also clocks the CK2 input (pin 9) of the second counter to produce the divideby-100 (9.5kHz) signal at Q4 2 (pin 14). This 9.5kHz signal is fed to the µF position of Slc and also clocks decade counter IC6 [4017). Depending upon the range selected, S 1c couples one of the reference signals (950kHz, 95kHz or 9.5kHz) to the pin 1 input of IC8a. When the gating signal from ICBc is high, the selected reference signal [waveform G) passes through ICBa and clocks IC3, a 74C926 4-digit counter. In addition to the 4-digit counter, IC3 also contains latches, BCD to 7-segment decoder drivers, and internal multiplexing circuitry. It drives four common-cathode displays in conjunction with transistors Q4-Q7. The a-g display segments are driven via 470 current limiting resistors. S2d, Q8 and Q9 provide the decimal point switching. When S2d is in the open position (as shown on Fig.2), both transistors are off and so the decimal points are also off. When DP3 is selected, Q9's base is pulled low via a 1okn resistor and so the transistor turns on and lights DP3. Similarly, when DP2 is selected, QB turns on and lights DP2. Strictly speaking, QB & Q9 can be eliminated and S2d used to switch the decimal points directly to the + 5V rail via 470 current limiting resistors. However, this arrangement would have upset the stability of the meter because we would have had to route the high-current decimal point supply lines close to the Cx input. QB & Q9 solve this problem because they require only low current lines for their bases to pass near the Cx terminals. Latch enable & reset In order to function correctly, the 74C926 must be fed with two control signals: latch enable (LE) and reset (R). The LE signal instructs the 74C926 to transfer the contents of the counters to the latches. The latches then drive the display, leaving the counters free to be reset and clocked with the next series of pulses. The latch enable and reset signals are generated using a 4017 decade counter [IC6) with decoded outputs. This device is clocked by the 9.5kHz output at pin 14 of IC5 and each decoded output goes high in turn for the period of the clock signal. The decoded "2" output (pin 4) provides the latch enable signal while the decoded '' 4'' output [pin 10) provides the reset signal. These are shown as waveforms H I on Fig.3. Thus, the sequence of events is as follows. First, the gating signal arrives at pin 2 of IC8a and the reference oscillator [or one of its divided outputs) clocks IC3. Next, after the gating signal has finished, the latch enable is taken high by IC6 and the contents of the counters are latched and displayed. Finally, the reset (pin 13) is pulled high and the counters are cleared for the cycle. Note that the Reset input (pin 15) of IC6 is connected to pin 3 of IC2. This means that IC6 can only be clocked when pin 3 of IC2 is low (ie, at the end of the gating period). This ensures that the latch enable and reset signals for IC3 are generated at the appropriate times. IC6 also provides the rapid update feature for low value capacitors on the µF range. It works like this. At the end of the reset pulse, IC6's decoded "5" output (pin 1) goes high and pulls the Clock Enable [pin 13) high. This stops the counter and so decoded output "5" remains high [waveform J on Fig.2). This high now quickly charges the 33µ,F timing capacitor on Slb via a 1ookn resistor and D4 and thus enables ICl to deliver a new trigger pulse to begin the next cycle. Without this feature, the µF range would only be updated every 20 seconds or so, since it would & MAY 1990 35 Fig.4: here's how to install the parts on the two PCBs. Note that you will have to remove two pins from Sl before soldering it to the display board. Be sure to use 1 % resistors where indicated and take care with component polarity. , -I ~ I•• •7 I I 0 --ob-. ~ or. Ok OOk 1M 100n / D3~ / -aDot take this long for the 33µF capacitor to charge via the lMQ resistor. By using IC6's decoded "5" output to charge the 33µF capacitor, the display update time is reduced to slightly longer than the charging time for the test capacitor (Cx). Over-range indication Q3, flipflop IC7a and LED 1 form the over-range indicator circuit. This is driven by the carry out [CO) output of IC3. During each cycle, the CO output goes high when [and if) a count of 6000 is reached and this turns on Q3 which pulls the clock input [pin 11) of IC7a low. If IC3 is subsequently clocked from 9999 to 0000, its CO output goes low again and Q3 turns off. When this happens, the CK input of IC7a is immediately pulled high [via the 2.ZkO resistor) and clocks a high to the Q output which lights LED 1. IC7a is then reset using the same pulse that resets IC3 and so the Q output goes low again and the LED goes out. Thus, LED 1 flashes on and off 36 SILICON CHIP for counts greater than 9999 to indicate that the meter should be switched to the next highest range. Power supply Power for the circuit is derived from a 15V centre tapped lA mains transformer. This feeds a full-wave rectifier circuit consisting of D5 & D6 and the resulting unregulated supply rail then used to drive two + 5V 3-terminal regulators. One of these regulators supplies power to IC3 [Vee) and the displays, while the other supplies + 5V to the rest of the circuitry. So why use two separate regulators? The reason is that IC3 and the displays generate hash on the supply line because the displays are multiplexed. By using two separate regulators, this hash is kept out of the sensitive capacitance measuring sections of the circuit. Building it Despite the circuit complexity, the Digital Capacitance Meter is easy to build. All the parts are mounted on two PC boards which are soldered together at rightangles and mounted in a standard plastic instrument case. This method of construction reduces the internal wiring to a minimum. Most of the parts are mounted on the main PCB (code SC04106901), while the display PCB (code SC04106902) carries the LED displays and range switches. The completed assembly slots into a matching groove in the front of the case, along with the captive red Perspex panel which is held by the switch locking nuts. Four self-tapping screws are then use to secure the assembly to integral pillars in the bottom of the case. A self-adhesive dress label covers the bottom half of the Perspex panel and this gives the unit a very professional appearance. In addition, a light mask is fitted to the back of the panel to blank out unwanted areas of the display board. Fig.4 shows where the parts go on the two PC boards. Begin by installing the wire links on the main Fig.5: here's how everything goes together inside the case. The power transformer is mounted on an aluminium plate and this is secured to the bottom of the case by selftapping screws. The Perspex front panel is mounted on the rotary switches and secured by the locking nuts. REAR PANEL ALUMINIUM PLATE ACTIVE (BROWN) 8 <at>I :::,..,,::._~----~~__r-- 8 -= ' ~ ~~ ~ ~ r SELF·TAPPING_/ SCREWS :>......=..____ ----r1 SO[rLDER REGULATOR HEATSINK I I PLASTIC I INS ULA TING ----i SLEEVING I I : S1 PCB (0.6mm tinned copper wire will do nicely), then install PC stakes to terminate the leads from the power transformer secondary and from VR1. This done, you can install the remaining parts on the main board but make sure that all polarised parts are correctly oriented. These parts include the ICs, transistors, regulators, diodes and electrolytic capacitors. Make sure that the correct transistor type is used at each location. VR1 to be positioned as close to the centre of the PC board as its mounting slot will allow so that it clears one of the side pillars in the case. No heatsink is required for REG 1 which can be bolted directly to the board. Display PCB Now for the display PCB. Install S2 PC pins at the Cx and GND terminals, then install the wire links, diodes, resistors, transistors and capacitors. The over-range LED should be installed so that its top surface is 13mm above the surface of the board. Don't trim the LED leads just yet in case you have to make adjustments later on. Note that the lOOk!J resistor on pin 6 of ICZ is stood on end to save space. For the same reason, the O.lµF capacitors should all be miniature monolithic types (don't use greencaps - they won't fit on the board). A small heatsink is fitted. to 3-terminal regulator REGZ to aid heat dissipation. Smear the metal tab of the regulator with heatsink compound and install a solder lug under the head of the screw before bolting the assembly to the PC board. Note that the heatsin.k needs The plastic insulating sleeving fitted over the power switch should be long enough to pass right through the heatsink. In addition, the heatsink is earthed by connecting it to mains earth (see Fig.5). M AY 1990 37 solder tack them in a couple of places. Now test the assembly in the case (the PCB goes in the rearmost slot at the front of the case) and make any adjustments that may be necessary. When everything is correct, solder all the matching pads together to create a permanent assembly. Note that is is normal for the main PC board to sit slightly proud of the standoffs on the bottom of the case. Final assembly The combined PCB and front panel assembly slides into the slots at the front of the case and is secured by four self-tapping screws through the main board. Take care with the mains wiring. The four 7-segment LED displays are stood off the board using Molex pins. To do this, separate the Molex strips into eight 5-pin lengths, then solder them to the board and snap off the shorting bars. The displays can now be pushed into the pins as far as they will go. Check that the decimal point is at the bottom right of each display. If you do insert a display upside down, all sorts of odd segments will light up. The two rotary switches can now be installed on the PCB. Use a pair of sidecutters to remove two pins from Sl as indicated on Fig.4 and push both switches down onto the PCB as far as they will go before soldering the terminals. The board will accept both the open-style rotary switches sold by Dick Smith Electronics and the enclosed type sold by other retailers. Construction of the PCB assembly can now be completed by soldering the two boards together at right angles. To do this, carefully align the edge pads of the two boards and The input connector consists of two alligator clip leads wired to a BNC plug. You can make the leads longer than those shown here if you wish, provided their stray capacitance doesn't exceed the range of the null control. 38 SILICON CHIP Fig.5 shows the final assembly details. Begin by affixing the adhesive label to the bottom of the Perspex panel, then position the light mask on the back of the panel and mount the mains switch, nulling potentiometer and BNC input socket. The front panel can now be mounted on the two rotary switches and secured with the switch locking nuts. If the Perspex panel is not sup. plied pre-drilled, use the light mask to mark out the positions of the mounting holes. The power transformer is mounted on a 178 x 45mm aluminium panel at the rear of the case. Use screws, nuts and lockwashers to secure the transformer and earth solder lugs as shown in Fig.5. This assembly is secured to integral standoffs in the bottom of the case using self-tapping screws. The mains cord enters through a hole in the rear panel and is clamped using a cord grip grommet. Before clamping the cord, strip back about 15cm of the outer sheath so that the active (brown) lead can reach the mains switch. The mains wiring can now be completed as shown in Fig.5. Note the earth link between the solder lug attached to REG2 and the earth lug on the transformer mounting panel. This is necessary because the leads to the mains switch pass close to the heatsink. As an additional safety precaution, sleeve the switch terminals and the leads adjacent to the he~tsink with heatshrink tubing (see photo). The construction can now be completed by wiring up the transformer secondary, the null control and the BNC input socket. «H Mllm -t11n1a1.u1;1., L:sco41os902 0 ~T"" 0 0) o:::t 0 (.) (/') 'ID Fig.6: here are full-size artworks for the two PC boards. Keep the leads between the BNC socket and the display board short and make sure that the centre pin of the socket goes to the Cx pin. The GND pin connects to the solder lug on the BNC socket. The leads between the main board and the null control are routed through a hole near the top of the display board. Now go over your work carefully and check for possible wiring errors. In particular, check for missed solder joints, shorts between adjacent pads on the PCBs, and incorrectly oriented parts. If everything is OK, switch on and check that all four digits show a reading. This should be 0000 when S1 is in either the µF or nF position. Check that the correct decimal point appears when S2 is set to 99.99 and 999.9. Now rotate the null control fully anticlockwise and select the pF range. Check that you can zero the reading by winding the null control in a clockwise direction. If you strike problems, switch off immediately and check for wiring errors. The waveforms shown in Fig.2 will be useful for troubleshooting if you have access to a CRO. Calibration A 0. lµF 1 % calibration capacitor has been specified in the parts list but other precision values could 11\ also be used if you have them on hand. To calibrate the instrument, connect the 0. lµF capacitor to the test terminals and select the nF and 999.9 ranges. Now adjust trimpot VRZ until the display reads 100.0 (ie, l00nF) - and that's it. You don't have to calibrate the other ranges. Once the unit has been calibrated on one range, the other ranges will automatically be correct. Using the meter Note that some care should be exercised when nulling the instrument on the pF range. The correct procedure is to wind the null conMAY 1990 39 t,() = = 1: "C CII "'CII "C Ql "' = Ql ~ = CII I.I ..:.: "'CII e -! = ~ ..;,,l a: w 1w "'CII e ~ ... w (1) 0 (/) (.) .D ·= <( 0 ... :: (1) ~ea ... E u Ill -(/) c. Ill QI u (1) (1) c,; (0 0 .1:.- ~!: 'C C> • • C: C>;; ·= gC: 3:: u C: ... Ill C: 0 z - 1( .) <( a. <( (.) ..J <( - 1- C, 0 a:w c., ..,._wz > <C a: Oa: w ~ trol fully anticlockwise, then wind it slowly back until the display just reaches 0000. Once the display shows 0000, you've found the correct nulling point and the null control should not 40 SILICON CHIP be moved. If you do keep winding the control back, the display will still read 0000 but the nulling pulse will now be too long and readings on the pF range will be too low. Finally, be aware that a capac- itor charged to a high voltage and then connected to the test terminals may damage the circuit. It is therefore a good idea to ensure that the test capacitor is discharged before connecting it to the meter.I§;!