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Part.2 Build your own LED Message Board Last month we introduced this exciting peripheral device for a computer which can also be driven from an IBM keyboard. This month we continue with a more detailed circuit description with emphasis on the inter£ace board. By DON McKENZIE 36 SILICON CHIP Let's pick up where we left off and continue with the description of how the display is driven. To make the text easier to follow, we have repeated the circuit of the interface board this month. The display is refreshed constantly in much the same way as a dynamic RAM. As noted before, your eyes perceive that all LEDs are switched on together but they are never all on together. Only one horizontal row is ever selected at any given time and the display data for each row is updated or "refreshed" each time a new row is selected. This refresh period is determined by the resistor and capacitor values in the 555 timer circuit on the main CPU board but more about this timer later on. The refresh time is set to just under one millisecond [lms). So allow lms for each horizontal row update. With seven rows this means a 7ms cycle to update the full display. Before updating any row, all row driver transistors Ql to Q7 on the interface board are switched off. By the way, the emit- ters of Ql to Q7 on the interface board should be connected to the + 9V rail instead of the + 5V rail as shown last month. Having turned off all the drivers, the information to be displayed in the top row [row 1) is sent out as a serial bit pattern after being assembled by the micro. This serial data stream is clocked through the daisy chained 74LS 164s on the display panels. More on the data and clock signals later. For a 16-character display, there are 96 LEDs in each row, so 96 bits must be sent through the daisy chained 164s. These chips are simple serial to parallel converters clock eight bits in and these eight bits are presented on the output pins. The last output is sent to the next 164's data input pin to form the daisy chain. When the full 96 bits of data are clocked through the daisy chained 74LS164s, they become the column [vertical) information. The full refresh cycle Assembling a mirror image of the ASCII text buffer after internal character bit pattern generation and then feeding this information to the serial to parallel converter [shift registers) ICs on the display panels, at 96 bits per row, takes a bit of CPU time. It represents around 1/3 of a millisecond for each row. At a display refresh time of lms per row this leaves us with 2/3 of a millisecond for actually displaying each row. The full sequence of events for one display cycle is as follows, with the timing shown in fractions of a millisecond: • Switch off all transistors: 0.00. • Write Row 1 data (96 bits) to display panels: 0.00 to 0.33. • Switch on Ql to display row 1: 0.33 to 1.00. • Switch off all transistors: 1.00. • Write Row 2 data (96 bits): 1.00 to 1.33. • Switch on Q2 to display row 2: 1.33 to 2.00. • Switch off all transistors: 2.00. This sequence is repeated on all rows and transistors right through to Row 7 to finish the 7ms cycle. The full sequence is continually repeated under processor driven interrupt control. Note that one LED is only on for 0.66ms in every 7ms cycle, a duty cycle of about 10%. Let's now have a look at the 74LS373 octal latch El (page 39, last month). This is the row select latch. In order to select a single row, El is loaded with the row select byte. Data bits DO, Dl and D2 are used to select rows 1 to 7 [binary 0 to 6). Data bit D3 (pin 8) is latched through -to pin 9 to enable or disable the outputs of E2, the 7445 row driver IC. When all transistors Ql to Q7 are to be switched off, D3 is high. The row information (DO to D2) is presented to the El latch together with the enable bit [D3). To latch or lock this data into El a clock pulse must be sent to pin 11 of El. This row latch dock comes from the output busy [BSY) signal of the CPU board and is inverted by gate E4b. The outputs of El not only drive E2 but also E3, a 74LS151 8-input multiplexer. If Row 1 has been set as the current row by loading El, this row select information is also presented to pins 9, 10 and 11 of E3. These signals determine which data lines DO through D7 are selected as the data input of E3. With Row 1 selected and locked into El, data bit DO is the selected data input for E3. If Row 2 was locked into El then data bit Dl would be the selected input bit for E3. The same applies right up to Row 7 and data bit D6. Data bit D7 serves another function which we will explain shortly. E3 (74LS151) simply passes the selected data bit from its input to its output at pin 5. Thus E3 performs a parallel to serial data conversion APRIL 1989 37 A000-BFFF C000-FFFF This is one of the 7 x 24 LED panels, four of which are required to make up the full display. Each panel has 168 LEDs in all. and the resulting serial data stream is fed to the daisy-chained 74LS 164 shift registers for the LED display. One half of E6, a 74LS04 hex inverter, is used to buffer the serial data to the LEDs. The other half is used to buffer the clock for the shift registers. This clock signal comes from the CPU output strobe (STB) signal. So we have one set of data (DO to D7) and two clocks, BSY and STB. That sounds confusing. The busy (BSY) clock locks the data into the row select latch, while the strobe (STB) clock is used to clock data into the 74LS164s on the display panels. Flash timer E5 is a 555 timer which provides the flashing display mode for the Message Board. The output at pin 3 is gated with data bit D7 to drive the enable pin of E3. When the timer output is low, the output of E3 is also low and so, effectively, no serial data passes through. When the timer output is high, the serial data passes through. When D7 is high, the timer has no effect and the flash mode is off. CPU board As noted last month, the CPU board is a complete microprocessor controller which uses a ZB0A microprocessor, a 2764 EPROM, a 6264 BK x 8 static RAM and an 8255 programmable peripheral interface (PPI) - see page 37, March 1989. The CPU board updates the display with CPU interrupts using an interrupt service routine, and all that is required to change the display is to load the display buffer (DISBUF) with a mirror image of the ASCII data to be displayed. The memory map is as follows: 0000-lFFF 2000-7FFF 8000-97FF BK EPROM FIRMWARE (2764) MIRROR IMAGE OF 0000-lFFF BK STATIC RAM (6264) Where to buy the parts At the time of writing no complete kits for this project are likely to be available. A complete set of printed boards plus the programmed 2764 EPROM and full instructions is available from the designer, Don McKenzie, for $150. The specially made grey Perspex channel, suitable for all LED colours, is also available from Don Mckenzie for $50 plus $15 for packing and postage. Write to Don McKenzie, 29 Ellesmere Crescent, Tullamarine, Victoria 3043. All the semiconductors and other parts are readily available from parts suppliers such as Jaycar Electronics, Altronics, Rod Irving Electronics, Geoff Wood Electronics and David Reid Electronics. 38 SILICON CHIP MIRROR IMAGE OF 8000-9FFF 74LS373 ROW SELECT LATCH (OUTPUT BUSY) INCLUDES MIRROR IMAGES. The only port addressed device is the 8255 PPL This is the interface to the computer input and message board output bus. The ZB0A's IORQ (input/output request) line is connected to the chip select of the 8255. Any time an 1/0 instruction is executed the 8255 responds. Any port from zero to 255 is the 8255's port decode. The power up routines program the 8255 to mode 1, Port A input, Port B output, and Port C handshaking for A and B. Capacitor C5 hanging on the chip select line to ground produces enough of a delay to satisfy the timing restrictions of ZB0A to 8255 interfacing. Pin 12 of the 8255 is the input BUSY to the (external) computer. This signal is inverted by E13a (74LS04) to produce the ACK signal. This means that while the 8255 is holding the ACK active (low) it sends the BUSY signal to the computer. The ACK is also connected to R4 and the data LED. The LED lights up when the BUSY is high and ACK is low, and switches off when BUSY is low and ACK is high. This LED is used for the ROM diagnostic routines to aid kit builders, and also indicates data entry into the CPU board. 2764 EPROM The 2764 EPROM has two chip enables, pins 20 and 22. Pin 20 connects to the MREQ signal of the CPU. Any memory referenced instruction will select the EPROM but no data output will take place until you also chip select pin 22. Pin 22 is connected to A15 of the CPU. Any time A15 is low and memory is selected the EPROM is enabled. This gives an effective address for the EPROM from 0000 to 7FFFH. A13 is already dedicated to the output strobe, so a maximum size of BK of EPROM can be used. 6264 static RAM The 6264 static RAM has two chip enables, pins 20 and 26. Pin 20 connects to A14 of the CPU and pin RB 2.21l 10W J3 CENTRONICS 36 PIN FEMALE INPUT GNO 16,19-30,33 J2 26 25 240 5V ------------,u+9V 9V IN 32 J1 3A 12V IN 13 GNO 25 12 BSY 0 24 BSY Ol l 1 C3 + 16~WI BC1·BC5I TANT 5x.01 COMMONo--------+---- 23~10 22~9 POWER TO PBUFF 21~8 +5V 20~7 16 19~6 IBM PC/XT KEYBOARD CONNECTIONS 5-PIN DIN SOCKET 18~5 170 02 017 100 01 016 • ,O, 02 01 0103 15~2 14~1 PINS 14,15,17,18, 31,34,35,36 N/C +5V013 I GNO 012 BSY -11 6 - 05 74LS02 4 E4b 111 - I 2 4 MMB STB J2/14 TO RN6 SIOE0-----4 OF COMPIKBO ...,_,..,.......,_. SWITCH 15 +9V Ls 120 9 14 04 -6 03 ..,.s _4 02 01 -3 8 - E1 74LS373 ENABLE OPTIONA L COM P/K 80 DECODE CIRCUIT 13 5 S1 14 I 4 2 so 15 E2 7445 3 00 -2 oL ~c JS 0825 MAL J4 OUTPUT + s v ~13,26 _ -12,25 ROW 1 12,25 7~Joi~6 +9V ROW 2 ~11,24 4701l 12 6 S2 7 -- J2/22 74LS157 KBO CLK OIN/1 17 8 -7 COM STB J3/1 J2/14 STB J2/22 07 J2/25 GND MMBCNT J2/26 +sv 18 13 STB CLOCK DATA GNO +5V 7 MMB 07 KBO DATA OIN/2 +5V 5 ACK 010 07 -9 06 1 2 KEYBOARD 4 5 COMP D7 J3/9 1 ROW 1 2 ROW 2 3 ROW 3 4 ROW 4 5 ROW 5 6 ROW 6 7 ROW 7 1k B1/E -- ROW 3 ~ 10,23 4701l al?: ROW 4 ~ 9,22 Q7 1k ROW 5 ~ ~ 8,21 ROW 6 ~ 7,20 _ _ 6,19 ROW 7 6,19 -- '-.:::,i C ~ ~o - -- ~ .,. 5,18 ~ .,. 11 10 9 07 12 06 13 D5 14 04 15 D3 1 D2 2 D1 3 DO 4 2_:r E4a 3 1 ~ 8 +5V ~ 7 LED2~ RUN R7 1501l B 1 ·:; CLOCK- - -- 4,17 ., ~ 4 -3 16 C 6 ~ 1Uw=~ -- R3 1k 2 BD646 .~l: = + - - a ' L- DATA_ -4,17 74LS04 7 ES 555 __.§ E61 1~ 5 3 12 C1 E3 74LS151 ':" 8 4 .........z R2 100k 1E,6° 14 10 7 +5V R1 100k +sv !L.-+sv BCE 7805 3,16 R4 1k ~ + 5 V ~ 2,15 ~ 1,14 -~M GND Fig.2: the interface board circuitry. It accepts data from the programmable peripheral interface and decodes it to obtain the 7 row driver lines. It also produces the serial data to drive the 8-bit shift registers in the LED display panel. 26 to A15. Pin 20 is a low select and pin 26 is a high select. This gives an effective memory map of 8000H to BFFFH. The read and write signals connected to pins 22 and 27 control the data flow to and from the static RAM. Serial Data clock The message board output strobe is produced by inverting CPU signal A13. One gate of the 741S04 (E13c) is used for this. Any time the program sets A13 high, a serial data clock pulse is delivered. During APRIL 1989 39 This is the view inside the Message Board control unit. It contains the power supply, the microprocessor controller and the interface board. power up or reset of the CPU c:11 address and data bus signals go to a high impedance state. The high to A13 appears as an output strobe every time the CPU is reset. R5, a lkO resistor, is used as a pulldown to prevent this output strobe during power up or reset. The output BUSY line is pulsed when A14 and A15 are high. This gives a starting address of COOOH. When the A15 line goes high, it disables the EPROM and a high on the line disables the static RAM. Two gates of E9 (741S00) are used to gate this signal which connects to the interface board as the row select latch clock. The 555 timer for the Z80 interrupt is set up as a 1: 100 duty cycle timer with a short low-going pulse every 0.95ms. This interrupts the CPU every 0.95ms to service the display update routine. Keyboard/computer switch As noted previously, the LED Message Board can accept input from an IBM keyboard or external computer via the Centronics port. The keyboard/computer switch S2 sets PC7 pin 10 of the 8255 either high or low to tell the CPU which input mode it is in. If it is in the corn- The front panel of the Message Board control unit carries the Reset switch, keyboard/computer switch and two LEDs (Data and Run). 40 SILICON CHIP puter mode then the data byte presented to port A is read as a full 8-bit byte and acted on accordingly as data in. If the keyboard position is selected, only data bit 7 is read in and assembled as a keystroke either 9 or 10 clocks at a time. The strobe operates in the same manner in either mode; ie, as a data bit detect. When a strobe is detected the 8255 input "buffer full" signal is set at pin 17 of the 8255. This signal passes through an inverter (E13f) to pin 17 (NMI - non-maskable interrupt) of the CPU. This interrupts the current task of the Z80A to execute a service routine for the keyboard or .computer input. PC7 can also be used to control the optional 741S 15 7 keyboard/ computer decoder shown on the circuit for the interface board. This allows you to connect up both a computer input and a keyboard at the same time. This was convenient when the software for this project was being developed but the average user probably would only need one input device connected at any given time. This decoder chip switches between the strobe and data bit 7 of both devices. CPU support Only a few CPU signals remain to be explained. The main clock for the Z80 is generated by the 4.91MHz crystal oscillator employing transistor Q1. Its ouput signal is buffered and squared by gate E13b. The Reset signal for the 8255 requires a positive-going pulse while the CPU needs a negative-going pulse as generated by the reset switch S1. The 10k0 resistor R3 is a pullup which normally holds reset pin 26 high. When S1 is pressed, pin 26 is pulled low. The 22µF capacitor across the switch eliminates any contact bounce. The reset pulse from switch S1 is also fed to gate E13d which inverts the signal and feeds it to the 8255 reset, pin 35. Next month we will conclude the Message Board description with the assembly instructions and programming via the keyboard. ~