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1 gating time, sec 10 12B ,01 PER 1Mn/10 1 .1 . .m 12,8 1.28 ,128 DIGITAL FREQUENCY METER Build this superb ~ November, 1987 1GHz Digital Frequency Meter By STEVE PAYOR This superb 1GHz Digital Frequency Meter will outperform any other instrument in its price range. It uses the highest performance ICs, provides both frequency and period measurements, and features an 8-digit LED readout. 32 SILICON CHIP There is only one way to describe the performance of our new 1GHz Digital Frequency Meter - it's superlative! The design brief for this instrument was simple: it had to be the best DFM for its price available in Australia. It also had to include both frequency and period measurement modes, a frequency cycles counted 1000 i,ating time, sec 10 · ·· ' . :.: 10 . ·· ••····· .,.. · 1Z11,, · 12.8 l28 128 o,o,rAL FREtlUENtv MEren·• These two views show the new counter in period mode (left) and frequency mode [right). The unit is housed in an attractive plastic instrument case, with the LED displays hidden behind a red acrylic panel. Note kHz and µsec indicators. response to 1GHz, switchable gating times, and an 8-digit readout with switchable decimal points and overflow indication. And, as if that wasn't enough, the all-up kit price had to be kept to less than $300! It took a lot of doing, but we've managed to come up with a very refined design that beats the socks off anything else going. This design not only outperforms existing kit DFMs but also commercial units costing many times more. To meet our design objectives, we selected three key parts for the circuit: Intersil's ICM7216A LSI frequency counter, Motorola's MC10116 triple differential line driver, and Philips' SAB6456 1GHz divide-by-64 prescaler/amplifier. The ICM7216A counter IC was chosen because it contains all the circuitry necessary to count, generate gating signals, latch data, and drive an 8-digit multiplexed LED display. It also includes a highfrequency oscillator and control inputs for decimal point placement and gating time. The 10116 and SAB6456 ICs are used at the inputs of the 0-lO0MHz and 1GHz ranges respectively. Both are high-speed EGL devices and feature excellent sensitivity across their respective bandwidths around 20mV in the case of the 10116 and 10mV (max.) for the SAB6456. The 10116 has been around for a number of years and has been used as a 0-lO0MHz preamplifier in many commercial DFMs. The SAB6456 is a more recent device, originally designed as a switchable prescaler for use with UHF/VHF television tuners It has a guaranteed range of operation from 70-l000MHz. Three other EGL devices have also been used in the circuit: two 10131 dual-D flipflops which have been configured as divide-by-five and divide-by-two counters, and a 10100 three input NOR gate. Finally, a few inexpensive CMOS chips round out the IC count in our new DFM. These devices are used for frequency division and logic switching. Main features Let's take a look at some of the features of the unit. As seen from the front of the instrument, there are two groups of four pushbuttons: the RANGE buttons, which move the position of the decimal point, and the FUNCTION buttons which select the various period and frequency modes. Throughout the following circuit description, these buttons will be referred to as Rl, R2, R3, R4 and Fl, F2, F3 and F4 respectively. The RANGE buttons select the gating time when in frequency mode, and the number of cycles counted when in period mode. The FUNCTION buttons select the various operating modes: either period or three frequency ranges (0-l0MHz, 0-l00MHz or 10MHz-1GHz). Immediately below these pushbuttons are two BNC input sockets. One of these has an input impedance of 1MO shunted by 10pF and is used for period and frequency measurements up to 100MHz. ThesecondinputhasaninputimNOVEMBER 1987 33 10Hz-10DMHz(; INPUT . _ • 100MHz PREAMP AND SCHl,ITT TRIGGER 16Hz{;;::; INPUT':(' ,-, COUNTER ICM7216A LI DISPLAY TIMEBASE RATIO IC1 +64 FRED/PERIOD SWITCHING T Fig.1: this diagram shows the main circuit blocks of the counter. Signals applied to the 10Hz-100MHz input are amplified, and divided by 10 or fed direct to the base of a TIL level translator (Q2). Similarly, signals applied to the 1GHz input are divided by 128 before reaching Q2. Q2, in turn, clocks an Intersil ICM7216A counter IC which drives the LED display. pedance of 500 and is used for frequency measurements up to one gigahertz (1GHz). An interesting feature of the unit is the provision of four switchable gating times: .01, 0.1, 1 and 10 seconds for the 10Hz to 100MHz input, and 0.128, 1.28, 12.8 and 128 seconds for the 1GHz input. The gating time is simply the time over which measurements are made before the display is updated. A long gating time means a higher count and greater resolution, but the drawback is slow update times. Selectable gating times thus make for a more versatile unit. You can opt for high resolution or fast update time, or a compromise between the two, as the situation demands. In the period mode, the gating switches select the number of cycles counted before the reading is displayed - either 1, 10, 100 or 1000. This mode allows very accurate measurement of low frequency signals (ie, those below about lOkHz). As before, you can opt for high resolution, fast update time, or a compromise between the two. All readings are displayed direct1y in kilohertz (kHz) or microseconds (µsec) , depending on the mode selected. As you can see from the photographs, the display features both kHz and µsec indicators, together with LED indication of the mode selected. Another LED, situated in the top left-hand corner of the display, provides overflow indication. 34 SILICON CHIP Easy to build We've put a lot of work into making this unit easy to build so that the specs of your assembled kit will match those of the prototype. All parts, with the exception of the power supply components, are mounted on two printed circuit boards which are soldered together at rightangles by means of matching solder pads. A red acrylic panel fitted with a Scotchcal label is attached to the display PCB by means of the BNC input sockets. The whole assembly then slides into matching grooves in a compact plastic instrument box. A third PCB accommodates the power supply components and is mounted together with the transformer, on the rear panel. We did this so that heat-generating components, such as the power transformer and a voltage regulator IC, were as far away from the sensitive counter circuitry as possible. Circuit description Before getting down to details, it is interesting to note that only two logic families are used in this frequency meter: the aforementioned ECL (Emitter Coupled Logic) for the high-speed "front end" circuitry, and CMOS for the remainder. All the ICs are common types except for the 1GHz ECL prescaler (Philips SAB6456) and the main CMOS counter/display driver (Intersil ICM7216A). Another interesting feature is the complete elimination of front-panel wiring. This was made possible by using PCB-mounted pushbutton switches and by electronically switching signal paths. Normally, one would expect to see a bank of mechanically latched and interlocked pushbuttons, but here the mechanics have been replaced by CMOS logic circuitry. Viewed as a whole, the circuit is quite a jigsaw puzzle, so we will examine it one section at a time, starting with the inputs. The 0-lOOMHz input This input is used for period measurements to 0.4µs (2.5MHz) when function button Fl is pressed, and frequency measurements up to 100MHz. The input impedance is nominally lMO with protection against all but the worst overloads. Firstly, .any DC component of the signal is removed by the 0.047µF input coupling capacitor. The signal is then clipped by a pair of BAW62 high-speed silicon diodes in conjunction with a series 180k0 current-limiting resistor. Note: do not substitute other types here as these diodes have exceptionally low capacitance (lpF typ.) and a high current rating. To maintain a flat frequency response, the 180k0 resistor is shunted by an 18pF capacitor (Cl) which compensates for the stray capacitance to ground across the 820k0 resistor of about 4-5pF (due to the diodes and JFET Ql). A JFET source-follower (Ql) is us- a little daunting, but this is achieved with a standard EGL differential line receiver (10116) and careful circuit layout. Note: readers unfamilar with the internal circuitry of EGL should refer to the accompanying panel. The 10116 contains three differential amplifiers, each with complementary outputs. Also provided is a DC bias voltage, VBB (pin 11 ), which we have used to bias the inputs of the first stage (IC2b). The signal is capacitively coupled from the JFET buffer stage and, by keeping as much symmetry in the layout as possible, most of the noise picked up at this point is effectively cancelled by the balanced differential input. This is important because the proximity of the 8-digit multiplexed LED display makes for a very noisy environment. The DC balance of the first stage is adjusted by VRl. Since each in- ed to buffer the input signal, and the voltage gain of this stage is about 0.7. Not shown on the circuit diagram, but connected to the source of the JFET, is a small "guard" track which surrounds the input circuitry on the PCB. This helps to minimise the stray capacitance around the input components, and the net result is an effective circuit input capacitance of only 6pF. In practice, by the time we add an input socket and plug, it is closer to lOpF. 100MHz preamp This part of the circuit amplifies the incoming signal and converts it to a "clean" square wave suitable for the logic and counting circuitry. At first glance, the requirements of high gain and a frequency response flat to 100MHz may seem put draws approximately 13µA of bias current, this lkO multi-turn trimpot can shift the DC input voltage by ± 13mV. The voltage gain of the first stage is about seven. The second stage (IC2c) has some negative feedback to reduce its gain. This feedback is applied from one output to its corresponding inverting input by two 1000 resistors. If IC2c was an operational amplifier, it would have a gain of - 1 via the inverting input and + 2 via the non-inverting input, giving a total differential gain of three. But since the open loop gain is only seven (instead of practically infinity in the case of an op amp), the actual stage gain is closer to two. There are reasons for reducing the gain here. First, using all the available gain would make the circuit too sensitive. To give a good stable reading, a DFM must be able All About Emitter Coupled Logic +SV vcc vcc - - - - - - - - - - - - +sv --,---·- OUTPUT I OUTPUT l -7-...-- INPUT PULL-DOWN RESISTORS INPUT ov VEE ..._......._no~ffuT HIGH +4.3V f t + -=- =t:L CIRCUIT SYMBOL OR LOW OUTPUT +3.4V 50k 4mA - - - - - - - - - - - - - VEE OV i:3:r::R CIRCUIT SYMBOL Fig. 3 BASIC ECL LOGIC GATE Fig. 2 BASIC ECL DIFFERENTIAL AMPLIAER Emitter Coupled Logic (ECL) was one of the first forms of bipolar logic to be produced as monolithic integrated circuits, back in the early 1960s. Today, it is still the fastest form of logic available, with propagation delays of less than one nanosecond per gate quite common. The ECL 10,000 series ICs used in this project are slowed internally to make them less critical to use with normal circuit wiring. The propagation delay is 2ns and the rise and fall times have been slowed to 3.5ns. ECL ICs are normally designed to run from a -5.2V supply (VEE), t but they also work quite well from a +5V supply; ie, Vee= +5V and VEE= 0V. Fig.2 shows the basic structure of an ECL differential amplifier. Depending upon which input is at the higher voltage, either the left or the righthand transistor in the differential pair will be turned on and the voltage across its collector load will be about 0.9V while the collector of the other transistor will be at Vee. Each collector output is buffered by an emitter follower , which gives an output voltage swing between +3.4V (logic low) and +4.3V (logic high). An external pull-down resistor is required on each used output. Fig .3 shows how this basic structure is modified to form a logic gate. A number of transistors (one for each input) are connected in parallel on one side of the differential circuit, while the transistor on the other side is connected to an internally generated bias voltage (VBB) which is half-way between the high and low logic levels; ie, about +3.8V. When one or more of the inputs is taken above +3.8V, the current shifts from the right to the left hand side of the emitter-coupled circuit and the NOR output goes low, while the OR output goes high. NOVEMBER 1987 35 Altronics Will Deliver Any Of These Quality Products To Your Door Faster Than Any Other Australian Supplier Or Your Money Back (Within 24 Hours To Every Capital City and Suburbs - Allow Additonal 24 - 48 Hours For Country Areas) 11111111111111111 IllIIll II UIIIH II Hiil IIIIOII II IIIIIIIIIUlll llllllll lllllmmn Qlllllll III U1111111111111111Ill In Ill II Ill II Ill Ill Ill Ill Ill I1111111111111111 HI 1111111111111 . ,., Toroidal Power Transformers 31.! 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Two S.naor Input• Ultrasonic Movement Detector This Ultrasonic Movement Detector proviaes an open window etc. Connects directly to an any movement up to 3 metres within an an I ~ ;:; ::t: (") :z: n 0 t=: Cl) = I .,. µsec PERIOD .,. kHz FREQUENCY TO 100MHz FREQUENCY TO 1GHz 1 0 0 0 0 0 D 1 . Fl +128 +10 +1 +1 .011- FUNCTION LEDS 270{) 100MHz PREAMP AND SCHMITT TRIGGER 100{) . F2 . F3 .,. .,. F4 (CMOS) FROM PUSHBUTTDN LOGIC J 1N914 D9 1N914 .Jit ECL-CMOS TRANSLATOR ... 2N5485 B VIEWED FROM BELOW 2N4258 ~- +5V FRONT PANEL BOARD 4,t,.UB,, -- - - - - - - - - - - - 12~4 HLMP-2300 NOTCH--"'W 8C549 B F4 (ECL) GOD cOE E ·LJc s F3 14 +---+-'ll------t--➔----tl.....,_+5V .,. 470{! 1GHz FREQUENCY METER F1 .0R.F2 ,------t----.------t----------J-----------t-----,-+sv 04 1N914 10 10VW 10 .----+----,10VW+ Fig.4: the front panel circuitry. Signals from the 100MHz preamp (IC2) and 1GHz prescaler circuits (ICt) are fed to NOR gate IC3. The signals are then divided by counter stages IC4 and IC5, or fed direct to the base of level translator Q2. kHz kHz FREQUENCY TO 10MHz 0 0 D 1 0 0 0 1 .,. .01.I UNITS OVERALL PRE-SCALING DISPLAY DIVISION RATkl +64 1GHz PRESCALER MODE .,. .01I. IC1 SAB6456 SYNCHRONOUS +5 COUNTER .,. .01+ ,--------------------4....--4.________________________.,....__ r----t--t-----+SV FUNCTION INPUTS F1 F2 F3 F4 t' 10MHz-1GHz Cl 18pF 10131 .011 ..---------------+------------+5V Most of the counter circuitry is mounted on two PCBs which are soldered together at rightangles. This view shows the parts on the main counter PCB. The Intersil ICM7216A is at the right. to ignore the noise which is always present on the signal. The sensitivity we have chosen is about optimum for most audio and RF measurements without the need for an input attenuator. The second reason for using negative feedback has to do with maintaining the high-frequency performance, which will be discussed a little later. The third stage, IC2a, may appear similar to the second stage, but in this case the feedback is positive rather than negative. This means that IC2a functions as a Schmitt trigger rather than as a linear amplifier. The positive feedback around IC2a causes it to latch in either the 1 or O state when no signal is present. To toggle the output, the signal amplitude must exceed the hysteresis voltage which is about 450mV. By working backwards from the here, we can calculate the theoretical sensitivity of the instrument; ie. 450mV divided by 2 (second stage gain) divided by 7 (first stage gain) divided by 0.7 (JFET buffer) divided by 0.82 (input protection) = 56mV p-p, or 20mV RMS. Any noise signal with an amplitude of less than 56mV peak-to- peak will thus be ignored. At frequencies above 50MHz, the sensitivity of the Schmitt trigger is degraded somewhat by the phase shift (propagation delay) within the ECL amplifier. Thus, the positive feedback becomes less positive. At the same time, the negative feedback around the previous stage becomes equally less negative; ie. the gain of the second stage actually increases slightly. The serendipitous result is a relatively constant sensitivity up to around 100MHz, without the need for small "peaking" capacitors across the feedback resistors. Fig.6 shows the measured performance of one of the prototypes. The sensitivity was better than 20mV RMS over most of the frequency range, rising to around 90mV at 140MHz. The small "bumps" at 50Hz and 500Hz were caused by internal noise - from mains hum and the multiplexed digital display respectively. This noise slightly degrades the theoretical noise immunity, reducing the maximum amount of "ignorable" noise at the input socket from 56mV p-p to about 30mV p-p. A test point is provided at the output of IC2a for setting up and testing the above circuitry. The state of the Schmitt trigger can be monitored by plugging a 1.7V red LED into a pair of Molex pins on the PCB. The number of turns of trimpot VRl required to turn the LED on or off provides a convenient check of circuit operation. Following IC2a, the now digital signal is routed to the base of TTL level translator Q2 via one of two paths: either directly via ECL OR gate IC3d when Fl or F2 is selected, or via IC3b and a high-speed divideby-10 counter when function F3 is selected. The 1GHz input This input is used for frequency measurements from 10MHz to above 1GHz, and is selected by pressing function button F4. Surprisingly, this is one of the simplest parts of the circuit, thanks to the use of a Philips SAB6456 UHF prescaler (ICl). As mentioned above, this IC is normally intended for use in TV tuners where its function is to divide down the frequency of the local oscillator, as part of a frequency synthesiser circuit. Because it is designed to be driven by small-amplitude sinusoidal signals over a wide frequency range, it is ideal for our application. NOVEMBER 1987 39 ~ ~=- _ l z n :J:: ' -,!,- ~ 3 ,._J 1 µJ, 2 13 r:::-1, CONTROL I F4 ,i=,, ~ 0lfil.!£1!L_ 14 12 INPUT +5V T 9 s ~ 5 I 12 0 . in 11 7.8125Hz REFERENCE E C - , ◄• - - , I 1 I 7 ':' "!" .J.! r 1 ,!.It I~ If FUNCTION PUSHBUTTONS RATNJ ~ I a,!'!!! ~ .,. 10VWL 10 .,. ,I_ 1 ~F- . I ~ 2 3 _ 11' CE ,..._., -l R3,, I C b 11 g ! 8 I l d 1 4 1 __ J - J. I -' j I 7 I L:lr-1 a - - 4r::::-13 slo OUT ~ IN ____!ill_ 4r::::::::-,3 5 · j E N 240VAC '--<> Sl 13 c ~ ~ C f DP --1k§L .,!£l9!!.. 12 11 F4 12 11 POWER SUPPLY BOARD 1 , 01; 16VW 200 ·-r- - E DV t5V .,. -!!- ~ - s DP 018 8C549 Bfr C B 0.11;:i UT ~ t E .,. GND 7805 1"" IN • 1k 470D a\.!: 33D -- +5V p_ DP ~~c s _ DP :+ o.i _ y-IC11d ~11 D12 1 F3 101 - - - 111 ~ F2 1 F1 12 1or::::::-l11 4x1N4001 014 i.:.;_;;a.., _ __. 'lov :;: jo ~~ ~F" 2155A 7216A DECIMAL POINT SELECTION 5 ~ - Al IC1lb ~ 13 ~ d - p DP 8xHDSP-5501 ON FRONT~N~BOARD_ _ - 1-=jr - _ _._ _ _ _ _ _ _ ___, 1s L.:+:,J IC11c r-::::, 9 8 16 • L.:::,=-l B Jl...-.0 IC9c -~ IC10c I 8-DIGIT MULTIPLEXED DISPLAY ____icn_ - d L:l:J ~ 1s 15 ,--~--4--777---721 SE~mroN &A I - - ef_ fc ,-, I g b a .---4---+-J&--7777--_, ~ I •--3-----R4f: f 3 12 14 7 I. ~I. (: 1 0 1 RANGE PUSHBUTTONS R21,· 1 I ,1 • r l& 47k -~-■---■- 14 15 CK RESET ICl 2 4017 ON FRONT PANEL BOARD ____ - - · 1 R11 ·,' •..:PUSHBUTTON LATCHING 1M .022: 010{ 1N914 """ .,. 10VW ...J 1GHz FREQUENCY METER F2 F3 F4 FREQUENCY FREQUENCY FREQUENCY ,.. ---I---~-- - - - I' 16 15 RESE 47k IC13 4017 CE 13 1 2 3 7 4 O CK14 "":l:- I+ 10 .!!!! ------<1---,,-, - +5V ..---t----.---r--7--,.---, 500Hz t5V 1 4 +64 IC7 ,.J4 IN 4024 RESET 12 1& r-i: I a _ _ _ _ _ _ _ __. ....Jl!3i!,8--f3~,8~-J:3Wi.1L~-~3!,B'T"..J~3£BT_,a;:3:;::,B"i_,.;3:.B,_.._3,.,8, ._..;.._ _ _ _ _ _ _- - , I I I I 1 I 1 OVERFLOW ~---====1:.~======~1 I I 1 1 I LEDS (:,_ r HLMP-1301 '\ • :>,. - -- --- - - Fig.5: diagram showing the counter, display and power supply circuitry. Also shown is the latching circuitry for the function and range pushbuttons (IC8-12}. This section will be described next month. L I II C 500Hz • CLOCK _ T .01.I!'!!! ◄;Jo-______-..-:t~_-________ __ j PERIOD ' F1 , ..... - Bf r' E I ~ 016 BC549 4.7k ., ,. . ,._ 2.2k 1k '-.:::: L--' -______________ , 10k 15 . - - - - . - - - , - - 8 ;~ B r- dlj C-'L:c=====--------------t-nttrt=::il b 1 a 7 1 -:500Hz FILTERING ANO SHAPING • · I 0022 • lOk -:- I 100pF.I!'!!! • l DP 4 1 I I ==================--------11~•~~t=========---1 8 D7 ,1-6 15 D8 ::1;17 ll~ 19 I I ~------------------------==:t============================~--7 :::::::::::::::::::::::::::::::::::::::::::::~~~~~~l~~~~::::::::::::::::::::::::::::::::::::::::~::::: ;---7 3 1802i • 22 21 01~ltg 03 D4 20 I - ,..---l.---4---------~ L.:;;J F3•-...----+-, 4 . rJ F2 40111!..!n!!L 1r::-,2 1 .- 11P . F1 4016 IC9a - W 40 IC 11 +5V .,. lOOpFI. 10k IC& ~u 124 I ICM7216A INPUT A SC OUT .-!!HOLD 28 26 RESET ~◄►~-~-~~ :~ RANGE 0-1DMHz FROM FRONT PANEL BOARD 4-40pf 13 ovw.I,- 25 DSC IN pF 10MHz"T" 10M ::a - •• .l 39 "" - 100D~ 1 n 0 r=: Cf.J = lO0mV 70 w - c.:, ~ I I I I I r C1=15pF I 50 I 0 ...if> 30 :!:a ~ 20 r:c ------ 10mV 10Hz ...- l.---" V~ r--.. .__ V V 100Hz !kHz 10kHz I I/ lO0kHz 1MHz 10MHz 100MHz 200 FREQUENCY Fig.6: the measured sensitivity of the prototype was better than 20mV RMS over most of the range, rising to about 90mV at 140MHz. 1v.---------r----.------....-------r-----. SAB6456 - +---+-- - - - - - +- -+-- t - ---t w c.:, ~ 10mV 0 ...> ;;::, 11. :!:a en == r:c 100µV 1 - - - -- --+----+--- 50 - - - + ----+-+--- 100MHz 500 1GHz --1 2 FREQUENCY Fig.7: the SAB6456 has a guaranteed range of operation from 70-lO00MHz with a sensitivity of lOmV. Actual devices have a cutoff frequency of typically 1.7GHz. Pins 2 and 3 are differential ECL inputs, which are biased internally, so that the only external parts needed are two input coupling capacitors. These capacitors should ideally be leadless ceramic "chip" types, since the inductance of the leads on ordinary ceramic capacitors can be a problem at 1GHz. However, we have found that Philips miniature ceramic plate capacitors (2222-629 series) are useable, provided they are seated right down on the PCB, with an absolute minimum of lead length. Note: this applies to all the O.OlµF ceramic capacitors used throughout the circuit for highfrequency coupling and bypassing. No overload protection is provided on the 1GHz input since the usual pair of back-to-back diodes would provide too much of a capacitive load at 1GHz. In any case, most applications will not require a solid connection to this input. The sensitivity is very high, and according to the manufacturer's specifications, is guaranteed to be better than 10mV RMS from 70MHz to 1GHz (Fig.7). The typical input sensitivity at 1.2GHz is, in fact, a mere 50µV RMS, and the input will usually oscillate at this frequency when no signal is applied. In practice, this is of no consequence since the prescaler will stop oscillating when a valid signal is present. In fact, this self-oscillation provides us with a convenient way of checking the DFM operation on the 1GHz range - pressing the F4 button, with no input connected, should give a reading of around 1.2GHz. Note that the maximum input voltage for reliable counting is 300mV RMS. The input impedance is 5600 is parallel with 5pF at low frequencies, and 300 in parallel with 1.5pF at 1GHz. Inside the SAB6456 (ICl) is a binary counter which can be set to divide by 64 or 256, depending upon the mode control pin (pin 5). With pin 5 open circuit the division ratio is 64. What we would really like is a divide-by-10 or divide-by-100 prescaler, but such devices are quite expensive. Instead, we have managed to make do with the divide-by-64 option, followed by an additional divide-by-2 stage implemented with normal ECL circuitry. The fact that our 1GHz signal is divided by 128 instead of 100 does not cause any real problems, as will be shown next month. As shown in Fig. 7, the actual cutoff frequency for the SAB6456 is typically 1.7GHz. After dividing by 128, this leaves a signal of 13MHz for the ICM7216A counter chip. Since typical 7216 devices can count to 15MHz, our DFM can comfortably exceed its nominal 1GHz specification. The differential outputs of the SAB6456 are at pins 6 and 7 and the output voltage swing is typically from + 4V to + 5V. The addition of emitter follower stage Q3 to pin 7 gives us normal ECL signals and NOVEMBER 1987 41 PARTS LIST FOR 1GHz DFM 1 plastic instrument case, 200 x 160 x 70mm (W x D x H) 1 display PCB, code sc04 1-11 8 7 -1 , 1 94 x 61 mm 1 main counter PCB, code sc041-1187-2, 190 x 55mm 1 power supply PCB, code sc041-1187-3, 54 x 44mm 1 translucent red acrylic panel, 195 x 64 x 1 .5mm 1 Scotchcal label, 195 x 27mm 1 10MHz parallel AT-cut crystal 2 BNC panel sockets 8 momentary contact pushbutton switches 1 21 55 power transformer 1 push on/push off SPOT mains switch 1 mains cord and plug 1 cord clamp grommet 1 two-way mains terminal block 3 solder lugs 2 PC pin connectors 2 5mm metal standoffs 3 25mm 6BA screws and nuts 1 7mm dia. plastic plug (as used with mains sockets) 4 rubber feet Semiconductors 1 SAB6456 prescaler IC (Philips) 1 10116 ECL line driver 1 10100 ECL 3-input quad NOR gate 2 10131 ECL dual D flipflops 1 ICM7216A 10MHz universal counter 1 4024 7 -stage binary counter 4 4016 quad bilateral switches 2 401 7 decade counters 16 BC549 NPN transistors 1 2N4258 PNP transistor these are applied to pin 10 of IC3c which forms part of the signal path control logic. Control logic IC3 is a quad NOR gate, type 10100, which selects the appropriate signal routing. Pin 9 of this IC is a common enable input which is grounded, so that IC3a, b, c and d function as 2-input NOR gates. When button Fl (period) or F2 (frequency to 10MHz) is pressed, pin 13 of IC3d and pin 5 of IC3a go low. IC3a is used as an inverter, so 42 SILICON CHIP 1 2N5485 N-channel FET 3 BAW62 high-speed silicon diodes 4 1 N4001 silicon diodes 7 1 N914 silicon diodes 1 7805 5V 3-terminal regulator 8 common anode LED displays, Hewlett-Packard HDSP-5501 or equivalent 2 red light bar modules, Hewlett-Packard HLMP-2300 5 miniature red LEDs 1 red LED (for testing) Capacitors 1 2200µF 16VW axial electrolytic 1 1 OOOµF 1 6VW PC electrolytic 5 1 OµF tantalum 2 0.1 µF ceramic 15 0 .01 µF Philips miniature ceramic plate, type 2222-629 (0.2-inch lead spacing) 1 0 .047µF ceramic 1 0.022µF ceramic 1 0 .0022µF ceramic 1 1 OOpF ceramic 1 39pF NPO ceramic 1 1 8pF ceramic 1 4-40pF trimmer capacitor Resistors (0.25W, 5%) 2 x 1 OMO, 1 x 1 MO, 1 x 820k0, 1 x 180k0, 2 x 47k0, 3 x 10k0, 11 x 4 .7k0, 3 x 2.2k0 1%, 4 x 1k0, 15 X 4700, 2 X 2700, 1 X 1200, 4 X 1 000, 1 X 330, 1 X 1 kO multi-turn trimpot Miscellaneous Mains rated cable (32cm), hookup wire (50cm), heatshrink tubing. its output goes high and resets flipflop IC4b. At the same time, IC3d gates the signal from IC2a through to the EGL-CMOS level translator (Q2). Note that when two ECL gates share a common output pull-down resistor, either or both gates can take the output high, and so an OR function is obtained without using any extra gates. Thus, the EGLCMOS translator (Q2) can be driven by IC3d when the output of IC4b is low, and by IC4b when IC3d is low. When button F3 is pressed (fre- quency to 100MHz), we need to insert a divide-by-10 circuit. This is done in two stages: a divide-by-5 stage consisting of IC5a, IC5b and IC4a, and a divide-by-2 stage consisting of IC4b. Before we discuss how the divide-by-5 and divide-by-two counters work, note that IC4 and IC5 are dual D flipflops, with two clock inputs per flipflop which are ORed together. Pin 9 is a common clock input for both flipflops, while pins 6 and 11 are separate clock inputs. Either input can be used to clock the flipflop, provided the other is taken to a logic 0, or grounded. The D flipflops operate as follows: when the clock input goes to a logic 1, the data present at the D input is latched by the flipflop and appears at the Q output. The divide-by-5 counter This is a synchronous counter. All three flipflops (IC5b, IC5a and IC4a) are clocked simultaneously from the 100MHz Schmitt trigger output via IC3b. When the counter is not needed, it is stopped by applying a logic 1 to the Reset input (pin 4) of IC4a. However, if F3 is pressed, pin 4 of IC4a goes low and the counter functions again. The three flipflops are connected to operate as a shift register; ie, each input is connected to the output of the previous flipflop. The input to the first flipflop, however, is connected to the OR of the Q-bar outputs of the last two stages. This gives a count sequence which divides the clock signal by 5. The divide by two counter (IC4b) is wired with the Q-bar output connected to the D input. This means that each cycle of the clock signal causes the flipflop to toggle and so provide a divide-by-two function. As before, the counter is stopped by applying a logic 1 to its Reset input (pin 13). Now let us look at the function button logic which involves ten transistors from Q4 to Q14. This part of the circuit controls the signal switching to the EGL-CMOS translator (Q2). Normally, Q4 to Q6 are on while Q7-Q14 are off. Let's say that function button Fl is pressed [ie, period mode is Electronic switching means that internal wiring has been kept to an absolute minimum. Matching slots at the front of the case accept the main PCB and front panel assembly, while power supply components are mounted on the rear panel. selected). When this happens, the Fl line is latched high by IC13 (4017) and so transistors Q7 and Q8 are turned on. This then turns on LED 4 and LED 2 which are the period mode and µsec display indicators respectively. QB also controls Q4 via diode D9. Normally, Q4 is turned on by its 4.7k0 base resistor and pin 13 of IC3d and pin 5 of IC3a are both held high. When Flis pressed, however, QB turns on and pulls Q4's base low via D9. Q4 thus turns off and pin 13 of IC3d and pin 5 of IC3a are pulled low by Q4's 4.7k0 emitter resistor. IC3d is now enabled and gates the signal from the 100MHz preamp through to the base of the ECLCMOS level translator (Q2), as discussed previously. Note that, during this time, IC4b is held reset by the high on the out- put [pin 2) of IC3a, while IC4a is held reset by Q5 which is on. Thus, the divide-by-5 and divide-by-2 counters are disabled. Q6 is also on and disables IC3c which controls the signal routing for the 1GHz input. If F2 (10MHz) is now pressed, Q7 and QB turn off and Q9 and QlO turn on. This turns on LED 5 and LED 3 [via D5) which are the mode and kHz indicators respectively. Q4 is again turned off, this time via DB, and so IC3d again gates through the signal from IC2a to the base of QZ. If F3 (100MHz) is pressed, Ql 1 and Q12 are turned on and light LED 6 and LED 3 (via D6). Q12 also turns off Q5 which releases the reset on IC4a and thus enables the divide-by-5 counter. At the same time, pin 2 of IC3a goes low and enables IC4b. As a result, signals from the 100MHz preamp are now gated via IC3b and pass through the divide-by-5 and divide-by-2 stages before being fed to the ECL-CMOS translator. Finally, when F4 (1GHz) is pressed, LED 7 and LED 3 light and Q6 is turned off by Q14. Q5 is on and so IC4a will now be disabled. The divide-by-2 counter [IC4b) , however, will still be enabled by the low on pin 2 of IC3a. Thus, when F4 is selected, signals from the 1GHz divide-by-64 prescaler are gated by IC3c and fed to the divide-by-2 counter [IC4b). That's all we have space for this month. When we resume next month, we'll describe the counter circuitry and the latching circuitry for the pushbutton switches. In addition, we'll give you all the construction details. N OVEMBER 1987 43